CN116128703A - Graphics processor, chip, and electronic device - Google Patents

Abstract

The application provides a graphics processor, a chip and an electronic device. The graphics processor comprises at least two data and command distributors and at least two graphics processor cores, wherein each data and command distributor is connected with at least one graphics processor core, and one data and command distributor is connected with one graphics processor core through a group of data and command transmission lines; the graphics processor is configured to provide at least one virtual graphics processor, each of the virtual graphics processors including one of the data and command distributors and some or all of the graphics processor cores coupled thereto. The graphics processor is capable of providing at least one virtual graphics processor that is virtualized such that the graphics processor is commonly used by multiple users.

Description

Graphics processors, chips and electronic equipment

technical field

The present application belongs to the technical field of processors, and relates to a graphics processor, in particular to a graphics processor, a chip and electronic equipment.

Background technique

Graphics processing unit (GPU), also known as display core, visual processor, and display chip, is a graphics processing unit that is specially designed for processing on personal computers, workstations, game consoles, and some mobile devices (such as tablets, smartphones, etc.). Microprocessor for image and graphics related operations. The GPU reduces the graphics card's dependence on the central processing unit (CPU) and completes part of the original CPU's work.

The number of graphics processors in an electronic device is usually relatively limited. In order to more efficiently use the limited graphics processor resources to better meet user needs, a graphics processor virtualization technology emerges as the times require. Graphics processor virtualization requires that an actual graphics processor be virtualized into multiple virtual graphics processors to accommodate simultaneous use by multiple users. Each user uses one virtual GPU, and each virtual GPU can use one or more GPU cores. However, in existing graphics processor virtualization technologies, the graphics processor cores used by each virtual graphics processor are often fixed, and it is difficult to flexibly configure them according to actual needs.

Contents of the invention

The present application provides a graphics processor, a chip, and an electronic device. In the graphics processor, the graphics processor core included in each virtual graphics processor can be configured according to actual requirements.

In a first aspect, an embodiment of the present application provides a graphics processor, the graphics processor includes at least two data and command distributors and at least two graphics processor cores, each of the data and command distributors communicates with at least one of the The graphics processor core is connected, wherein, one of the data and command distributors is connected to one of the graphics processor cores through a set of data and command transmission lines; the graphics processor is configured to provide at least one virtual graphics processing Each of the virtual graphics processors includes a data and command distributor and part or all of the graphics processor cores connected thereto.

In an implementation manner of the first aspect, the graphics processor is configured to provide n virtual graphics processors according to the received instruction, where n is any positive integer less than or equal to N, and N is the The number of GPU cores.

个所述图形处理器内核相连，其中i和ni均为小于或等于N的正整数，floor为向下取整函数。In an implementation manner of the first aspect, the i-th data and command distributor of the graphics processor and

Two graphics processor cores are connected, wherein i and ni are both positive integers less than or equal to N, and floor is a function of rounding down.

个所述图形处理器内核相连，mj和mj+1为相邻的能够被N整除的正整数，1≤mj+1＜mj≤N。In an implementation manner of the first aspect, the graphics processor includes N data and command distributors, and one of the data and command distributors is connected to N cores of the graphics processor, wherein mj-mj+1 the data and command distributors with

Two graphics processor cores are connected, mj and mj+1 are adjacent positive integers divisible by N, 1≤mj+1<mj≤N.

In an implementation manner of the first aspect, the graphics processor further includes a data selector, and the graphics processor cores connected to at least two of the data and command distributors communicate with the data Connect to command dispatcher.

In an implementation manner of the first aspect, the number of the data and command distributors and the number of the graphics processor cores are eight, and the connection mode of the data and command distributors and the graphics processor cores includes 1 one-to-eight connection, 1 one-to-four connection, 2 one-to-two connections, and 4 one-to-one connections.

In an implementation manner of the first aspect, the number of physical layers of the graphics processor is configured according to the number of data and command transmission lines.

In an implementation manner of the first aspect, the data and command distributor is fully connected to the graphics processor core.

In a second aspect, an embodiment of the present application provides a chip, the chip including the graphics processor described in any implementation manner of the first aspect of the present application and input and output pins.

In a second aspect, an embodiment of the present application provides an electronic device, where the electronic device includes the graphics processor and the memory described in any implementation manner of the first aspect of the present application.

The graphics processor provided by the embodiment of the present application can provide at least one virtual graphics processor, and the graphics processor core contained in each virtual graphics processor can be configured according to actual needs. Therefore, in specific applications, the virtual graphics processor can be configured according to actual needs The graphics processor core included in the processor can be flexibly configured.

In some embodiments of the present application, by optimizing the connection mode between the data and command distributor and the graphics processor core, the number of connections between the data and command distributor and the graphics processor core can be reduced, avoiding chip layout The congestion problem in the wiring (Place and Route, P&R) stage is conducive to reducing the chip area. In addition, in some embodiments, the number of layers of the physical layer of the graphics processor is configured according to the number of data and command transmission lines. In these embodiments, the number of graphics processor physical layers can be reduced by optimizing the wiring between the data and command dispatcher and the graphics processor core.

Description of drawings

Figure 1 shows a schematic diagram of the structure of an electronic device.

FIG. 2 shows a schematic diagram of the structure of a graphics processor.

FIG. 3A shows a schematic structural diagram of a graphics processor provided by an embodiment of the present application.

FIG. 3B is a schematic diagram of the connection relationship between the data and command distributor and the graphics processor core in an embodiment of the present application.

FIG. 4 shows a schematic structural diagram of a graphics processor provided by an embodiment of the present application.

5A and 5B are schematic structural diagrams of a graphics processor provided by an embodiment of the present application.

FIG. 5C is a schematic structural diagram of a graphics processor provided by an embodiment of the present application.

FIG. 6 shows a schematic structural diagram of a graphics processor provided by an embodiment of the present application.

FIG. 7 shows a schematic structural diagram of a chip provided by an embodiment of the present application.

Component designation description

100 Electronic equipment

110 System Processor

120 graphics processor

121-1～121-k graphics processor core

122 Configure command processor

123 Crossbar bus

124-1～124-k L2 cache

130 memory

140 display screen

300 Graphics Processor

310-1～310-M Data and command distributor

330-1～330-N graphics processor core

500 Graphics Processor

510-1～510-8 Data and command distributor

520-2～520-8 data selector

530-1～530-8 graphics processor core

Detailed ways

Embodiments of the present application are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

In this application, terms such as "installation", "connection", "connection" and "fixation" should be interpreted in a broad sense, for example, it can be a fixed connection or a detachable connection, unless otherwise clearly specified and limited. , or integrated; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific situations.

It should be noted that the diagrams provided in the following embodiments are only schematically illustrating the basic idea of the application, and only the components related to the application are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

The following embodiments of the present application provide a graphics processor, and its application scenarios include but not limited to electronic devices. The electronic device may be a mobile phone, a tablet computer, a personal computer (personal computer, PC), a personal digital assistant (personal digital assistant, PDA), a smart watch, a netbook, a wearable electronic device, an augmented reality (augmented reality, AR) device, Different types of electronic devices such as virtual reality (VR) devices, vehicle-mounted devices, smart cars, smart speakers, robots, and smart glasses.

Please refer to FIG. 1 , which is a schematic structural diagram of an electronic device 100 in an embodiment of the present application. The electronic device 100 includes a system processor 110 (eg, may be a CPU), a graphics processor 120 , a memory 130 and a display screen 140 .

In specific operations, the system processor 110 may boot into an operating system (operation system, OS) to provide various operations of the user system, including user applications, data processing services, communication services, storage services, game services, or other operations. The graphics processor 120 may provide operations such as graphics processing, rendering services, and enhancements for the system processor 110 . Specifically, referring to FIG. 2 , the graphics processor 120 provides a graphics processor core (for example, 121-1, 121-2, ..., 121-k), a configuration command processor 122, a crossbar (crossbar) bus 123, etc. The operation of the component, where k is a positive integer. It can be understood that operations such as graphics processing, rendering service, and enhancement can be performed by one or more functional modules of the graphics processor core 120 , for example, one functional module of the graphics processor core 120 can correspondingly complete one operation. Wherein, in FIG. 1 , the graphics processor 120 may be a separate component connected to the system processor 110 through the communication line 150 , but it should be understood that the graphics processor 120 may also be integrated into the system processor 110 in other examples.

Memory 130 may include random access memory (random access memory, RAM), a cache memory device, or other volatile memory elements employed by system processor 110 or graphics processor 120 . Wherein, other volatile memory components adopted by the graphics processor 120 include caches that may be integrated into the graphics processor 120, for example, the second-level (L2) caches 124-1, 124-2, . . . , 124 in FIG. 2 -k. The memory 130 may also include a non-volatile memory element, such as a hard disk drive (hard disk drive, HDD), a flash memory device, a solid state drive (solid state drive, SSD), or store an operating system, application or Other memory devices for other software or firmware.

Electronic devices 100 may communicate via one or more communication links, such as one or more network links. For example, a communication link may use metal, glass, optical, air, space, or some other material as the transmission medium. Example communication links may use various communication interfaces and protocols, such as internet protocol (internet protocol, IP), Ethernet, universal serial bus (universal serial bus, USB), bluetooth (bluetooth), WiFi or other communication signaling or Communication formats, including combinations, modifications or variations thereof. Communications links can be direct links, or can include intervening networks, systems, or devices, and can include logical network links transported over multiple physical links.

Electronic device 100 may include software such as operating systems, logs, databases, utilities, drivers, networking software, user applications, data processing applications, game applications, and other software stored on computer-readable media. The software of the electronic device 100 may include one or more platforms hosted by a distributed computing system or cloud computing service. The software of the electronic device 100 may include logical interface elements, such as software-defined interfaces and application programming interfaces (APIs).

Software of the electronic device 100 may be used to generate data to be rendered by the graphics processor 120 and to control the operation of the graphics processor 120 to render graphics for output to one or more display screens 140 for display.

System processor 110 , graphics processor 120 , memory 130 and display screen 140 may communicate via coupled communication line 150 . Example communication lines 150 may use metal, glass, optical, air, space, or some other material as a transmission medium. Communications link 150 may use various communication protocols and communication signaling, such as a computer bus, including combinations or variations thereof. Communications link 150 may be a direct link, or may include intervening networks, systems, or devices, and may include logical network links transported over multiple physical links.

FIG. 2 shows an example of a graphics processor 120 in the embodiment of the present application. As shown in FIG. 2 , the graphics processor 120 specifically includes a plurality of graphics processor cores 121-1, 121-2 ... 121-k, a configuration command processor 122, a crossbar switch bus 123, and a plurality of L2 caches 124-1, 124-2, 124-3...124-k. The crossbar bus 123 is connected between the graphics processor core and the L2 cache, and is used to provide a channel for the graphics processor core to access the L2 cache, and a channel for the L2 cache to return data to the graphics processor core. In addition, the L2 cache is also connected to the external memory 130 through a memory interface (memory interface, MIF).

Under the architecture provided by the embodiment of this application, the system processor 110 prepares the tasks and data for the graphics processor 120 to run, and sends them to the graphics processor core in the form of command configuration, and the configuration command processor 122 receives the system processor The command issued by 110 parses out the task, and directly issues it to the graphics processor core, and the graphics processor core starts to execute the task. Wherein, the task can also be sent to the memory 130 by the configuration command processor 122 through the crossbar bus 123 , and the task can be read from the memory 130 by the graphics processor core and processed.

The specific process for the graphics processor core to execute the task includes: the graphics processor core reads task-related external data from the memory 130 , processes and writes the data. Since the graphics processor core is multi-threaded (thread) processing, that is, one instruction processes a batch of data, in order to reduce the data fetching and data storage delay of the graphics processor core and improve the processing efficiency of the graphics processor core, a typical design will be in the graphics processing An L2 cache is placed between the processor core and the memory 130, a large amount of data is prefetched and cached through the L2 cache, and the waiting time of the graphics processor core is reduced.

The technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings in the embodiments of the present application.

FIG. 3A is a schematic structural diagram of a graphics processor 300 in an embodiment of the present application. As shown in FIG. 3A , the graphics processor 300 includes M data and command distributors (dispatchers) 310-1 to 310-M, and N graphics processor cores (clusters) 330-1 to 330-N, wherein M and N is a positive integer greater than or equal to 2, and each GPU core includes a set of graphics processing pipelines. In some implementation manners, the values of M and N may be the same, and in other implementation manners, the values of M and N may also be different. Each data and command distributor can be connected to at least one graphics processor core, and can be connected to N graphics processor cores at most. Among them, the connection mode between the data and command distributor and the graphics processor core includes, but is not limited to, the data and command distributor is directly connected to the graphics processor core, or the data and command distributor is indirectly connected to the graphics processor core through a data selector, etc. connected. A data and command distributor is connected to a graphics processor core through a set of data and command transmission lines, and each set of data and command transmission lines is, for example, a set of 1000-2000 data and command transmission lines.

In the embodiment of the present application, the graphics processor 300 is used to provide at least one virtual graphics processor, and each virtual graphics processor includes a data and command distributor and part or all of the graphics processors connected to the data and command distributor kernel. For example, the data and command distributor 310-1 in the graphics processor 300 shown in FIG. 3A and the graphics processor cores 330-1 and 330-N connected thereto can provide a virtual graphics processor, and the data and command distributor 310- 2 and its associated GPU core 330-2 may provide another virtual GPU.

In some implementations, the graphics processor can provide multiple virtual graphics processors at the same time, and each virtual graphics processor can include multiple graphics processor cores, and each graphics processor core is only included in one virtual graphics processor . Each user can use one virtual GPU, and each GPU core can only be used by one user at a time.

Optionally, FIG. 3B is a schematic diagram showing a connection relationship between the data and command distributor and the graphics processor core in the embodiment of the present application. Taking the data and command distributor 310-1 as an example, it uses an advanced extensible interface protocol (advanced extensible interface, axi) and an advanced high performance bus (advanced high performance bus, ahb) interface (host interface, HI). Synchronous dynamic random access memory (double data rate, DDR) is connected. Among them, the Advanced Extensible Interface Protocol is a bus protocol, corresponding to an on-chip bus oriented to high performance, high bandwidth, and low delay. The advanced scalable interface protocol can enable the system on chip (system on chip, SoC) to obtain more excellent performance with smaller area and lower power consumption. The advanced high-performance bus is a high-performance bus, which is mainly used for the connection between high-performance modules. Its main features include single clock edge operation, non-tri-state implementation, and support for burst transmission. The graphics processor core 330-1 includes a shader (shader) module, a transformation feedback (transform feedback, TFB) module, a position primitive assembly (position primitive assembly, PPA) module, a final basic assembly (final primitive assembly, FPA) module, a pixel Engine (pixel engine, PE) module and other modules. Among them, the final basic component module is used to write out the intermediate results to the memory. The positioning primitive component is used to perform culling operations such as triangle back face culling and zero area culling. The FPA module is used to perform viewport frustum transformation, and the pixel engine module is used to perform operations such as alpha blending on pixels.

According to the above description, it can be seen that the graphics processor provided by the embodiment of the present application can provide at least one virtual graphics processor for a user, and the graphics processor can be shared by multiple users through virtualization of the graphics processor.

According to an embodiment of the present application, the graphics processor is configured to provide n virtual graphics processors according to the received instruction, where n is any positive integer less than or equal to N, and N is the number of graphics processor cores, where Numerical values can be 4, 8, 16, etc., for example. Optionally, the n virtual graphics processors include all N graphics processor cores, but this application is not limited thereto.

个图形处理器内核相连，其中i和n_i均为小于或等于N的正整数，floor为向下取整函数。请参阅图4，以N＝4为例，图形处理器400的第1个数据和命令分发器410-1连接1个图形处理器内核430-1(n₁＝3)，第2个数据和命令分发器410-2连接4个图形处理器内核430-1至430-4(n₂＝1)，第3个数据和命令分发器410-3连接两个图形处理器内核430-1和430-3(n₃＝2)，第4个数据和命令分发器410-4连接两个图形处理器内核430-2和430-4(n₄＝2)。本申请实施例中，数据和命令分发器与图形处理器内核的连接方式，包括但不限于数据和命令分发器与图形处理器内核直接相连，或者数据和命令分发器通过数据选择器等与图形处理器内核间接相连。In one embodiment of the present application, the i-th data and command dispatcher of the graphics processor and

Graphics processor cores are connected, where i and _ni are positive integers less than or equal to N, and floor is a function of rounding down. Please refer to FIG. 4, taking N=4 as an example, the first data and command distributor 410-1 of the graphics processor 400 is connected to a graphics processor core 430-1 (n ₁ =3), the second data and command Command distributor 410-2 is connected to 4 graphics processor cores 430-1 to 430-4 (n ₂ =1), and the third data and command distributor 410-3 is connected to two graphics processor cores 430-1 and 430 -3 (n ₃ =2), the 4th data and command distributor 410-4 connects two graphics processor cores 430-2 and 430-4 (n ₄ =2). In the embodiment of the present application, the connection mode between the data and command distributor and the graphics processor core includes but not limited to the direct connection between the data and command distributor and the graphics processor core, or the connection between the data and command distributor and the graphics processor through a data selector, etc. The processor cores are connected indirectly.

The graphics processor 400 shown in FIG. 4 may be configured to provide 1 to 4 virtual graphics processors according to received instructions. When the GPU is configured to provide 1 virtual GPU, the user can use 4 GPU cores 430-1 to 430-4 through the data and command distributor 410-2. When the GPU is configured to provide two virtual GPUs, the first user can use the GPU cores 430-1 and 430-3 through the data and command distributor 410-2, and the second user can use the data and command distributor 410-2 And command dispatcher 410-4 uses graphics processor cores 430-2 and 430-4. When the GPU is configured to provide 3 virtual GPUs, the first user can use the GPU core 430-1 through the data and command distributor 410-1, and the second user can use the data and command distributor 410-1 410-2 uses graphics processor cores 430-2 and 430-4, and the third user can use graphics processor core 430-3 through data and command distributor 410-3. When the graphics processor is configured to provide 4 virtual graphics processors, the first user can use the graphics processor 430-1 through the data and command distributor 410-1, and the second user can use the data and command distributor 410 -2 uses the graphics processor 430-2, the third user can use the graphics processor 430-3 through the data and command distributor 410-3, and the fourth user can use the graphics processor through the data and command distributor 410-4 430-4.

According to the above description, it can be seen that the connection between the data and command distributor and the graphics processor core in the embodiment of the present application is simplified as one one-to-four connection (a total of 1×4 group connections), two one-to-two connections ( A total of 2 × 2 groups of connections), and a one-to-one connection (a total of 1 × 1 group of connections), so in the embodiment of the present application, there are a total of 9 groups of connections between the data and command distributor and the graphics processor core. Compared with the method of full connection between the data and command distributor and the graphics processor core, the connection method provided by the embodiment of the present application requires fewer connections, which is beneficial to avoid the congestion problem in the P&R stage and reduce the chip area.

It should be understood that, when N=4 shown in FIG. 4 , the connection manner between the data and command distributor and the graphics processor core is only a feasible manner of the embodiment of the present application, but the present application is not limited thereto. In some implementations, the graphics processor cores to which the data and command distributors are connected may be different from those shown in FIG. Distributor 410-3 may not connect 430-1 and 430-3 but connect 430-2 and 430-4. In other implementations, the number of graphics processor cores connected to the data and command distributor may be different from that in Figure 4, for example, the data and command distributor 410-1 may be connected to 2, 3 or 4 graphics processor cores , the data and command distributor 410-2 can be connected to 1, 2 or 3 GPU cores.

It should be noted that, in order to improve core utilization efficiency, in the above example, all virtual graphics processors provided by the graphics processor at the same time use all 4 graphics processor cores, but the present application is not limited thereto. For example, when the GPU 400 is configured to provide only one virtual GPU, the user can use the two GPU cores 430-1 and 430-3 through the data and command distributor 410-2, and the other two graphics processors Processor cores 430-2 and 430-4 are in an idle state. For another example, when the graphics processor 400 is configured to provide two virtual graphics processors, the first user can use one graphics processor core 430-1 through the data and command distributor 410-1, and the second user can use Two graphics processor cores 430-2 and 430-4 are used by the data and command distributor 410-4, and the other one graphics processor core 430-3 is in an idle state.

个图形处理器内核相连，m_j和m_j+1为相邻的能够被N整除的正整数，1≤m_j+1＜m_j≤N。例如，N＝4时m_j和m_j+1的数值包括两种：m_j+1＝1且m_j＝2，m_j+1＝2且m_j＝4。基于此，本申请实施例提供的图形处理器包含4个数据和命令分发器时，其中的1个数据和命令分发器与4个图形处理器内核相连，其中的另1个数据和命令分发器与2个图形处理器内核相连(m_j+1＝1且m_j＝2)，其中的另外两个数据和命令分发器各自与1个图形处理器内核相连(m_j+1＝2且m_j＝4)。本申请实施例中，数据和命令分发器与图形处理器内核的连接方式，包括但不限于数据和命令分发器与图形处理器内核直接相连，或者数据和命令分发器通过数据选择器等与图形处理器内核间接相连。In an embodiment of the present application, the graphics processor includes N data and command distributors, one of which is connected to N graphics processor cores, and m _j -m _j+1 data and command dispatcher with

Two graphics processor cores are connected, m _j and m _j+1 are adjacent positive integers divisible by N, and 1≤m _j+1 <m _j ≤N. For example, when N=4, the values of m _j and m _j+1 include two types: m _j+1 =1 and m _j =2, and m _j+1 =2 and m _j =4. Based on this, when the graphics processor provided by the embodiment of the present application includes 4 data and command distributors, one of the data and command distributors is connected to the 4 graphics processor cores, and the other one of the data and command distributors It is connected to 2 graphics processor cores (m _j+1 =1 and m _j =2), and the other two data and command distributors are connected to 1 graphics processor core each (m _j+1 =2 and m _j = 4). In the embodiment of the present application, the connection mode between the data and command distributor and the graphics processor core includes but not limited to the direct connection between the data and command distributor and the graphics processor core, or the connection between the data and command distributor and the graphics processor through a data selector, etc. The processor cores are connected indirectly.

Next, the above connection schemes will be described in detail by taking N=8 and N=16 as examples respectively. Referring to FIG. 5A , in an example, N=8, and the graphics processor 500 includes 8 data and command distributors. One of the data and command distributors 510-1 is directly connected to the graphics processor core 530-1, and is indirectly connected to the graphics processor cores 530-2 to 530-8 through a data selector. One of the data and command distributors 510-5 is indirectly connected to the four GPU cores 530-5 to 530-8 through data selectors (m _j+1 =1, m _j =2). For the two data and command distributors 510-3 and 510-7, the data and command distributor 510-3 is indirectly connected to the two graphics processor cores 530-3 and 530-4 through a data selector, and the data and command The distributor 510-7 is indirectly connected to the two GPU cores 530-7 and 530-8 through a data selector (m _j+1 =2, m _j =4). The four data and command distributors 510-2, 510-4, 510-6 and 510-8 are respectively connected with the corresponding graphics processor cores 530-2, 530-4, 530-6 and 530-8 through data selection devices are indirectly connected (m _j+1 =4, m _j =8).

The graphics processor 500 shown in FIG. 5A can be configured to provide 1 to 8 virtual graphics processors, which can support 1 user at least (when the graphics processor 500 is configured to provide 1 virtual graphics processor), and can support at most 8 users (when the GPU 500 is configured to provide 8 virtual GPUs). The graphics processor cores of the graphics processor 500 have 22 possible assignments, as shown in Table 1 below. For example, in the tenth case, the graphics processor 500 is configured to provide 3 virtual graphics processors for 3 users, wherein two users occupy 3 graphics processor cores, and the other user occupies 2 graphics processor cores. In combination with FIG. 5A, the allocation scheme of the graphics processor cores can be that the first user occupies the graphics processor cores 530-1, 530-2 and 530-8, and the second user occupies the graphics processor cores 530-5 and 530-6. and 530-7, the third user occupies graphics processor cores 530-3 and 530-4.

It should be noted that the connection manner between the data and command distributor and the graphics processor core in the embodiment of the present application is not unique, and other connection manners may also be used in some other implementation manners. For example, FIG. 5B shows another connection scheme when N=8, and this scheme has the same effect as the connection scheme shown in FIG. 5A.

Table 1. Distribution of the number of cores of the graphics processor 500

In the above example, the connection between the data and command distributor and the GPU core is simplified as 1 one-to-eight connection (a total of 1×8 group connections), one one-to-four connection (a total of 1×4 group connections). line), 2 one-to-two connections (a total of 2×2 group connections), and 4 one-to-one connections (a total of 4×1 group connections), so in the embodiment of the application, the data and command distributor and the graphics processing A total of 20 sets of connections between the cores. Wherein, each group of connections is, for example, a group of 1000-2000 data and command connections. Compared with the method of full connection between the data and command distributor and the GPU core, the connection method provided in this example requires fewer connections, which is beneficial to avoid the congestion problem in the P&R stage and reduce the chip area.

Please refer to FIG. 5C , in another example, N=16, the graphics processor includes 16 data and command dispatchers. The first data and command distributor is directly connected to the first graphics processor core, and indirectly connected to the remaining 15 graphics processor cores through data selectors. Among them, the ninth data and command distributor is indirectly connected to the eight graphics processor cores through the data selector. Among them, the second data and command distributor is indirectly connected to the five graphics processor cores through the data selector. Among them, the seventh data and command distributor is indirectly connected with the four graphics processor cores through the data selector. Among them, the 16th data and command dispatcher is indirectly connected with the 3 graphics processor cores through the data selector. Among them, the 4th, 11th and 13th data and command distributors are indirectly connected to the two graphics processor cores through data selectors. Among them, the 3rd, 5th, 6th, 8th, 10th, 12th, 14th, and 15th data and command distributors are indirectly connected to 1 graphics processor core through data selectors connected. In this example, the connection between the data and command dispatcher and the graphics processor core is simplified as 1 one-to-sixteen connection (a total of 1×16 groups of wires), one pair of eight connections (a total of 1×8 groups of wires) connection), 1 one-to-five connection (a total of 1×5 groups of connections), 1 one-to-four connection (a total of 1×4 groups of connections), 1 one-to-three connection (a total of 1×3 groups of connections ), 3 one-to-two connections (a total of 3 × 2 group connections), and 8 one-to-one connections (a total of 8 × 1 group connections), so in the embodiment of the application, the data and command distributor and the graphics processor There are a total of 50 sets of connections between the cores. Compared with the method of full connection between the data and command distributor and the GPU core, the connection method provided in this example requires fewer connections, which is beneficial to avoid the congestion problem in the P&R stage and reduce the chip area.

In an embodiment of the present application, the graphics processor may further include a data selector. Graphics processor cores connected to at least two data and command distributors are indirectly connected to the data and command distributors through data selectors. For example, the graphics processor 500 shown in FIG. 5A includes data selectors 520-2 to 520-8. For a graphics processor core connected to at least two data and command distributors, such as graphics processor core 530-5, it is indirectly connected to the corresponding data and command distributor through a data selector. In the embodiment of the present application, the data selector selects at most one data and command distributor to connect to the graphics processor core at the same time.

Optionally, for a graphics processor core that only needs to be connected to one data and command distributor, such as graphics processor core 530-1, it may not be connected to the data and command distributor through a data selector.

It should be understood that the data selector described in the embodiment of the present application includes all devices or circuits capable of selecting and outputting a specified signal from a group of input signals, rather than being limited to a specific device or circuit. In one embodiment of the present application, the data and command dispatcher is fully connected to the GPU core. Wherein, full connection means that each data and command distributor is connected to all graphics processor cores, and each graphics processor core is connected to all data and command distributors. Among them, the connection mode between the data and command distributor and the graphics processor core includes, but is not limited to, the data and command distributor is directly connected to the graphics processor core, or the data and command distributor is indirectly connected to the graphics processor core through a data selector, etc. connected. Figure 6 shows an example diagram of the full connection between the data and command distributor and the graphics processor core when N=8, at this time, the graphics processor can be configured to provide 1 to 8 virtual graphics processors, and can satisfy all allocations.

In an embodiment of the present application, the number of physical layers of the graphics processor is configured according to the number of data and command transmission lines. Specifically, there is a maximum limit on the number of data and command transmission lines contained in each physical layer of the graphics processor, and the fewer the number of data and command transmission lines, the fewer layers of the physical layer of the graphics processor. Taking N=8 as an example, when the data and command distributor is fully connected to the graphics processor core, the number of data and command transmission lines is 64 groups, and the number of physical layers of the graphics processor is configured as 8 layers. When the connection mode shown in FIG. 5A or FIG. 5B is adopted, the number of data and command transmission lines is 20 groups, and the number of physical layers of the graphics processor can be configured as 4 layers. In this case, the number of physical layers of the graphics processor can be reduced by adopting the connection method shown in FIG. 5A or FIG. 5B .

The application also provides a chip. FIG. 7 is a schematic structural diagram of a chip in an embodiment of the present application, and the chip includes the graphics processor and input and output pins described in any embodiment of the present application.

The present application also provides an electronic device, which includes the graphics processor described in any embodiment of the present application and a memory connected to the graphics processor in communication.

To sum up, the graphics processor provided by the embodiment of the present application can provide at least one virtual graphics processor, and the graphics processor can be shared by multiple users through virtualization of the graphics processor. In some embodiments of the present application, by optimizing the connection mode between the data and command distributor and the graphics processor core, the number of connections between the data and command distributor and the graphics processor core can be reduced, avoiding chip layout The congestion problem in the wiring stage is conducive to reducing the chip area and reducing the number of physical layers of the graphics processor. Therefore, the present application effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments are only illustrative to illustrate the principles and effects of the present application, but are not intended to limit the present application. Any person familiar with the technology can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the application shall still be covered by the claims of the application.

Claims (10)

1. A graphics processor comprising at least two data and command distributors and at least two graphics processor cores, each of said data and command distributors being coupled to at least one of said graphics processor cores, wherein one of said data and command distributors is coupled to one of said graphics processor cores via a set of data and command transmission lines;

the graphics processor is configured to provide at least one virtual graphics processor, each of the virtual graphics processors including one of the data and command distributors and some or all of the graphics processor cores coupled thereto.

2. The graphics processor of claim 1, wherein the graphics processor is configured to provide N of the virtual graphics processors in accordance with the received instructions, where N is any positive integer less than or equal to N, where N is the number of graphics processor cores.

3. The graphics processor as recited in claim 2, wherein an ith of said data and command distributors and

the graphics processor cores are connected, wherein i and n _i All are positive integers less than or equal to N, and floor is a downward rounding function.

4. A graphics processor as claimed in claim 3, wherein said graphics processor comprises N of said data and command distributors, 1 of which is coupled to N of said graphics processor cores, m of which _j -m _j+1 Each of the data and command distributors and

each saidGraphics processor cores are connected, m _j And m _j+1 Is adjacent positive integer which can be divided by N, and is 1.ltoreq.m _j+1 ＜m _j ≤N。

5. The graphics processor of claim 4, further comprising a data selector, the graphics processor core connecting at least two of the data and command distributors being connected to the data and command distributors by the data selector.

6. The graphics processor of claim 4 wherein the number of data and command distributors and the graphics processor cores is 8, the manner in which the data and command distributors are connected to the graphics processor cores comprises 1 one-to-eight connection, 1 one-to-four connection, 2 one-to-two connection, and 4 one-to-one connection.

7. The graphics processor of claim 1, wherein the number of layers of a physical layer of the graphics processor is configured according to the number of data and command transmission lines.

8. The graphics processor of claim 1, wherein the data and command distributor is fully coupled to the graphics processor core.

9. A chip comprising the graphics processor of any one of claims 1 to 8 and input-output pins.

10. An electronic device comprising the graphics processor of any one of claims 1 to 8 and a memory.

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