CN116112009A - A fractional frequency phase-locked loop circuit based on Sigma-delta modulator - Google Patents

Abstract

The invention relates to a fractional frequency-division phase-locked loop circuit based on a Sigma-delta modulator, belonging to the field of electronic circuits. The overall circuit structure of the phase-locked loop includes a clock frequency divider, a frequency and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator and a Sigma-delta modulator. Using the optimized design based on the MASH structure, the Sigma-Delta modulators are cascaded to achieve a high-order structure, and then the fractional frequency-divided signal output is integrated into the phase-locked loop. The Sigma-Delta modulator optimized and designed by the invention improves the signal-to-noise ratio of the modulator while improving the fractional frequency division precision. In the phase-locked loop, the output signal of the Sigma-delta modulator is integrated with the frequency-divided signal, and then transmitted to the PFD for phase comparison with the reference signal to control the frequency output of the VCO, completing a high-precision, high-performance phase-locked loop circuit with good phase noise .

Description

A fractional frequency phase-locked loop circuit based on Sigma-delta modulator

technical field

The invention belongs to the field of electronic circuits and relates to a fractional frequency division phase-locked loop circuit based on a Sigma-delta modulator.

Background technique

A phase-locked loop is called a PLL (Phase-Locked Loop) and is a frequency synthesizer, which is mainly a negative feedback control system that can generate a target frequency. There are many functions of the phase-locked loop, which can be mainly used in the frequency synthesis and exchange of frequency multiplication and frequency division; it can generate some high-frequency output signals as a frequency synthesizer. In recent years, it has been widely used even in biophysics, fluid mechanics, meteorology, atomic physics, oceanography, etc. As a very important module in the current Soc chip, the phase-locked loop is also developing towards higher precision and performance.

With the development of integrated circuits and the demand for higher precision and higher performance of the clock frequency inside the chip, the application of fractional frequency division phase-locked loops is gradually increasing. The fractional frequency-division phase-locked loop has high-frequency resolution phase-locked synthesis and has good noise characteristics, so it has become the mainstream technical means of high-frequency resolution synthesis in the market. However, the fractional frequency PLL will cause problems such as bit modulation and fractional spurs, and its quantization noise will have some negative effects on the signal purity of the PLL output. Therefore, Sigma-Delta modulation technology is generally used to solve these problems. .

Sigma-delta modulation technology was originally applied in the field of ADC (Analog to Digital Converter), but due to its good noise shaping technology, it is also applied in fractional frequency division phase-locked loop. As for the fractional frequency division phase-locked loop proposed this time, the main focus of the present invention lies in the high-precision frequency resolution and noise characteristics of the fractional frequency division phase-locked loop.

Contents of the invention

In view of this, the object of the present invention is to provide a fractional frequency division phase-locked loop circuit based on a Sigma-delta modulator.

To achieve the above object, the present invention provides the following technical solutions:

A high-precision and high-performance fractional frequency division phase-locked loop circuit designed based on a Sigma-delta modulator. The circuit includes frequency divide (clock frequency divider), PFD (frequency phase detector), CP (charge pump), LPF (loop filter), VCO (voltage controlled oscillator) and Sigma-delta modulator.

The present invention realizes through following technical scheme:

The Sigma-delta modulator uses the two technologies of oversampling and noise shaping. Using technology to diffuse the noise within the Nyquist bandwidth to the entire oversampling frequency, and then cooperate with noise shaping to push the noise to high frequencies, a good SNR signal-to-noise ratio will be obtained. If the sampling frequency is (f _s ) and the input signal bandwidth is (B _w ), the relationship between them can be represented by the oversampling rate OSR:

The first-order Sigma-delta modulator is to input a given decimal, use modules such as integrators and quantizers to continuously accumulate and quantify, and then output a series of pseudo-random control signal codes. In the long run, the average of this series of random signal codes is a fractional frequency division.

The system transfer function of the first-order Sigma-delta modulator is as follows:

Y(z)＝X(z)z ^-1 +E(z)(1-z ^-1 )

Its output Y(z) can be decomposed into two parts, the input signal and the quantization noise, and further decomposed to obtain the quantization noise transfer function NTF(z) and the signal transfer function STF(z):

From the above two formulas, the final modulator system only delays the input signal by one period before outputting the input signal, but for the quantization noise, it is equivalent to a noise shaping process . Since the noise transfer function is (1-z ^-1 ), high-order quantization can be achieved by transferring the quantization noise generated by each modulator to the next-stage Sigma-delta modulator for processing. This structure is called It is a MASH (Multi-stageNoise Shaping) structure, and the noise transfer function after high-order modulation is (1-z ^-1 ) ⁿ . After the noise shaping of the last modulator stage is completed, the digital output of each stage is delayed integrated. The conventional MASH1-1-1 structure Sigma-detla modulator adopts this method, and its system transfer function is as follows:

Y _n (z)=X ₁ (z)+(1-z ^-1 ) ^(n-1) E _n-1 (z)=Y ₁ (z)+(1-z ^-1 )Y ₂ (z) +(1-z ^-1 ) ² Y ₃ (z)

Finally, it is found that its noise performance is effectively improved and a high-precision effective number of bits can be obtained. However, in actual circuit design, too high order will easily lead to phase matching problems of subsequent frequency and phase detectors and overload of modulators. Therefore, after considering these comprehensive factors, the following optimization is performed, as shown in the Simulink simulation structure shown in Figure 3, and its second-order Z-domain model is:

Y(z)=X(z)-(1-H(z))E(z)

in,

H(z)＝1-(1-z ^-1 ) ²

The noise transfer function is:

NFT[Z]＝(1-z ^-1 ) ²

So the relationship between the input and output of MASH2-1 is:

Y(z)＝X(z)-(1-z ^-1 ) ⁴ E ₃ (z)

Finally, a second-order filter and a pseudo-random sequence generator are used to further reduce the period of the spurious model, and reduce the output of the discrete spectral line of the spurious signal to achieve the effect of reducing noise. It can be seen from Fig. 3 that the final effective number of bits (ENOB) can reach 18 bits, and its signal-to-noise ratio is 117.8dB.

The output range of the final Sigma-delta modulator is as shown in Figure 5. To achieve fractional frequency division, for example, to perform frequency division with N.F of 7.3894, the integer part N is 7, and the fractional part F is 0.3894. In Sigma-delta The input of the modulator is a 16-bit binary number "25536". It can be seen that the output is an integer from -1 to 3, and the average value imported into the calculator in MATLAB is 0.3896, which is in line with expectations. In order to achieve odd frequency division and even frequency division, the frequency divider adopts a dual-mode frequency divider of modulus 8 and modulo 9. Finally, random modulation is used to scramble the output sequence of Sigma-delta, which is similar to adding a jitter signal to the Sigma-delta modulator.

The beneficial effects of the present invention are:

The Sigma-Delta modulator optimized and designed by the invention improves the signal-to-noise ratio of the modulator while improving the fractional frequency division precision. In the phase-locked loop, the output signal of the Sigma-delta modulator is integrated with the frequency-division signal, and then transmitted to the PFD for phase comparison with the reference signal to control the frequency output of the VCO, and finally a high-precision, high-performance phase-locked loop with good phase noise is completed. circuit.

Other advantages, objects and features of the present invention will be set forth in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the investigation and research below, or can be obtained from It is taught in the practice of the present invention. The objects and other advantages of the invention may be realized and attained by the following specification.

Description of drawings

In order to make the purpose of the present invention, technical solutions and advantages clearer, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

Figure 1 is the optimized Sigma-delta structure simulink simulation;

Figure 2 is the simulink simulation of the MASH1-1-1 structure of Sigma-delta;

Fig. 3 is the fractional frequency division phase-locked loop circuit structure of the present invention;

Fig. 4 is the signal-to-noise ratio and oversampling rate frequency analysis of Sigma-delta modulator of the present invention;

Fig. 5 is the frequency output wave form diagram of Sigma-delta modulator;

Figure 6 is a top-level schematic diagram of a sigma-delta modulator.

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the diagrams provided in the following embodiments are only schematically illustrating the basic concept of the present invention, and the following embodiments and the features in the embodiments can be combined with each other in the case of no conflict.

Wherein, the accompanying drawings are for illustrative purposes only, and represent only schematic diagrams, rather than physical drawings, and should not be construed as limiting the present invention; in order to better illustrate the embodiments of the present invention, some parts of the accompanying drawings may be omitted, Enlargement or reduction does not represent the size of the actual product; for those skilled in the art, it is understandable that certain known structures and their descriptions in the drawings may be omitted.

In the drawings of the embodiments of the present invention, the same or similar symbols correspond to the same or similar components; , "front", "rear" and other indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred devices or elements must It has a specific orientation, is constructed and operated in a specific orientation, so the terms describing the positional relationship in the drawings are for illustrative purposes only, and should not be construed as limiting the present invention. For those of ordinary skill in the art, the understanding of the specific meaning of the above terms.

Please refer to FIG. 1 to FIG. 6 , the present invention discloses a high-precision and high-performance fractional frequency-division phase-locked loop circuit designed based on a Sigma-delta modulator. The overall circuit structure of the phase-locked loop includes frequency divide (clock frequency divider), PFD (phase frequency detector), CP (charge pump), LPF (loop filter), VCO (voltage controlled oscillator) and Sigma- delta modulator. Among them, the Sigma-Delta modulator module is the key point of the present invention, and the optimally designed Sigma-Delta modulator is mainly used to integrate the fractional frequency-divided signal output into the phase-locked loop. Follow these steps:

Step 1: The fractional frequency division part is mainly completed by a Sigma-delta modulator. A higher-order Sigma-delta modulator is realized by cascading a second-order and a first-order Sigma-delta modulator, which improves the signal-to-noise ratio and effective number of bits of the modulator. At the output end of the modulator, the random modulation technology of shift register is used to disrupt the periodicity of the output and suppress the output of fractional spurs.

Step 2: Complete the circuit design of the Sigma-delta modulator in the form of a digital circuit, which mainly includes an accumulator, an adder and a delay device, and the delay device is implemented by a D flip-flop. The first stage of the modulator can be designed in a pipelined structure. After the input signal is modulated by the two-stage integrator, the quantization noise is transmitted to the next-stage modulator, and the output signals of the two are integrated by noise to obtain the final output.

Step 3: After the output signal of the modulator is randomly modulated, the optimized Sigma-Delta modulator output signal is integrated with the integer frequency division signal, and then input to the frequency and phase detector for phase comparison with the reference signal. When the input signal lags behind the reference signal, increase the VCO output frequency to discharge the CP until the error is eliminated; similarly, when the input signal is ahead of the reference signal, the CP is charged, and the VCO will reduce the output frequency until the phase error is eliminated, and lock when the error is 0. Phase ring locked.

The first-order Sigma-Delta modulator is composed of an integrator, a unit quantizer, and a feedback through continuous accumulation and quantization. Its structure and function are similar to the effect of oversampling.

The transfer function of the first-order Sigma-delta system is:

Y(z)＝X(z)z ^-1 +E(z)(1-z ^-1 )

The first-order Sigma-delta modulator is designed in a high-order cascade. The third-order system transfer function is:

Y _n (z)=X ₁ (z)+(1-z ^-1 ) ^(n-1) E _n-1 (z)=Y ₁ (z)+(1-z ^-1 )Y ₂ (z) +(1-z ^-1 ) ² Y ₃ (z)

Then increase the Sigma-delta modulator after increasing the order to improve the signal-to-noise ratio SNR and oversampling rate OSR, where the relationship between the effective number of bits L and the signal-to-noise ratio SNR is as follows:

From the above two formulas, it can be seen that the SNR can be improved by increasing the order L and the oversampling rate OSR, and the purpose of the noise shaping technology is to quantize the noise to a smaller size, so that the SNR can be further improved. Improvement, it can be found that the effect of noise shaping is more obvious on the high-order structure, so it can be seen that noise shaping improves system performance. Here, the structural composition of the Sigma-Delta modulator is changed to reduce the quantization noise without increasing the order of the MASH structure.

Finally, it is found that its noise performance is effectively improved and a high-precision effective number of bits can be obtained. However, in actual circuit design, too high order will easily lead to phase matching problems of subsequent frequency and phase detectors and overload of modulators. Therefore, after considering these comprehensive factors, the following optimization is performed. A second-order modulator and a first-order modulator are cascaded to form the output signals of the two to obtain the final output after delay integration. Its second-order Z domain model is:

Y(z)=X(z)-(1-H(z))E(z)

in,

H(z)＝1-(1-z ^-1 ) ²

The noise transfer function is:

NFT[Z]＝(1-z ^-1 ) ²

So the relationship between the input and output of MASH2-1 is:

Y(z)＝X(z)-(1-z ^-1 ) ⁴ E ₃ (z)

Finally, it is found that its noise performance is effectively improved and a high-precision effective number of bits can be obtained. However, in actual circuit design, too high order will easily lead to phase matching problems of subsequent frequency and phase detectors and overload of modulators. Therefore, after considering these comprehensive factors, the optimized high-order MASH2-1 structure Sigma-delta modulator can achieve high precision and high performance. You can see the matlab simulation results of the Sigma-delta modulator from Figure 4, the oversampling rate can reach up to 128, the signal-to-noise ratio is 117.8db, and the effective number of bits (ENOB) can reach 18.

The top-level schematic diagram of the Sigma-delta modulator structure of the final digital circuit design is shown in Figure 6. f_N is the integer frequency division ratio of the input, frac is the fractional frequency division ratio part of the input, and the final output is the modulated signal of the modulator. The module of the whole digital circuit is mainly realized by the combination of adder, multiplier and D flip-flop, and the output frequency of the frequency division signal is increased by means of pipeline design.

For some phase noise introduced by the Sigma-delta modulation output, some modulation techniques are required to suppress the fractional spurs of the output signal. Here, the random modulation technology is mainly used to randomly modulate the output signal of Sigma-delta to suppress its fractional spurs.

The fractional frequency-divided output signal is input to the frequency and phase detector for phase comparison with the reference signal. When the input signal lags behind the reference signal, increase the VCO output frequency until the CP discharges until the error is eliminated; when the input signal is ahead of the reference signal, the CP charges, and in the same way the VCO reduces the output frequency until the phase error is eliminated, when the error is 0 Time-locked loop lock.

The input terminal of the reference clock frequency divider is connected to the reference clock signal, and one input terminal of the frequency and phase detector is connected to the frequency-divided clock signal sent by the reference clock frequency divider for phase comparison with the input signal. The output signal modulated by the Sigma-Delta modulator can also be seen in Figure 3. Its noise spectrum has the characteristics of shifting the noise from low-pass to high-pass, and then passes through the low-pass characteristics of the phase-locked loop circuit, such as A charge pump and a low-pass filter are used to obtain a high-precision, high-performance phase-noise phase-locked loop circuit.

Finally, it is noted that the above embodiments are only used to illustrate the technical solutions of the present invention without limitation. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be carried out Modifications or equivalent replacements, without departing from the spirit and scope of the technical solution, should be included in the scope of the claims of the present invention.

Claims (3)

1. A fractional frequency division phase-locked loop circuit based on a Sigma-delta modulator, characterized in that: the circuit includes a clock frequency divider, a phase frequency detector PFD, a charge pump CP, a loop filter LPF, a voltage control Oscillator VCO and Sigma-delta modulator; Among them, the Sigma-Delta modulator uses the Sigma-Delta modulator to integrate the fractional frequency division signal output into the phase-locked loop; the fractional frequency division signal is completed by the Sigma-delta modulator; A higher-order Sigma-delta modulator is realized by cascading a second-order and a first-order Sigma-delta modulator to improve the signal-to-noise ratio and effective number of bits of the modulator; use shift registers at the output of the modulator The unique random modulation technology disrupts the periodicity of the output and suppresses the output of decimal spurs; The Sigma-Delta modulator includes an accumulator, an adder and a time delay device, wherein the delay device is realized by a D flip-flop; the first stage of the Sigma-Delta modulator adopts a pipeline structure; when the input signal passes through two stages of integration After the modulation of the modulator, the quantization noise is transmitted to the modulator of the next stage, and the output signals of the two are integrated by noise to obtain the final output; After the output signal of the Sigma-Delta modulator is through random modulation, the output signal is integrated with the integer frequency division signal, and then input to the frequency and phase detector for phase comparison with the reference signal; when the input signal lags behind the reference signal Next, increase the VCO output frequency to discharge the CP until the error is eliminated; when the input signal is ahead of the reference signal, the CP is charged, and the VCO reduces the output frequency until the phase error is eliminated, and the phase-locked loop is locked when the error is 0. 2. a kind of fractional frequency division PLL circuit based on Sigma-delta modulator according to claim 1, is characterized in that: described Sigma-Delta modulator it passes accumulator, adder and delay in digital circuit timer to achieve; According to the linear structure of the first-order Sigma-delta modulator, its input-output relationship is obtained: Y(z)＝X(z)z ^-1 +E(z)(1-z ^-1 ) For the input signal X(z), delaying the input signal by one cycle before outputting it is equivalent to a noise shaping process for the quantization noise E(z). 3. a kind of fractional frequency division PLL circuit based on Sigma-delta modulator according to claim 2, is characterized in that: described Sigma-delta modulator is a multistage cascade, adopts the MASH2-1 after optimization The Sigma-delta circuit of the structure is improved on the basis of the third-order MASH1-1-1 structure; the transfer function of the system is derived from the simulink simulation model of the MASH2-1 structure Sigma-delta: Y(z)=X(z)-(1-H(z))E(z) in, H(z)＝1-(1-z ^-1 ) ² The noise transfer function is: N(z)＝(1-z ^-1 ) ² The signal-to-noise ratio of the N-order modulator when unit quantization is obtained:

At the same time, the effective number of digits L is obtained as:

Among them, OSR is the oversampling rate, and SNR is the signal-to-noise ratio; by changing the structural composition of the Sigma-Delta modulator, the quantization noise is reduced without increasing the order of the MASH structure.

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