CN116107958A - Chip system and electronic equipment - Google Patents

Abstract

The embodiment of the present application provides a chip system and electronic equipment, by setting a control chip and a memory chip such as a first memory chip on the first surface of the first main board, that is, the first memory chip is located on the periphery of the control chip, and the first main board A plurality of memory chips are arranged on the second surface of the first motherboard, wherein a part of the memory chips on the second surface of the first main board, such as the second memory chip, is arranged in a staggered manner from the control chip, and another part of the memory chips, such as the third memory chip, is arranged on the front and back of the control chip , that is, the third memory chip and the control chip have an overlapping area in the direction perpendicular to the first motherboard, so that the space on the first motherboard is fully utilized, and the number of memory chips installed on the first motherboard is increased, thereby realizing The high-density layout of the memory is improved, thereby increasing the total memory bandwidth of the first motherboard.

Description

Chip system and electronic equipment

technical field

The embodiments of the present application relate to the field of chip technologies, and in particular, to a chip system and electronic equipment.

Background technique

Double data rate (DDR for short) memory is a common high-speed storage device widely used in digital boards. DDR memory is usually used with a controller. By electrically connecting the controller to the DDR memory, the controller controls the data exchange between the DDR memory and the processor.

In related technologies, the chip system includes a main board, a memory chip and a controller, wherein the controller and the memory chip are both arranged on the main board. With the improvement of the processing capability of the motherboard, the demand for increasing the bandwidth and quantity of the DDR memory continues to increase. Therefore, multiple memory chips can be installed on the motherboard to increase the total memory bandwidth and the quantity of the memory in the chip system.

However, in the related art, the installation space on the motherboard of the chip system is not fully utilized, so that the amount of memory on a motherboard (referred to as a single board) in the chip system is small, so that the memory bandwidth of the single board of the chip system is limited.

Contents of the invention

The embodiment of the present application provides a chip system and electronic equipment, so that the space on the motherboard in the chip system is fully utilized, thereby increasing the number of memory chips installed on the single board, and improving the total bandwidth of the single board memory of the chip system .

An embodiment of the present application provides a chip system on the one hand, including a first motherboard, a control chip, and a plurality of memory chips electrically connected to the control chip;

The first motherboard includes a first surface and a second surface oppositely arranged, the control chip is arranged on the first surface of the first motherboard, and the multiple memory chips include a first memory chip, a second memory chip and a third memory chip, the first The memory chip is arranged on the first surface of the first motherboard, and the second memory chip and the third memory chip are arranged on the second surface of the first motherboard at intervals;

Wherein, the third memory chip and the control chip have an overlapping area in a direction perpendicular to the first main board, and the second memory chip and the control chip are staggered in a direction perpendicular to the first main board.

In the chip system provided by the embodiment of the present application, a control chip and a memory chip such as a first memory chip are arranged on the first surface of the first main board, that is, the first memory chip is located on the periphery of the control chip, and on the second surface of the first main board A plurality of memory chips are arranged, wherein, a part of the memory chips located on the second surface of the first main board, such as the second memory chip, is arranged in a staggered manner with the control chip, and another part of the memory chips, such as the third memory chip, is arranged on the front and back of the control chip, that is, the third memory chip. The memory chip and the control chip have an overlapping area in the direction perpendicular to the first main board, which makes full use of the space on the first main board, increases the number of memory chips on the first main board, and realizes high-density memory layout , thereby increasing the total memory bandwidth of the first motherboard, thereby increasing the total memory bandwidth of the entire chip system.

In a feasible implementation manner, the chip system may further include a second main board, the second main board is disposed on the second surface of the first main board, and the third memory chip is disposed on a side of the second main board facing away from the first main board, In this way, the third memory chip can be pre-set on one side of the second main board and used as a chip component. When it is necessary to increase the memory bandwidth of the first main board, the chip component can be directly connected to the corresponding side of the first main board. The location is sufficient, thereby improving the manufacturing efficiency of the chip system.

In a feasible implementation manner, the chip system may include a plurality of first electrical connectors, each first electrical connector includes a first through hole formed in the first motherboard, and one end of each first through hole is connected to the The corresponding pins of the control chip are electrically connected, and the other end of each first through hole is electrically connected with the corresponding pins of the third memory chip. The corresponding pins of the third memory chip are electrically connected. On the other hand, because the third memory chip is arranged on the side of the second main board facing away from the first main board, through holes can be directly set in the first main board to serve as the first main board. A part of the electrical connector leads the pins of the control chip to the side of the second motherboard facing the first motherboard, which simplifies the setting of the first electrical connector in the first motherboard compared to blind holes in the first motherboard process, thereby improving the setting efficiency of the first electrical connector in the first main board.

In a feasible implementation, each first electrical connector further includes a first via hole, a first trace, and a second via hole connected in sequence, and the first via hole, the first trace, and the second via The holes are all located in the second main board, wherein the first wiring is arranged parallel to the first surface of the first main board, one end of the first wiring is electrically connected to the corresponding first through hole through the first via hole, and the first wiring The other end of the second via hole is electrically connected to the corresponding pin of the third memory chip.

By arranging the first wiring in the second main board, in this way, vias can be provided at any position along the extension direction of the first wiring to electrically connect the pins of the control chips that are staggered in the direction perpendicular to the first main board and the pins of the third memory chip, for example, the first through hole can be electrically connected to the first via on the side facing the first motherboard, and the first via is electrically connected to the corresponding first through hole. The other side of a trace is electrically connected to the second via hole, and the other end of the second via hole is electrically connected to the corresponding pin of the third memory chip, thereby realizing the connection between the pin of the control chip and the pin located on the control chip. The corresponding pins of the third memory chip on the back are electrically connected, and the positions of the first via hole and the second via hole can be adjusted according to the actual pin positions.

In a feasible implementation manner, both the first via hole and the second via hole are configured as through holes penetrating through the second main board, so as to facilitate the manufacture of the first via hole and the second via hole. In addition, by arranging the second main board, the through holes as the first via hole and the second via hole are arranged on the second main board, reducing the number of through holes provided on the first main board, thereby avoiding the structure of the first main board. affect stability.

In a feasible implementation manner, a plurality of third memory chips are arranged at intervals on the side of the second main board facing away from the first main board, and the corresponding pins of each third memory chip are connected to the corresponding pins of the control chip through corresponding electrical connectors. Corresponding pins are electrically connected.

In the embodiment of the present application, by setting multiple third memory chips on the back of the control chip, the space on the back of the control chip is further fully utilized, and a high-density layout of the memory is realized, thereby increasing the total memory bandwidth of the first mainboard, and further improving the overall memory capacity of the entire chip. The total memory bandwidth of the system.

In a feasible implementation manner, there are multiple second via holes, and the multiple second via holes are respectively electrically connected to corresponding pins of multiple third memory chips.

The setting of multiple second via holes, on the one hand, realizes the electrical connection between one of the pins of the control chip and the corresponding pins of multiple multiple third memory chips at the same time, that is, realizes the function of driving more than one, and on the other hand On the one hand, by simultaneously connecting a plurality of second via holes on one side of the first wiring, the electrical connection between the control chip and the plurality of third memory chips is more convenient, and it also simplifies the connection between the control chip and the plurality of third memory chips. The structure of the first electrical connectors between the memory chips reduces the number of first electrical connectors in the chip system and improves the assembly efficiency of the chip system.

In a feasible implementation manner, the chip system includes a plurality of second electrical connectors, and each second electrical connector includes a third via hole, a second trace, a fourth via hole, and a fifth via hole;

One end of the third via hole is electrically connected to the corresponding pin of the control chip, the other end of the third via hole is electrically connected to the second wiring, and one end of the fourth via hole and the fifth via hole are both electrically connected to the second wiring ;

The other end of the fourth via hole is electrically connected to the corresponding pin of the first memory chip, and the other end of the fifth via hole is electrically connected to the corresponding pin of the second memory chip.

In the embodiment of the present application, a second electrical connection member is provided in the chip system to realize a stable electrical connection between the control chip and the corresponding pins on the second memory chip or the third memory chip. In addition, by setting the second electrical connector to include the second wiring, in this way, through holes such as the fourth via hole and the fifth via hole can be provided at any position in the extending direction of the second wiring, so as to align with the main board. (that is, the first main board and the second main board) the symmetrical or asymmetrical first memory chip and the second memory chip on both sides are electrically connected, and in addition, by setting another via hole such as the first Three via holes can electrically connect the second wiring to one of the pins of the control chip, so that any pin of the control chip can be electrically connected to the corresponding pins on the first memory chip and the second memory chip at the same time. The connection, on the one hand, makes the control chip electrically connected to the corresponding pins of the first memory chip (or the second memory chip). Specifically, the third through hole, the fourth through hole or the third through hole can be adjusted according to the position of the actual pin. The position of the fifth via hole, on the other hand, enables a second electrical connector to realize the function of driving multiple, that is, one control chip is electrically connected to the corresponding pins of multiple memory chips at the same time, thereby simplifying the second electrical connector. The structure reduces the number of second electrical connectors in the chip system, thereby making the connection circuits in the chip system more regular and non-interfering with each other, and also improving the manufacturing efficiency of the chip system.

In a feasible implementation manner, the area of the projected area of the second main board on the second surface is smaller than the area of the second surface;

The second memory chip and the second main board are arranged staggered in a direction perpendicular to the first main board.

In the embodiment of the present application, the area of the projected area of the second main board on the second surface is set to be smaller than the area of the second surface. The size of the second main board of the memory chip makes the chip assembly formed by the third memory chip and the second main board more portable and smart, on the one hand, it is convenient to manufacture the chip assembly, and on the other hand, it is convenient to assemble the chip assembly on the first main board. In addition, the second memory chip can be directly arranged in other areas of the second motherboard, so that the electrical connection structure between the second memory chip and the control chip can be simplified, and the electrical connection path between the second memory chip and the control chip can be reduced. , thereby reducing the circuit impedance between the second memory chip and the control chip, making the signal transmission between the second memory chip and the control chip more reliable.

In a feasible implementation manner, each first electrical connector further includes a first solder ball located between the second main board and the first main board, and one end of the first solder ball is connected to the corresponding first solder ball in the first main board. The other end of the first solder ball is connected with the corresponding first via hole in the second main board.

In the embodiment of the present application, first solder balls are arranged between the second main board and the first main board, and the first via holes on the second main board are soldered to the first through holes on the first main board through the first solder balls, In order to improve the electrical connection stability between the first via hole and the first through hole, in addition, soldering the second main board on the first main board through the first solder ball also improves the connection between the second main board and the first main board. connection stability, thereby further improving the reliability of the electrical connection between the first through hole and the first through hole, and ensuring a stable electrical connection between the pins of the control chip and the corresponding pins of the third memory chip.

In a feasible implementation manner, the first solder balls in each of the first electrical connectors overlap with the corresponding pins of the control chip in a direction perpendicular to the first main board, that is to say, the plurality of first solder balls The number of a plurality of pins corresponding to a solder ball and the control chip is the same, the spacing is equal, and the position of each first solder ball is consistent with the corresponding pin on the control chip in a direction parallel to the first main board, so that it can be guaranteed The first through hole used to connect the first solder ball and the corresponding pin of the control chip is perpendicular to the first main board, which makes the manufacturing process of the first through hole simpler, thereby improving the manufacturing efficiency of the electrical connector of the chip system.

In a feasible implementation manner, the chip system further includes a resistance-capacitance element, the resistance-capacitance element is arranged on the side of the second motherboard facing the first motherboard, and the resistance-capacitance element is arranged adjacent to the first solder ball, and the resistance-capacitance element is connected to the first solder ball. a solder ball electrical connection;

Wherein, the resistance-capacitance element includes at least one of a termination resistor and a filter capacitor.

In the embodiment of the present application, a resistance-capacitance element is provided at a position adjacent to the first solder ball in the chip system, and the termination resistance therein realizes impedance matching in the first electrical connector, ensuring that the resistance in the first electrical connector does not affect signal transmission, The filter capacitor is used to absorb the current fluctuation generated by the first electrical connector during operation and the interference that is connected in series via the AC power supply, so that the working performance of the first electrical connector is more stable. In addition, because the resistance at the position where the first through hole is connected to the first via hole is relatively large, and the current fluctuation here is more obvious, so by setting the resistance-capacitance element close to the first solder ball, the connection between the first through hole and the second through hole is realized. Impedance matching or current stability at a via hole connection, so as to further ensure the stability of signal transmission between the control chip and the third memory chip. In addition, by arranging the resistance-capacitance element on the side of the second main board facing the first main board, the space on the side of the second main board facing away from the first main board is saved, thereby providing more space for the arrangement of the third memory chip, Therefore, the number of third memory chips can be increased.

In a feasible implementation manner, there are multiple resistance-capacitance elements, and the plurality of resistance-capacitance elements are arranged in one-to-one correspondence with the plurality of first solder balls;

And each resistance-capacitance element is disposed adjacent to the corresponding first solder ball.

In the embodiment of the present application, by setting a resistance-capacitance element near each first solder ball, the impedance matching or current stability of each first electrical connector at the connection between the first through hole and the first via hole is ensured, and the mutual Signals between two adjacent first electrical connectors fluctuate to cause crosstalk, thereby ensuring the stability of signal transmission between each corresponding pin between the control chip and the third memory chip.

In a feasible implementation manner, the second main board is press-fitted on the second surface of the first main board;

The second memory chip and the third memory chip are spaced apart on the side of the second main board facing away from the first main board.

In the embodiment of the present application, by pressing the second main board on the second surface of the first main board, on the one hand, it ensures the stability of the connection between the second main board and the first main board, and ensures the structural stability of the entire chip system. On the one hand, compared with a single main board, the electrical connection between the corresponding pins that are vertically staggered is realized, and one of the main boards, such as the first main board, is formed with a through hole as a part of the electrical connector. The through hole is a blind hole in terms of the entire board formed after the first main board and the second main board are pressed together, that is to say, a part of the blind hole can be directly realized through the through hole made on the first main board, and because the through hole The manufacturing process of the blind hole is simpler than that of the blind hole, therefore, the manufacturing process of the electrical connector such as the first electrical connector in the chip system is simplified.

In a feasible implementation manner, the second wiring is located in the second main board, so that the third via hole and the fourth via hole of the second electrical connector both include through holes located in the first main board, so that the Some of the second electrical connectors in the first main board are easier to manufacture, thereby improving the manufacturing efficiency of the second electrical connectors in the chip system.

In a feasible implementation manner, the part of the third via hole located on the second main board is a through hole penetrating through the second main board, the part of the fourth via hole located on the second main board is a through hole penetrating through the second main board, and the fifth via hole is located on the second main board. The hole is a through hole penetrating through the second main board, thus making the electrical connection in the second main board easier to manufacture. In addition, by setting the second main board and the above-mentioned second electrical connector, on the one hand, the electrical connection between the asymmetrical pins in the first memory chip and the second memory chip is ensured; on the other hand, the second electrical connection The through hole part of the component can be set to include a through hole penetrating through the first main board and a through hole penetrating through the second main board, which simplifies the manufacturing process of the entire second electrical connector and improves the manufacturing efficiency of the chip system. In addition, parts of the third via hole, the fourth via hole and the fifth via hole only penetrate the second main board, which also reduces the number of through holes provided in the first main board, thereby avoiding affecting the stability of the first main board.

In a feasible implementation, each second electrical connector further includes a sixth via hole located in the second main board, one end of the sixth via hole is electrically connected to the second wiring, and the other end of the sixth via hole It is electrically connected with the corresponding pin of the third memory chip.

In the embodiment of the present application, the sixth via hole is provided in the second electrical connector, so that the control chip is electrically connected to the corresponding pins of the first memory chip, the second memory chip, and the third memory chip through the second electrical connector. connection, so that one second electrical connector realizes the function of driving multiple, thereby simplifying the structure of the second electrical connector, reducing the number of second electrical connectors in the chip system, thereby making the connection circuit in the chip system more regular , do not interfere with each other, and also improve the production efficiency of the chip system. In addition, by adjusting the position of the sixth via hole, the fast electrical connection between the control chip and the pins at different positions in the third memory chip can be realized, so that it is more convenient for the number and position of the control chip and the third memory chip to be different. It is easier to communicate between pins with different pitches.

In a feasible implementation, the second wiring is located in the first main board, so that a part of the fifth via hole can be a through hole formed in the second main board, thereby facilitating the second electrical connection in the second main board. production of pieces.

In a feasible implementation manner, the second memory chip and the first memory chip are arranged symmetrically with respect to the first motherboard;

The fourth via hole communicates with the corresponding fifth via hole to form a second via hole perpendicular to the first main board. In this way, the manufacturing process of the fourth via hole and the fifth via hole can be simplified, and the manufacturing process of the second electrical connector can be improved. efficiency.

In a feasible implementation manner, the first surface of the first motherboard is provided with a plurality of first memory chips at intervals, the number of fourth via holes is multiple, and one end of the plurality of fourth via holes is connected to the plurality of first memory chips respectively. Corresponding pins of a memory chip are electrically connected;

Alternatively, a plurality of second memory chips are arranged at intervals on the side of the second main board facing away from the first main board. Corresponding pins are electrically connected.

In the embodiment of the present application, a plurality of first memory chips and a plurality of second memory chips are arranged on the first main board to make full use of the space on the first main board, further increasing the setting of the memory chips of the first main board quantity, thereby realizing a high-density layout of memory, thereby increasing the total memory bandwidth of the first motherboard, and further improving the total memory bandwidth of the entire chip system. In addition, the electrical connection between the corresponding pins of the control chip and the plurality of first memory chips can be realized by adjusting the number and respective positions of the fourth via holes. Correspondingly, by adjusting the number and positions of the fifth via holes respective positions, so as to realize the electrical connection between the corresponding pins of the control chip and the plurality of second memory chips.

In a feasible implementation manner, the thickness of the second main board is smaller than that of the first main board, thus simplifying the manufacturing process of setting blind holes on the second main board, thereby improving the electrical connection of the chip system, such as the first electrical connection. The manufacturing efficiency of the connector or the second electrical connector. In addition, by miniaturizing the second main board, that is, reducing the size of the second main board on which the third memory chip is disposed, the second main board is more convenient to be assembled on the first main board, and the whole chip system is thinner and lighter.

In a feasible implementation manner, at least one of each of the first electrical connector and the second electrical connector further includes a second solder ball, and the pins of the control chip are electrically connected to the first motherboard through the second solder ball. to improve the stability of the connection between the control chip and the first main board, thereby also ensuring the electrical connection between the pins of the control chip and the metal vias (such as the first through holes) in the first main board stability.

In a feasible implementation manner, at least one of each of the first electrical connector and the second electrical connector further includes a third solder ball, and the pins of the memory chip are welded on the first motherboard through the third solder ball , so as to improve the stability of the connection between the memory chip and the first main board, thereby also ensuring the stability of the electrical connection between the pins of the memory chip and the metal vias (such as the fourth via) in the first main board.

Another aspect of the embodiment of the present application provides an electronic device, including the above-mentioned chip system.

In the embodiment of the present application, the above-mentioned chip system is arranged in the electronic device, and the control chip and the memory chip such as the first memory chip are arranged on the first surface of the first motherboard, that is, the first memory chip is located on the periphery of the control chip, and the first A plurality of memory chips are arranged on the second surface of the motherboard, wherein, a part of the memory chips located on the second surface of the first motherboard, such as the second memory chip, and the control chip are staggered, and another part of the memory chips, such as the third memory chip, is arranged on the front of the control chip. On the back side, that is, the third memory chip and the control chip have an overlapping area in the direction perpendicular to the first main board, so that the space on the first main board is fully utilized, and the number of memory chips installed on the first main board is increased, thereby The high-density layout of the memory is realized, the total memory bandwidth of the entire chip system is improved, and the storage performance of the electronic device is further improved.

Description of drawings

FIG. 1 is a schematic structural diagram of a chip system provided by an embodiment of the present application;

Fig. 2 is a top view of a chip system provided by an embodiment of the present application;

FIG. 3 is another schematic structural diagram of a chip system provided by an embodiment of the present application;

Fig. 4 is another schematic structural diagram of the chip system provided by an embodiment of the present application;

Fig. 5 is another schematic structural diagram of the chip system provided by an embodiment of the present application;

FIG. 6 is another schematic structural diagram of a chip system provided by an embodiment of the present application;

FIG. 7 is another schematic structural diagram of a chip system provided by an embodiment of the present application;

FIG. 8 is another schematic structural diagram of a chip system provided by an embodiment of the present application.

Explanation of reference signs:

100-first main board; 200-control chip; 300-memory chip; 400-electric connector; 500-second main board; 600-resistance-capacitance element;

110-first surface; 120-second surface; 310-first memory chip; 320-second memory chip; 330-third memory chip; 410-first electrical connector; 420-second electrical connector;

411-first via; 412-first via; 413-first trace; 414-second via; 410a-metal via; 415-first solder ball; 416-second solder ball; 417- The third solder ball; 421-the third via; 422-the second trace; 423-the fourth via; 424-the fifth via; 425-the sixth via; 426-the second via;

421a-first part; 421b-second part; 423a-third part; 423b-fourth part; 424a-fifth part; 424b-sixth part.

Detailed ways

The terms used in the embodiments of the present application are only used to explain specific embodiments of the present application, and are not intended to limit the present application.

An embodiment of the present application provides an electronic device, including a memory and a processor, wherein the memory is used to store executable instructions of the processor, and may also store application data, such as image data, video data, and sound data. The processor is used to send instructions to the memory and process application data in the memory.

In practical applications, the memory is specifically arranged in the electronic device in the form of an integrated circuit integrated on the circuit board, that is, a chip. For example, the memory may be a chip system, and correspondingly, the processor may also be arranged in the electronic device in the form of a chip, such as , the processor may also be a processing chip system.

It should be noted that the electronic device provided in the embodiment of the present application may be a terminal or a cloud server, for example, the electronic device includes but is not limited to a mobile phone, a tablet computer, a notebook computer, an ultra-mobile personal computer (ultra-mobile personal computer, referred to as : UMPC), handheld computers, walkie-talkies, netbooks, POS machines, personal digital assistants (PDA), wearable devices, virtual reality devices, routers, etc.

In the embodiment of the present application, the chip system includes a motherboard, a memory chip, and a control chip. Wherein, the motherboard is specifically a printed circuit board (Print Circuit Board, referred to as PCB), and the memory chip can be a double data rate (Double data rate, referred to as DDR) memory chip, the DDR chip is a common high-speed memory device, widely used in the digital board.

The DDR memory chip is usually used in conjunction with a controller, and the controller may be a control chip, for example, the control chip may be an Application Specific Integrated Circuit (ASIC for short).

By electrically connecting the control chip with corresponding pins of the DDR memory chip, the data exchange between the DDR memory chip and the processor can be controlled by the control chip. For example, when the processor needs data in the memory chip, the processor will send an instruction to the control chip, and the control chip will then send the instruction to the memory chip, and the control chip will then transmit the relevant data in the memory chip to the In the processor, the data is finally processed by the processor.

From a functional understanding, the memory chip can be seen as a bridge or warehouse between the control chip and the processor. Obviously, the capacity of the memory chip determines the size of the "warehouse", and the bandwidth of the memory chip determines the width of the "bridge". Both are indispensable. Among them, the bandwidth of the memory chip determines the memory speed.

DDR memory chips mainly use parallel buses to transmit data signals, which greatly increases the bus bandwidth, thereby effectively improving the data storage rate of the chip system. Wherein, when the bandwidth of a single memory chip such as a DDR memory chip is constant, increasing the number of memory chips is a means to increase the total memory bandwidth of the chip system.

In related technologies, there are multiple memory chips in the chip system, and the multiple memory chips are arranged at intervals on any side of the motherboard. For example, the motherboard includes a first surface and a second surface oppositely arranged along the thickness direction, and the control chip is arranged on the first surface or the second surface, for example, the control chip is arranged on the first surface, and a plurality of memory chips can be arranged at intervals On the first surface, it can also be arranged on the second surface at intervals.

In practical application, the plurality of memory chips arranged on the second surface are located on the periphery of the control chip along the direction parallel to the motherboard. In other words, the plurality of memory chips and the control chip located on the second surface are staggered in the direction perpendicular to the motherboard. set up.

However, with the continuous enhancement of the processing capability of the motherboard, the demand for increasing the number of memory chips continues to increase, and the space on the motherboard in the above-mentioned chip system is not fully utilized, so that the number of memory chips on a motherboard (single board for short) in the chip system The number is small, so that the single-board memory bandwidth of the chip system is limited.

The embodiment of the present application provides a chip system, by setting a control chip and a memory chip such as a first memory chip on the first surface of the first motherboard, that is, the first memory chip is located on the outer periphery of the control chip, and on the first surface of the first motherboard A plurality of memory chips are arranged on the second surface, wherein, a part of the memory chips on the second surface of the first motherboard, such as the second memory chip, is arranged in a staggered manner from the control chip, and another part of the memory chips, such as the third memory chip, is arranged on the front and back of the control chip, namely The third memory chip and the control chip have an overlapping area in the direction perpendicular to the first main board, so that the space on the first main board is fully utilized, and the number of memory chips installed on the first main board is increased, thereby realizing memory The high-density layout improves the total memory bandwidth of the entire chip system, thereby improving the storage performance of electronic devices.

The structure of the chip system provided by the embodiment of the present application will be described in detail below in conjunction with the accompanying drawings.

FIG. 1 is a schematic structural diagram of a chip system provided by an embodiment of the present application, and FIG. 2 is a top view of the chip system provided by an embodiment of the present application. Referring to FIG. 1 and FIG. 2 , the embodiment of the present application provides a chip system, which includes a motherboard, a control chip 200 and a plurality of memory chips 300 electrically connected to the control chip 200 . Wherein, in order to distinguish this main board from another main board mentioned below, this main board is referred to as the first main board 100 . It can be understood that the first main board 100 may be a PCB.

With reference to Fig. 1 and shown in Fig. 2, for the convenience of description, the length direction of the first main board 100 is represented by arrow x, the thickness direction of the first main board 100 is represented by arrow z (refer to Fig. 1), and the first main board 100 is represented by arrow z. The width direction of 100 is indicated by arrow y (refer to FIG. 2).

Referring to FIG. 1, the first main board 100 includes a first surface 110 and a second surface 120 arranged opposite to each other. In the z direction) two surfaces set opposite to each other. In practical applications, the first surface 110 can be used as the front side of the first main board 100 , and the second surface 120 can be used as the back side of the first main board 100 .

In specific setting, the control chip 200 can be set on any one of the first surface 110 and the second surface 120 of the first main board 100, and in the embodiment of the present application, the control chip 200 is specifically set on the first surface 110 of the first main board 100. That is, the front side is used as an example for illustration.

Referring to Fig. 1 and Fig. 2, when a plurality of memory chips 300 are specifically arranged, a part of the memory chips 300 are arranged on the first surface 110 of the first main board 100, that is, a part of the memory chips 300 and the control chip 200 are arranged on the first main board 100. The same side of the memory chip 300 is located on the periphery of the control chip 200 . For example, the memory chip 300 located on the first surface 110 can be arranged on one side of the control chip 200 along the x direction (refer to FIG. 1 ), or can be arranged on the side of the control chip 200 along the y direction (refer to FIG. 2 ).

Referring to FIG. 1 , another part of memory chips 300 is disposed on the second surface 120 of the first motherboard 100 . Among the plurality of memory chips 300 located on the second surface 120 of the first main board 100, some memory chips 300 and the control chip 200 are staggered along a direction perpendicular to the first main board 100 (shown in the z direction with reference to FIG. 1 ), That is to say, the part of the memory chips 300 is located on the periphery of the control chip 200 arrangement area of the second surface 120 along the direction perpendicular to z.

Wherein, the control chip layout area refers to the projection area of the control chip 200 on the first surface 110 or the second surface 120 of the first motherboard 100 along the z direction.

For example, a part of the memory chips 300 may be located on the second surface 120 on the side of the control chip arrangement region along the x direction (refer to FIG. 1 ), or on the second surface 120 on the side of the control chip arrangement region along the y direction.

Among the plurality of memory chips 300 disposed on the second surface 120, another part of the memory chips 300 and the control chip 200 have an overlapping area along the direction perpendicular to the first motherboard 100 (refer to the z direction in FIG. 1 ), in other words, Referring to FIG. 1 , a part of the memory chip 300 is located on the back side of the control chip 200 along the z direction, for example directly below. Wherein, the back side of the control chip 200 refers to the side of the control chip 200 facing the first motherboard 100 .

For the convenience of description below, the plurality of memory chips 300 in the embodiment of the present application may include a first memory chip 310 , a second memory chip 320 and a third memory chip 330 . Wherein, the first memory chip 310 is disposed on the first surface 110 of the first motherboard 100 , in other words, the memory chip 300 located on the first surface 110 of the first motherboard 100 serves as the first memory chip 310 . It can be understood that the first memory chip 310 may be disposed on one side of the control chip 200 along the x direction, or may be disposed on one side of the control chip 200 along the y direction. Certainly, the first memory chip 310 may be disposed on both sides of the control chip 200 along the x-direction and the y-direction.

Exemplarily, there may be a plurality of first memory chips 310. Among the plurality of first memory chips 310, a part of the first memory chips 310 may be disposed on one side of the control chip 200 along the x direction, for example, the control chip 200 may be arranged on the side of the x direction. One or more first memory chips 310 can be arranged on one side of the control chip 200. As shown in FIG. Three or more first memory chips 310 are arranged at intervals on one side of the control chip 200 along the x direction, which is not limited here.

2, another part of the first memory chip 310 can be arranged on one side of the control chip 200 along the y direction, for example, one or more first memory chips 310 can be arranged on one side of the control chip 200 along the y direction, as shown in FIG. 2 shows that two first memory chips 310 are arranged at intervals on one side of the control chip 200 along the y direction. Of course, in the embodiment of the present application, three or three memory chips may also be arranged at intervals on one side of the control chip 200 along the x direction. The above first memory chip 310 is not limited here. In this way, by arranging a plurality of first memory chips 310 at intervals on the first surface 110 of the first motherboard 100, to make full use of the space on the first surface 110 of the first motherboard 100, the arrangement of the memory chips of the first motherboard 100 is increased. quantity.

Referring to FIG. 1 , the second memory chip 320 and the third memory chip 330 are disposed on the second surface 120 of the first motherboard 100 at intervals. Wherein, the third memory chip 330 and the control chip 200 have an overlapping area in the direction perpendicular to the first main board 100, that is to say, the third memory chip 330 is located on the back side of the control chip 200 along the z direction, for example, directly below. In other words, the memory chip 300 located on the back of the control chip 200 serves as the third memory chip 330 .

It should be noted that the third memory chip 330 and the control chip 200 can completely overlap in a direction perpendicular to the first motherboard 100 . For example, the projection area of the third memory chip 330 on the second surface 120 of the first main board 100 along the z direction is the first area, and the projection area of the control chip 200 on the second surface 120 of the first main board 100 along the z direction is the first area. Two areas, the first area is located inside the second area.

Of course, in some examples, the third memory chip 330 partially overlaps the control chip 200 in a direction perpendicular to the first motherboard 100, for example, a part of the first area is located inside the second area, and a part is located outside the second area, In other words, the memory chip 300 that partially overlaps with the control chip 200 in a direction perpendicular to the first motherboard 100 is also used as the third memory chip 330 .

In the embodiment of the present application, the number of the third memory chip 330 may be one or more. For example, as shown in FIG. Three memory chips 330 . Wherein, a plurality of third memory chips 330 may be arranged at intervals along the x direction, or may be arranged at intervals along the y direction. By arranging a plurality of third memory chips 330 at intervals on the second surface 120 of the first motherboard 100 , the space on the second surface 120 of the first motherboard 100 is fully utilized, and the number of memory chips installed on the first motherboard 100 is increased.

The second memory chip 320 and the control chip 200 are arranged staggered in the direction perpendicular to the first main board 100, that is to say, the second memory chip 320 is located on the outer periphery of the control chip 200 along the direction parallel to the first main board 100, that is, the second memory chip 320 The second memory chip 320 is located on the second surface 120 on the periphery of the control chip 200 arrangement area along the direction perpendicular to the z direction, for example, the second memory chip 320 is arranged on the second surface 120 and is located on one side of the control chip 200 arrangement area along the x direction (refer to FIG. 1 ), or be located on one side of the control chip 200 arrangement area along the y direction (not shown in the figure).

Exemplarily, the number of the second memory chip 320 may be one or multiple. For example, as shown in FIG. Memory chip 320. Wherein, a plurality of second memory chips 320 may be arranged at intervals along the x direction, or may be arranged at intervals along the y direction. By arranging a plurality of second memory chips 320 at intervals on the second surface 120 of the first motherboard 100 , the space on the second surface 120 of the first motherboard 100 is fully utilized, and the number of memory chips installed on the first motherboard 100 is increased.

In the chip system provided by the embodiment of the present application, a control chip 200 and a memory chip such as a first memory chip 310 are arranged on the first surface 110 of the first motherboard 100, that is, the first memory chip 310 is located on the periphery of the control chip 200, and The second surface 120 of a motherboard 100 is provided with a plurality of memory chips, wherein a part of the memory chips located on the second surface 120 of the first motherboard 100 such as the second memory chip and the control chip 200 are staggered, and the other part of the memory chips such as the third memory chip 330 is arranged on the front and back of the control chip 200, that is, the third memory chip 330 and the control chip 200 have an overlapping area in the direction perpendicular to the first main board 100, so that the space on the first main board 100 is fully utilized, increasing the The number of memory chips on the first main board 100 realizes a high-density memory layout, thereby increasing the total memory bandwidth of the first main board 100 , and further increasing the total memory bandwidth of the entire chip system.

Referring to FIG. 1 , in the embodiment of the present application, the first memory chip 310 is directly disposed on the first surface 110 of the first motherboard 100 .

In some examples, the second memory chip 320 and the third memory chip 330 are directly disposed on the second surface 120 of the first motherboard 100 .

FIG. 3 is another schematic structural diagram of a chip system provided by an embodiment of the present application. Referring to FIG. 3 , the chip system of the embodiment of the present application may also include a second motherboard 500, the second motherboard 500 is arranged on the second surface 120 of the first motherboard 100, and the third memory chip 330 is arranged on the back of the second motherboard 500. To the side of the first motherboard 100 , in other words, the third memory chip 330 is disposed on the second surface 120 of the first motherboard 100 through the second motherboard 500 .

For convenience of description, the side of the second motherboard 500 provided with the third memory chip 330 can be taken as the front side of the second motherboard 500, and the side of the second motherboard 500 facing away from the third memory chip 330 can be taken as the back side of the second motherboard 500 .

In this way, the third memory chip 330 can be pre-set on one side of the second main board 500, and as a chip component, when it is necessary to make a chip system with a high-density layout, for example, when it is necessary to increase the memory bandwidth of the first main board 100 , the chip assembly can be directly connected to the corresponding position of the first motherboard 100, thereby improving the manufacturing efficiency of the chip system.

In practical applications, the control chip 200 has a plurality of pins (also referred to as pins) arranged at intervals, and each pin has a different network attribute, that is to say, each pin transmits a different signal. Wherein, the multiple pins of the control chip 200 can be divided into data pins, address pins and control pins according to different functions.

Correspondingly, the memory chip 300 also has a plurality of pins arranged at intervals, and the plurality of pins correspond to the network attributes of the plurality of pins in the control chip 200, in other words, the memory chip 300 and the corresponding pins in the control chip 200 The net properties of the pins are the same function.

For example, one of the pins of the control chip 200 is used to transmit data signals, such as the pin is electrically connected to the corresponding pin of the memory chip 300, so as to transmit the data in the memory chip 300 to the control chip 200, and through the The control chip 200 transmits the data to the processor. Another pin of the control chip 200 is used to transmit address signals, for example, this pin is electrically connected to the corresponding pin of the memory chip 300, so as to read the data corresponding to the address in the memory chip 300 according to the address selection instruction issued by the processor. . Another pin of the control chip 200 is used to transmit control signals, such as the pin is electrically connected to the corresponding pin of the memory chip 300, so as to control the memory chip 300 according to the control instructions issued by the processor, for example, the control chip 200 passes This pin performs operations such as chip selection on the data in the memory chip 300 .

Referring to FIG. 3 , the chip system may include a plurality of electrical connectors 400, and each pin of the control chip 200 may be electrically connected to a corresponding pin of the corresponding memory chip 300 through a corresponding electrical connector 400, so as to implement a control chip. Mutual transmission of specific signals between 200 and memory chip 300 .

Wherein, the plurality of pins of the control chip 200 can be arranged at intervals along the length direction of the control chip 200, such as the x direction, and correspondingly, the corresponding plurality of pins in the memory chip 300 are also arranged along the length direction of the memory chip 300, such as the x direction. Arranged at intervals, so that each electrical connector 400 is located in the same plane, such as the xoz plane.

Certainly, in some examples, the multiple pins of the control chip 200 may also be arranged at intervals along the width direction of the control chip 200, such as the y direction, and correspondingly, the corresponding multiple pins of the memory chip 300 are also arranged along the width direction of the memory chip 200. The length direction of 300 such as the y direction is arranged at intervals so that each electrical connector 400 is located in the same plane such as the yoz plane.

The embodiment of the present application is specifically described by taking an example in which multiple pins of the control chip 200 can be arranged at intervals along the length direction of the control chip 200 , for example, the x direction.

Referring to FIG. 3 , the plurality of electrical connectors 400 in the embodiment of the present application may include a first electrical connector 410 and a second electrical connector 420, wherein the first electrical connector 410 is used to electrically connect the control chip 200 to the second electrical connector. Three memory chips 330 , the first electrical connector 410 is set corresponding to the pins in the control chip 200 that need to be electrically connected to the third memory chip 330 .

It can be understood that the number of the first electrical connector 410 may be one or more. For example, when a pin of the control chip 200 needs to be electrically connected to a corresponding pin of the third memory chip 330, there is only one first electrical connector 410, and one end of the first electrical connector 410 is connected to the pin of the control chip 200. The other end of the first electrical connector 410 is electrically connected to the corresponding pin of the corresponding third memory chip 330 .

When multiple pins of the control chip 200 need to be electrically connected to multiple pins of the third memory chip 330, the number of the first electrical connectors 410 is the same as the pins used to electrically connect the third memory chip 330 on the control chip 200 The numbers are the same, so that the plurality of pins of the control chip 200 are electrically connected to the corresponding pins of the third memory chip 330 through the corresponding first electrical connectors 410, so that the control chip 200 can perform various operations on the third memory chip 330. Functional control.

Referring to FIG. 3 , in the embodiment of the present application, when the third memory chip 330 is arranged on the side of the second motherboard 500 facing away from the first motherboard 100 , in other words, the third memory chip 330 is arranged on the side of the second motherboard 500 On the front side, each first electrical connector 410 may include a first through hole 411 formed in the first motherboard 100, one end of each first through hole 411 is electrically connected to a corresponding pin of the control chip 200, and each first The other end of the through hole 411 is electrically connected to the corresponding pin of the third memory chip 330 . It can be understood that the other end of each first through hole 411 can be electrically connected to the corresponding pin of the third memory chip 330 through other parts of the first electrical connection member 410 such as the part located in the second motherboard 500 .

For example, one end of the first through hole 411 extends to the first surface 110 of the first main board 100 and is electrically connected to the corresponding pin of the control chip 200, and the other end of the first through hole 411 extends to the first surface 110 of the first main board 100. The second surface 120 is electrically connected to the electrical connector 400 between the third memory chip 330, so that the control chip 200 and the third control chip 200 can be realized through the first through hole 411 and other parts of the first electrical connector 410. Electrical connection of chip 200 .

It should be understood that the first through holes 411 extend along the z direction, that is, the direction perpendicular to the first main board 100 , and each first through hole 411 is provided corresponding to each pin used to connect the third memory chip 330 in the control chip 200 .

Wherein, the first through hole 411 specifically includes a through hole penetrating through the first motherboard 100 and a metal medium filled in the through hole. The metal medium may include but not limited to conductive metals such as copper and aluminum, and the specific composition of the metal medium is not limited here.

On the one hand, the first electrical connector 410 realizes the electrical connection between the pins of the control chip 200 and the corresponding pins of the third memory chip 330 on the back of the control chip 200; 500 faces away from the side of the first main board 100, so that a through hole can be directly set in the first main board 100 to serve as a part of the first electrical connector 410 to lead the pins of the control chip 200 to the second main board 500 toward the first main board 500. One side of the main board 100, compared with setting blind holes in the first main board 100, simplifies the installation process of the first electrical connector 410 in the first main board 100, thereby improving the first electrical connector 410 in the first Setup efficiency within motherboard 100 .

It should be noted that a blind hole means that one end of the metal via hole does not penetrate to one surface of the main board such as the first main board 100 .

Continuing to refer to FIG. 3, each first electrical connector 410 may also include a first via hole 412, a first trace 413, and a second via hole 414 connected in sequence, and the first via hole 412, the first trace 413 and the second via hole 414 are located in the second main board 500 . Wherein, the first wiring 413 is arranged parallel to the first surface 110 of the first motherboard 100 . Wherein, the first trace 413 is a trace in the wiring layer parallel to the first surface 110 in the second main board 500, for example, the xoy plane, and the first trace 413 extends along the x direction.

It can be understood that, as an example, the wiring layer in the second main board 500 can be etched on one of the insulating dielectric layers among the multiple dielectric layers stacked and deposited along the z direction when the second main board 500 is manufactured, A plurality of wiring grooves extending along the x direction or the y direction are formed, and then a metal medium is filled in the wiring grooves, so that the metal medium forms a wiring for electrically connecting various components. The first trace 413 in the first electrical connection member 410 is one of the traces in the wiring layer extending along the x direction.

One end of the first trace 413 is electrically connected to the corresponding first through hole 411 through the first via hole 412, in other words, one end of the first via hole 412 is electrically connected to the first trace 413, and the first via hole 412 The other end is electrically connected to the corresponding first through hole 411 in the first motherboard 100 . The other end of the first wiring 413 is electrically connected to the corresponding pin of the third memory chip 330 through the second via 414, in other words, one end of the second via 414 is electrically connected to the first wiring 413, and the second via The other end of the hole 414 is electrically connected to the corresponding pin of the third memory chip 330 .

In practical applications, among the plurality of pins used to control the third memory chip 330 in the control chip 200, the distance between adjacent pins is the same as that of adjacent pins in the corresponding pins of the memory chip such as the third memory chip 330 The distances are different, which makes the pins of the control chip 200 and the corresponding pins of the third memory chip 330 staggered in a direction perpendicular to the first motherboard 100 , for example, in the z direction.

However, in the embodiment of the present application, the first wiring 413 is provided in the second main board 500, so that via holes can be provided at any position in the extending direction of the first wiring 413 to electrically connect the wires perpendicular to the first main board 100. The pins of the control chip 200 and the pins of the third memory chip 330 that are staggered in the z direction, for example, can be electrically connected to the first via hole 412 at the corresponding position on the side of the first wiring 413 facing the first motherboard 100 , and electrically connect the first via hole 412 with the corresponding first via hole 411, electrically connect the second via hole 414 at the corresponding position on the other side of the first trace 413, and connect the second via hole 414 The other end of the control chip 200 is electrically connected to the corresponding pin of the third memory chip 330, thereby realizing the electrical connection of the pin of the control chip 200 to the corresponding pin of the third memory chip 330 located on the back side of the control chip 200, that is, directly below, specifically The position of the first via hole 412 can be adjusted according to the position of the corresponding pin of the control chip 200 , and correspondingly, the position of the second via hole 414 can be adjusted according to the position of the corresponding pin of the third memory chip 330 .

FIG. 4 is another schematic structural diagram of a chip system provided by an embodiment of the present application. Referring to FIG. 4 , wherein, in some examples, the first via hole 412 and the second via hole 414 may be through holes through the second main board 500, so as to facilitate the fabrication of the first via hole 412 and the second via hole 414 . In addition, by setting the second main board 500 so that the through holes as the first via hole 412 and the second via hole 414 are arranged on the second main board 500, the number of through holes provided on the first main board 100 is reduced, thereby avoiding The structural stability of the first main board 100 is affected.

For example, both ends of the first via hole 412 can pass through the second main board 500 along the z direction, and any part of the first via hole 412 along the extension direction is electrically connected to the first wiring 413, so that the second main board 500 in the second main board 500 A via hole 412 is fabricated.

Similarly, both ends of the second via hole 414 can pass through the second main board 500 along the z direction, and any part of the second via hole 414 along the extending direction is electrically connected to the first wiring 413, so that the second main board 500 Fabrication of the second via hole 414 .

Referring to FIG. 3 , of course, in other examples, the first via hole 412 and the second via hole 414 may also be blind holes that do not penetrate the second main board 500 . For example, one end of the first via hole 412 facing away from the first main board 100 may extend to the first trace 413, that is, one end of the first via hole 412 does not penetrate to the front of the second main board 500, so that the first via hole 412 forms a blind hole. One end of the second via hole 414 facing the first main board 100 can extend to the first trace 413, that is, one end of the second via hole 414 does not penetrate to the back of the second main board 500, so that the second via hole 414 forms a blind. hole.

Referring to FIG. 3 , the side of the second main board 500 facing away from the first main board 100 may be provided with a plurality of third memory chips 330 at intervals, and the corresponding pins of each third memory chip 330 are connected to the control via corresponding electrical connectors. Corresponding pins of the chip 200 are electrically connected.

Referring to FIG. 3 , for example, two third memory chips 330 may be arranged at intervals on the side of the second motherboard 500 facing away from the first motherboard 100 , and the two third memory chips 330 are arranged at intervals along the x direction. For the convenience of description, the three third memory chips 330 arranged in sequence along the x direction can be used as the third memory chip a and the third memory chip b respectively.

When the control chip 200 is specifically connected to the two third memory chips 330, the electrical connection between the control chip 200 and the three third memory chips 330 can be realized through three first electrical connectors 410, for example, the three first electrical connections One end of the connection is electrically connected to the corresponding pin of the control chip 200. Among the three first electrical connectors 410, the other end of one of the first electrical connectors 410 is electrically connected to the corresponding pin of the third memory chip a, and the other end is electrically connected to the corresponding pin of the third memory chip a. The other end of the first electrical connection member 410 is electrically connected to the corresponding pin of the third memory chip b.

In the embodiment of the present application, by arranging a plurality of third memory chips 330 on the back of the control chip 200, the space on the back of the control chip 200 is further fully utilized, and a high-density memory layout is realized, thereby improving the total memory bandwidth of the first motherboard 100, and further Improves the total memory bandwidth of the entire system-on-a-chip.

Referring to FIG. 3 , in some examples, the number of the second via holes 414 in the first electrical connector 410 can be set to be multiple, and the multiple second via holes 414 are connected to the multiple third memory chips 330 respectively. Corresponding pins are electrically connected.

Continuing to take the example where two third memory chips 330 are arranged at intervals on the side of the second main board 500 facing away from the first main board 100, the number of the second via holes 414 of the first electrical connector 410 is two, and the two second via holes 414 are two. The via holes 414 are respectively the second via hole a and the second via hole b along the x direction, wherein each second via hole 414 overlaps with the corresponding pin of the corresponding third memory chip 330 in the z direction.

For example, one end of the second via hole a extends to the first trace 413 along the z direction, and the other end of the second via hole a extends to the back of the second motherboard 500 along the z direction, and is connected to the corresponding lead of the third memory chip a. One end of the second via hole b extends to the first trace 413 along the z direction, and the other end of the second via hole b extends to the back of the second motherboard 500 along the z direction, and is connected to the third memory chip b Corresponding pins are electrically connected.

In the embodiment of the present application, by setting a plurality of second via holes 414 in the first electrical connector 410, on the one hand, one of the pins of the control chip 200 is simultaneously connected with corresponding pins of a plurality of third memory chips 330. The electrical connection realizes the function of one drive and many drives.

On the other hand, by simultaneously connecting a plurality of second via holes 414 on one side of the first wiring 413, the electrical connection between the control chip 200 and the plurality of third memory chips 330 is more convenient, and the control is also simplified. The structure of the first electrical connectors 410 between the chip 200 and the plurality of third memory chips 330 reduces the number of the first electrical connectors 410 of the chip system and improves the assembly efficiency of the chip system.

1, it can be understood that when the third memory chip 330 is directly disposed on the second surface 120 of the first motherboard 100, the first through hole 411 and the first through hole 412 in the first electrical connector 410 The metal vias 410 a located in the first main board 100 are jointly formed. Both the first wiring 413 and the second via hole 414 in the first electrical connector 410 are located in the first main board 100 . It can be understood that the metal via 410a is a blind hole, one end of the metal via 410a is electrically connected to the pin of the control chip 200, and the other end of the metal via 410a is electrically connected to the first wiring 413, so that the control chip 200 The pins are electrically connected to the first wiring 413 through the metal via 410a.

Referring to FIG. 1 and FIG. 3 , in the embodiment of the present application, the second electrical connector 420 is used to electrically connect the control chip 200 with the first memory chip 310 and the second memory chip 320 . Taking the second electrical connector 420 electrically connecting the control chip 200 and the first memory chip 310 as an example, the second electrical connector 420 is provided corresponding to the pins of the control chip 200 that need to be electrically connected to the first memory chip 310 . It can be understood that the number of the second electrical connector 420 may be one or more. For example, when a pin of the control chip 200 needs to be electrically connected with a corresponding pin of the first memory chip 310, there is only one second electrical connector 420, and one end of the second electrical connector 420 is connected to the pin of the control chip 200. The other end of the second electrical connector 420 is electrically connected to the corresponding pin of the corresponding first memory chip 310 .

When multiple pins of the control chip 200 need to be electrically connected to multiple pins of the first memory chip 310, the number of the second electrical connectors 420 is the same as the pins used to electrically connect the first memory chip 310 on the control chip 200 The numbers are the same, so that multiple pins of the control chip 200 are electrically connected to corresponding pins of the first memory chip 310 through corresponding second electrical connectors 420, so that the control chip 200 can perform various operations on the first memory chip 310. Functional control.

Of course, in some examples, one end of a second electrical connector 420 is electrically connected to a pin of the control chip 200, and the other end of the second electrical connector 420 can also be connected to the first memory chip 310 and the second memory chip at the same time. Corresponding pins in the chip 320 are electrically connected, so that the control chip 200 can simultaneously control the first memory chip 310 and the second memory chip 320 through a second electrical connection 420 . Of course, in some examples, the control chip 200 can simultaneously control the first memory chip 310 , the second memory chip 320 and the third memory chip 330 through a second electrical connection 420 . The specific arrangement of the second electrical connector 420 can refer to the content below (refer to FIG. 3 and FIG. 4 ), and will not be described in detail here.

Referring to FIG. 1 and FIG. 3 , each second electrical connector 420 may include a third via hole 421 , a second trace 422 , a fourth via hole 423 and a fifth via hole 424 . One end of the third via hole 421 is electrically connected to the corresponding pin of the control chip 200, and the other end of the third via hole 421 is electrically connected to the second wiring 422, so that the corresponding pin of the control chip 200 passes through the third via hole. 421 is electrically connected to the second wire 422 .

One end of the fourth via hole 423 and the fifth via hole 424 are both electrically connected to the second wiring 422, and the other end of the fourth via hole 423 is electrically connected to the corresponding pin of the first memory chip 310, so that the second wiring 422 The fourth via hole 423 is electrically connected to the corresponding pin of the first memory chip 310 , so that the pin of the control chip 200 is electrically connected to the corresponding pin of the first memory chip 310 .

The other end of the fifth via hole 424 is electrically connected to the corresponding pin of the second memory chip 320, so that the second wiring 422 is electrically connected to the corresponding pin of the second memory chip 320 through the fifth via hole 424, so that the control chip The pins of 200 are electrically connected with the corresponding pins of the second memory chip 320 .

Wherein, the second wiring 422 of the second electrical connector 420 is arranged in the same manner as the first wiring 413 , for example, the second wiring 422 is arranged in the first main board 100 and is parallel to the first wiring of the first main board 100 . Surface 110 is provided. Wherein, the second trace 422 may be a trace in the wiring layer parallel to the first surface 110 in the first main board 100 , such as the xoy plane, and the second trace 422 extends along the x direction. It should be noted that, the wiring layer forming the second wiring 422 may be the above wiring layer forming the first wiring 413 . In some examples, the wiring layer forming the second wiring 422 may also be another wiring layer parallel to the above wiring layer forming the first wiring 413 .

In some examples, the number of the first memory chip 310 and the number of the second memory chip 320 can be one respectively, and the number of the fourth via hole 423 and the fifth via hole 424 of each second electrical connector 420 is also respectively one. indivual. For example, a first memory chip 310 and a second memory chip 320 are respectively arranged on both sides of the first motherboard 100, and one end of the fourth via hole 423 and the fifth via hole 424 are both electrically connected to the second wire 422, The other end of the fourth via hole 423 is electrically connected to the corresponding pin of the first memory chip 310, and the other end of the fifth via hole 424 is electrically connected to the corresponding pin of the second memory chip 320, so that the control chip 200 passes through the first memory chip 310. The two electrical connectors 420 are in stable electrical connection with corresponding pins on the second memory chip 320 and the third memory chip 330 at the same time.

Of course, as shown in FIG. 3 , in some other examples, a plurality of first memory chips 310 are arranged at intervals on the first surface 110 of the first motherboard 100 , and a plurality of second memory chips 310 are arranged at intervals on the second surface 120 of the first motherboard 100 . The memory chip 320 is to make full use of the space on the first motherboard 100, and further increase the number of memory chips on the first motherboard 100, thereby realizing a high-density layout of the memory, thereby increasing the total amount of memory on the first motherboard 100. bandwidth, thereby increasing the total memory bandwidth of the entire chip system.

Wherein, the number of the fourth via holes 423 is multiple, and one end of the multiple fourth via holes 423 is respectively electrically connected to the corresponding pins of the multiple first memory chips 310, and the number of the fifth via holes 424 is multiple, One ends of the plurality of fifth via holes 424 are respectively electrically connected to corresponding pins of the plurality of second memory chips 320 .

Referring to FIG. 3 , two first memory chips 310 are arranged at intervals on the first surface 110 of the first motherboard 100 and two second memory chips 320 are arranged at intervals on the second surface 120 of the first motherboard 100 as an example for illustration.

For the convenience of description, the two first memory chips 310 sequentially arranged along the x direction can be respectively referred to as the first memory chip a and the first memory chip b, wherein the first memory chip a is located on the left side of the first memory chip b. The two second memory chips 320 arranged in sequence along the x direction can be respectively referred to as the second memory chip a and the second memory chip b, wherein the second memory chip a is located on the left side of the second memory chip b.

The number of the fourth via hole 423 is two, and the two fourth via holes 423 are respectively the fourth via hole a and the fourth via hole b along the x direction, where the fourth via hole a corresponds to the first memory chip a The pins are electrically connected, and the fourth via b is electrically connected to the corresponding pins of the first memory chip b, so that one of the pins of the control chip 200 is connected to the corresponding pins of the two first memory chips 310 through a second electrical connector 420 pins are electrically connected.

In addition, the number of the fifth via hole 424 is two, and the two fifth via holes 424 are respectively the fifth via hole a and the fifth via hole b along the x direction, wherein the fifth via hole a and the second memory chip a The corresponding pins of the fifth via b are electrically connected to the corresponding pins of the second memory chip b, so that one of the pins of the control chip 200 is connected to the two second memory chips 320 through a second electrical connection 420 The corresponding pins are electrically connected.

Based on the above, one pin of the control chip 200 is electrically connected to the corresponding pins of the four memory chips 300 through a second electrical connector 420, so that one second electrical connector 420 realizes the function of driving multiple, that is, one control The chip 200 is electrically connected to the corresponding pins of multiple memory chips 300 at the same time, thereby simplifying the structure of the second electrical connector 420, reducing the number of the second electrical connector 420 in the chip system, so that the connection circuit in the chip system It is more regular and does not interfere with each other, which also improves the production efficiency of the chip system.

In addition, the electrical connection between the corresponding pins of the control chip 200 and the plurality of first memory chips 310 can be realized by adjusting the number and respective positions of the fourth via holes 423, and accordingly, the fifth via hole can be adjusted 424 and their respective positions, so as to realize the electrical connection between the corresponding pins of the control chip 200 and the plurality of second memory chips 320 .

FIG. 5 is another schematic structural diagram of a chip system provided by an embodiment of the present application. Referring to FIG. 5, in some examples, the first memory chip 310 and the second memory chip 320 located on different sides of the first motherboard 100 may be asymmetrical with respect to the first motherboard 100, that is to say, the first memory chip 310 and the second memory chip 320 are partially overlapped or staggered in the z direction perpendicular to the first main board 100 , so that the corresponding pins of the first memory chip 310 and the second memory chip 320 are staggered in the z direction.

For example, the first memory chip 310a and the second memory chip 320a are partially overlapped or staggered in the z direction, so that the corresponding pins of the first memory chip 310a and the second memory chip 320a are staggered in the z direction. And by setting the second electrical connector 420 to include the second trace 422, in this way, via holes such as the fourth via hole 423 and the fifth via hole 424 can be provided at any position in the extending direction of the second trace 422, The asymmetrical first memory chip 310 and the second memory chip 320 located on two sides of the main board (ie, the first main board 100 and the second main board 500 ) are simultaneously electrically connected.

3, the first memory chip 310 and the second memory chip 320 located on different sides of the first motherboard 100 can be arranged symmetrically with respect to the first motherboard 100, so that the first memory chip 310 and the second memory chip 320 Corresponding pins are provided in one-to-one correspondence in the z direction, that is to say, the pins of the first memory chip 310 and the corresponding pins of the second memory chip 320 overlap in the z direction, so that the fourth via hole 423 corresponds to the corresponding pin of the second memory chip 320 in the z direction. The fifth via hole 424 can be connected to form the second via hole 426 perpendicular to the first main board 100, so that the manufacturing process of the fourth via hole 423 and the fifth via hole 424 can be simplified, and the reliability of the second electrical connector 420 can be improved. Production efficiency.

For example, the first memory chip 310a and the second memory chip 320a overlap completely in the z direction, so that the corresponding pins of the first memory chip 310a and the second memory chip 320a overlap in the z direction, so that the fourth via hole 423 and The fifth via hole 424 can be connected to form a second via hole 426 perpendicular to the first main board 100 , that is to say, the extension direction of the second via hole 426 is consistent with the z direction.

FIG. 6 is another schematic structural diagram of a chip system provided by an embodiment of the present application. Referring to FIG. 6, in some examples, each second electrical connector 420 can also realize simultaneous electrical connection between the control chip 200 and the first memory chip 310, the second memory chip 320 and the third memory chip 330, for example , each second electrical connector 420 may also include a sixth via hole 425, one end of the sixth via hole 425 is electrically connected to the second wiring 422, and the other end of the sixth via hole 425 is connected to the corresponding end of the third memory chip 330. pins are electrically connected.

In the embodiment of the present application, the sixth via hole 425 is provided in the second electrical connector 420, so that the control chip 200 can communicate with the first memory chip 310, the second memory chip 320, and the third memory chip through the second electrical connector 420 at the same time. The corresponding pins in 330 are electrically connected, so that one second electrical connector 420 realizes the function of driving multiple, thereby simplifying the structure of the second electrical connector 420, reducing the number of second electrical connectors 420 in the chip system, Therefore, the connection circuits in the chip system are more regular and do not interfere with each other, and the production efficiency of the chip system is also improved.

In addition, by adjusting the position of the sixth via hole 425, the quick electrical connection between the control chip 200 and pins at different positions in the third memory chip 330 can be realized, thereby making it easier to connect the control chip 200 and the third memory chip 330. It is easier to connect pins with different numbers, different positions, and different pitches.

As shown in FIG. 3 , as a first possible implementation, the area of the projected area of the second main board 500 on the second surface 120 is smaller than the area of the second surface 120 , in other words, the second main board 500 occupies the area of the first main board 100 A portion of the second surface 120. For example, the extension length of the second main board 500 along the x direction is smaller than the extension length of the first main board 100 (refer to FIG. 3 ).

It can be understood that since the second main board 500 is provided with the third memory chip 330 , the second main board 500 and the control chip 200 have an overlapping area in a direction perpendicular to the first main board 100 (ie, the z direction). For example, at least part of the projected area of the second main board 500 along the z direction on the second surface 120 of the first main board 100 is located in the control chip arrangement area.

Referring to Fig. 3, in the above example, only the third memory chip 330 is arranged on the front side of the second motherboard 500, and the second memory chip 320 and the second motherboard 500 are arranged staggered in the direction perpendicular to the first motherboard 100, For example, the second memory chip 320 is directly disposed on the second surface 120 of the first motherboard 100 and is located on one side of the third memory chip 330 along the x direction.

Exemplarily, as shown in FIG. 3 , the control chip 200 and the second main board 500 are both located near the left side of the first main board 100 , the front of the second main board 500 is provided with a third memory chip 330 , and the second memory chip 320 directly It is disposed on the second surface 120 of the first main board 100 and is located on the right side of the second main board 500 .

During specific implementation, the second main board 500 and the third memory chip 330 disposed on the second main board 500 may be used as a whole as a chip component.

In the embodiment of the present application, the area of the projected area of the second main board 500 on the second surface 120 is set to be smaller than the area of the second surface 120, that is, the size of the second main board 500 with the third memory chip 330 is reduced, so that the third The chip assembly formed by the memory chip 330 and the second main board 500 is more portable and smart. On the one hand, it is convenient to manufacture the chip assembly, and on the other hand, it is convenient to assemble the chip assembly on the first main board 100 . In addition, the second memory chip 320 can be directly arranged in other areas of the second motherboard 500, so that the electrical connection structure between the second memory chip 320 and the control chip 200 can be simplified, and the number of connections between the second memory chip 320 and the control chip 200 can be reduced. The electrical connection path between them reduces the circuit impedance between the second memory chip 320 and the control chip 200, making the signal transmission between the second memory chip 320 and the control chip 200 more reliable.

Referring to FIG. 3 , in the above-mentioned first possible implementation manner, each first electrical connector 410 may further include a first solder ball 415 located between the second main board 500 and the first main board 100 , the first solder ball One end of the ball 415 is connected to the corresponding first through hole 411 in the first main board 100, and the other end of each first solder ball 415 is connected to the corresponding first via hole 412 in the second main board 500, so that the first main board 100 The first through hole 411 in the second motherboard 500 is electrically connected to the corresponding first through hole 412 in the second motherboard 500 through the first solder ball 415 .

In the embodiment of the present application, first solder balls 415 are arranged between the second main board 500 and the first main board 100 , and the first via holes 412 on the second main board 500 are soldered to the first main board 100 through the first solder balls 415 On the first through hole 411 of the first through hole 411, to improve the electrical connection stability between the first through hole 412 and the first through hole 411, in addition, the second main board 500 is welded on the first main board 100 through the first solder ball 415 , also improves the connection stability between the second main board 500 and the first main board 100, thereby further improving the electrical connection reliability between the first via hole 412 and the first through hole 411, ensuring that the pins of the control chip 200 Stable electrical connection with corresponding pins of the third memory chip 330 .

Because each first electrical connector 410 has a first solder ball 415, the first solder ball 415 in the plurality of first electrical connectors 410 is the same as the pin used to control the third memory chip 330 in the control chip 200. A corresponding setting, for example, the number of the first solder ball 415 is the same as the number of pins used to control the third memory chip 330 in the control chip 200, and the first solder ball 415 in each first electrical connection 410 is the same as the control chip 200. The corresponding pins of the chip 200 overlap in a direction perpendicular to the first main board 100, that is to say, each first solder ball 415 and the corresponding pin on the control chip 200 are along a direction parallel to the first main board 100, such as the x direction. In this way, it can be ensured that the first through hole 411 used to connect the first solder ball 415 and the corresponding pin of the control chip 200 is perpendicular to the first main board 100, so that the manufacturing process of the first through hole 411 is simpler. Therefore, the manufacturing efficiency of the electrical connector of the chip system is improved.

Continuing to refer to FIG. 3 , in the embodiment of the present application, the system-on-a-chip may also include a resistance-capacitance element 600, and the resistance-capacitance element 600 is arranged on the side of the second motherboard 500 facing the first motherboard 100, in other words, the resistance-capacitance element 600 It is arranged on the back side of the second motherboard 500, and the resistance-capacitance element 600 is arranged adjacent to the first solder ball 415, and the resistance-capacitance element 600 is electrically connected with the first solder ball 415, so that the resistance-capacitance element 600 can pass through the first solder ball 415. The ball 415 is electrically connected to a power supply pin among corresponding pins of the control chip 200 .

Wherein, the resistance-capacitance element 600 includes at least one of a termination resistor and a filter capacitor.

In the embodiment of the present application, a resistance-capacitance element 600 is provided at a position adjacent to the first solder ball 415 in the chip system, and the termination resistance therein realizes impedance matching in the first electrical connector 410, ensuring that the resistance in the first electrical connector 410 does not affect For signal transmission, the filter capacitor is used to absorb the current fluctuations generated by the first electrical connector 410 during operation and the interference that comes in series via the AC power supply, so that the working performance of the first electrical connector 410 is more stable.

In addition, because the resistance at the position where the first through hole 411 is connected to the first via hole 412 is relatively large, and the current fluctuation here is more obvious, the first The impedance matching or current stability at the connection between the through hole 411 and the first through hole 412 can further ensure the stability of signal transmission between the control chip 200 and the third memory chip 330 .

In addition, by arranging the resistance-capacitance element 600 on the side of the second main board 500 facing the first main board 100, in other words, setting the resistance-capacitance element 600 on the front of the second main board 500, to save the front space of the second main board 500 , thereby providing more space for the arrangement of the third memory chip 330 , thereby increasing the number of arrangement of the third memory chip 330 , so that the high-density layout of the first motherboard 100 improves the memory bandwidth of the first motherboard 100 .

It should be noted that the specific structure and working principle of the termination resistor or filter capacitor can directly refer to the related content of the termination resistor or filter capacitor in the prior art, and will not be repeated here.

In a specific configuration, there may be multiple RC elements 600 , and the RC elements 600 are arranged in one-to-one correspondence with the plurality of first solder balls 415 , and each RC element 600 is arranged adjacent to the corresponding first solder ball 415 .

For example, the number of the first solder balls 415 is 6, and the number of the RC elements 600 is also 6, and the 6 RC elements 600 are respectively arranged adjacent to the corresponding first solder balls 415, so as to ensure that each first electrical connection 410, the impedance matching or current stability at the connection between the first through hole 411 and the first through hole 412 also avoids crosstalk between the signals between two adjacent first electrical connectors 410 due to fluctuations, thereby ensuring that the control chip 200 Stability of signal transmission between each corresponding pin with the third memory chip 330 .

In some examples, the resistance-capacitance element 600 can also be arranged inside the second main board 500 to save the space on the back of the second main board 500, thereby providing a suitable setting space for setting the first solder ball 415 on the second main board 500, In order to facilitate the manufacture of the first solder ball 415 .

Referring to FIG. 5 , as a second possible implementation, the second main board 500 may be press-fitted on the second surface 120 of the first main board 100 . For example, the second main board 500 can be pressed on the second surface 120 of the first main board 100 through a high temperature pressing process. For the specific lamination process, reference may be made to relevant content in the prior art, and details will not be repeated here.

In the second feasible implementation manner, the second memory chip 320 and the third memory chip 330 are arranged at intervals on the side of the second motherboard 500 facing away from the first motherboard 100, that is to say, the second memory chip 320 and the third memory chip The third memory chips 330 are arranged at intervals on the front side of the second motherboard 500 .

It can be understood that, in this example, the second main board 500 may be the same as the first main board 100 along the cross-sectional dimension parallel to the first main board 100, that is to say, the length and width dimensions of the second main board 500 and the first main board 100 They can be the same respectively, so that the second memory chip 320 is also arranged on the front side of the second motherboard 500 .

In the embodiment of the present application, by pressing the second main board 500 on the second surface 120 of the first main board 100, on the one hand, it ensures the stability of the connection between the second main board 500 and the first main board 100, and ensures the integrity of the entire chip system. Structural stability, on the other hand, compared with a single main board, it not only realizes the electrical connection between the corresponding pins that are vertically staggered, but also allows one of the main boards, such as the first main board 100, to be used as an electrical connector. A part of the through hole, the through hole is a blind hole in the whole board formed after the first main board 100 and the second main board 500 are pressed together, that is to say, a part of the blind hole can be directly made on the first main board 100 The through hole is realized, and because the manufacturing process of the through hole is simpler than that of the blind hole, the manufacturing process of the electrical connector such as the first electrical connector 410 in the chip system is simplified.

Referring to Fig. 1, Fig. 3 and Fig. 4, the arrangement of the second electrical connector 420 is applicable to the structure shown in Fig. 1, Fig. 3 and Fig. 4, that is, when the second memory chip 320 is directly disposed When on the second surface 120 of the motherboard 100 , the corresponding pins on the control chip 200 can be electrically connected to the corresponding pins of the first memory chip 310 and the second memory chip 320 through the above-mentioned second electrical connector 420 at the same time.

It can be understood that when the second memory chip 320 is directly disposed on the second surface 120 of the first motherboard 100 , the third via hole 421 , the second trace 422 , the fourth via hole 423 and the second electrical connector 420 The five vias 424 are all located in the first main board 100 .

Referring to FIG. 5, the arrangement of the second electrical connector 420 can be applied to the structure shown in FIG. The electrical connection between the control chip 200 and the first memory chip 310 and the second memory chip 320 is realized respectively.

6, in this example, that is, when the second memory chip 320 is arranged on the front side of the second motherboard 500, the second wiring 422 can be located in the second motherboard 500, so that the second electrical connector 420 The third via hole 421 and the fourth via hole 423 both include through holes located in the first main board 100, making the part of the second electrical connector 420 located in the first main board 100 easier to manufacture, thereby improving the first in the chip system. The manufacturing efficiency of the two electrical connectors 420 .

FIG. 7 is another schematic structural diagram of a chip system provided by an embodiment of the present application. Referring to FIG. 7 , in some examples, the part of the third via hole 421 located on the second main board 500 may be a through hole penetrating through the second main board 500, and the part of the fourth via hole 423 located on the second main board 500 may be a through hole penetrating through the second main board 500. The through hole of the second main board 500 , the fifth via hole 424 may be a through hole penetrating through the second main board 500 .

Referring to FIG. 7 , specifically, when the second wiring 422 is located in the second main board 500, the third via hole 421 may include the first vias sequentially arranged along the extending direction (refer to the opposite direction of z in FIG. 5 ). A part 421a and a second part 421b, wherein the first part 421a is a through hole formed in the first main board 100, and the second part 421b may be a blind hole located in the second main board 500 (shown with reference to FIG. 6 ), the blind One end of the hole extends to the second trace 422 . Of course, referring to FIG. 7 , in some examples, the second part 421b can also be a through hole penetrating through the second motherboard 500, as long as any part of the second part 421b along the extending direction is guaranteed to communicate with the second wiring 422 That's it.

Correspondingly, the fourth via hole 423 includes a third part 423a and a fourth part 423b arranged in sequence along the extension direction (refer to the opposite direction of z in FIG. 5 ), wherein the third part 423a is formed on the first main board 100 The fourth part 423b may be a blind hole (shown in FIG. 6 ) in the second main board 500 , and one end of the blind hole extends to the second trace 422 . Of course, referring to FIG. 7 , in some examples, the fourth part 423b can also be a through hole penetrating through the second motherboard 500, as long as any part of the fourth part 423b along the extending direction is ensured to communicate with the second wiring 422 That's it.

In addition, the fifth via hole 424 is located in the second main board 500 . It can be understood that the fifth via hole 424 may be a blind hole located in the second main board 500 (refer to FIG. 6 ), one end of the blind hole extends to the front of the second main board 500, and the other end of the blind hole extends to The second trace 422 . Certainly, as shown in FIG. 7 , in some examples, the fifth via hole 424 may also be a through hole penetrating the second main board 500 , as long as any part of the fifth via hole 424 along the extending direction is guaranteed to be compatible with the second trace. 422 can be connected.

By setting the second part 421b of the third via hole 421 as a through hole penetrating the second main board 500, setting the fourth part 423b of the fourth via hole 423 as a through hole penetrating the second main board 500, and disposing the fifth via hole 424 The through hole passing through the second main board 500 makes the electrical connector 400 in the second main board 500 easier to manufacture.

In addition, by setting the second motherboard 500 and the above-mentioned second electrical connector 420, on the one hand, the electrical connection between the asymmetrical pins in the first memory chip 310 and the second memory chip 320 is ensured; The via hole portion of the second electrical connector 420 can be set to include a through hole penetrating through the first main board 100 and a through hole penetrating through the second main board 200, which simplifies the manufacturing process of the entire second electrical connector 420 and improves the chip system. production efficiency.

In addition, the third via hole 421, the fourth via hole 423 and the fifth via hole 424 are connected to the second memory chip 320. Part of the hole section only passes through the second main board 500, which also reduces the number of through holes set in the first main board 100. quantity, so as to avoid affecting the stability of the first motherboard 100 .

It can be understood that when the second wiring 422 is located in the second main board 500 , the sixth via hole 425 may be located in the second main board 500 . It can be understood that the sixth via hole 425 may be a blind hole located in the second motherboard 500, one end of the blind hole extends to the front of the second motherboard 500, and is electrically connected to the corresponding pin of the third memory chip 330, the The other end of the blind hole extends to the second trace 422 (shown in FIG. 6 ).

Certainly, the sixth via hole 425 may also be a through hole penetrating the second main board 500, as long as any part of the sixth via hole 425 along the extending direction is in communication with the second trace 422 (refer to FIG. 7 ) .

FIG. 8 is another schematic structural diagram of a chip system provided by an embodiment of the present application. Referring to FIG. 8, when the second memory chip 320 is arranged on the front side of the second motherboard 500, the second wiring 422 can also be located in the first motherboard 100, so that a part of the fifth via hole 424 can be formed on the The through hole in the second main board 500 facilitates the fabrication of the second electrical connector 420 in the second main board 500 .

Referring to FIG. 8, specifically, when the second memory chip 320 is arranged on the front side of the second motherboard 500, and the second wiring 422 is located in the first motherboard 100, the third via hole 421 may be formed on the first motherboard 500. A blind hole in the motherboard 100, one end of the blind hole extends to the first surface 110 of the first motherboard 100, and is electrically connected to the corresponding pin of the control chip 200, and the other end of the third via hole 421 extends to the second wiring 422 , so that the pins of the control chip 200 are electrically connected to the second wiring 422 through the third via 421 . Of course, in some examples, the third via hole 421 may also be a through hole penetrating through the first motherboard 100 , as long as any part of the third via hole 421 along the extending direction is ensured to communicate with the second wiring 422 .

The fourth via hole 423 may be a blind hole formed in the first motherboard 100, one end of the blind hole extends to the first surface 110 of the first motherboard 100, and is electrically connected to the corresponding pin of the first memory chip 310, the second The other end of the four vias 423 extends to the second wiring 422 , so that the pins of the memory chip are electrically connected to the second wiring 422 through the fourth vias 423 . Of course, in some examples, the fourth via hole 423 may also be a through hole penetrating through the first motherboard 100 , as long as any part of the fourth via hole 423 along the extending direction is ensured to communicate with the second wiring 422 .

The fifth via hole 424 includes a fifth part 424a and a sixth part 424b connected in sequence along the extending direction (refer to the opposite direction of z in FIG. One end of the blind hole extends to the second surface 120 of the first motherboard 100 , and the other part of the blind hole extends to the second trace 422 to be electrically connected to the second trace 422 . It can be understood that the fifth portion 424a may also be a through hole penetrating through the first motherboard 100 , as long as any part of the fifth portion 424a along the extending direction is ensured to communicate with the second wiring 422 .

The sixth part 424b may be a through hole formed in the second main board 500, that is to say, the through hole runs through the second main board 500, and one end of the through hole is electrically connected to the corresponding pin of the second memory chip 320. The other end of the through hole is electrically connected to the corresponding fifth portion 424a.

With reference to Fig. 3 and shown in Fig. 5, the thickness of the second main board 500 of the embodiment of the present application can be less than the thickness of the first main board 100, like this, has simplified the manufacturing process that blind hole is set on the second main board 500, thereby has improved chip. The manufacturing efficiency of the electrical connectors of the system, such as the first electrical connector 410 or the second electrical connector 420 .

In addition, by miniaturizing the second main board 500, that is, reducing the size of the second main board 500 on which the third memory chip 330 is arranged, the second main board 500 is more convenient to be assembled on the first main board 100, and the whole chip system is thinner and thinner. change.

Of course, in some examples, the thickness of the second main board 500 and the thickness of the first main board 100 can also be equal (not shown in the figure), so that it is possible to prevent the second main board 500 and the first main board 100 from appearing in the pressing process. The situation of uneven stress occurs, so as to ensure the pressing effect of the first main board 100 and the second main board 500 . In addition, the number of wiring layers in the second main board 500 and the first main board 100 can also be equal, which can further avoid the occurrence of uneven stress during the pressing process between the second main board 500 and the first main board 100 .

Referring to FIG. 3 , at least one of each first electrical connector 410 and second electrical connector 420 may further include a second solder ball 416, and the pins of the control chip 200 are electrically connected to the The first surface 110 of the first main board 100 is to improve the connection stability between the control chip 200 and the first main board 100, thereby also ensuring that the pins of the control chip 200 and the metal vias in the first main board 100 (such as the first main board 100) The stability of the electrical connection between a through hole 411).

Exemplarily, each first electrical connector 410 may further include a second solder ball 416, one end of the second solder ball 416 is electrically connected to the pin of the control chip 200, and the other end of the second solder ball 416 It is electrically connected with the first through hole 411 , so that the pins of the control chip 200 are electrically connected with the first through hole 411 through the second solder ball 416 .

3, for example, when the first electrical connector 410 includes a first solder ball 415, the pins of the control chip 200 can pass through the second solder ball 416, the first through hole 411, the first solder ball 415, The first via hole 412 , the first wire 413 and the second via hole 414 are electrically connected to corresponding pins of the third memory chip 330 .

In addition, each second electrical connector 420 may also include a second solder ball 416, one end of the second solder ball 416 is electrically connected to the pin of the control chip 200, and the other end of the second solder ball 416 is connected to the third terminal. The holes 421 are electrically connected, so that the pins of the control chip 200 are electrically connected to the third via holes 421 through the second solder balls 416 .

3, the pins of the control chip 200 can be electrically connected to the corresponding pins of the first memory chip 310 through the second solder ball 416, the third via hole 421, the second trace 422 and the fourth via hole 423 in turn. .

Referring to FIG. 3 , at least one of each first electrical connector 410 and second electrical connector 420 may also include a third solder ball 417, and the pins of the memory chip are welded on the first solder ball 417 through the third solder ball. the second surface 120 of the motherboard 100 to improve the stability of the connection between the memory chip 300 and the first motherboard 100, thereby also ensuring that the pins of the memory chip 300 and the metal vias (such as the fourth pass) in the first motherboard 100 The stability of the electrical connection between holes 423).

Exemplarily, each first electrical connector 410 may further include a third solder ball 417, one end of the third solder ball 417 may be electrically connected to a pin of the third memory chip 330, and the other end of the second solder ball 416 One end is electrically connected to the corresponding second via hole 414 , so that the pin of the third memory chip 330 is electrically connected to the second via hole 414 through the third solder ball 417 .

3, for example, when the first electrical connector 410 includes a first solder ball 415, the pins of the control chip 200 can pass through the second solder ball 416, the first through hole 411, the first solder ball 415, The first via hole 412 , the first wire 413 , the second via hole 414 and the third solder ball 417 are electrically connected to corresponding pins of the third memory chip 330 .

In addition, each second electrical connector 420 may further include a third solder ball 417 , and the first memory chip 310 or the second memory chip 320 may be soldered on the first motherboard 100 through the third solder ball 417 . For example, the first memory chip 310 can be welded on the first surface 110 of the first motherboard 100 through the third solder ball 417, and the second memory chip 320 can be soldered on the second surface 120 or the second surface of the first motherboard 100 through the third solder ball 417. The front side of the second motherboard 500 .

Taking the first memory chip 310 as an example, one end of the third solder ball 417 is electrically connected to the pin of the first memory chip 310, and the other end of the third solder ball 417 is electrically connected to the fourth via hole 423, so that the first memory chip The pins of 310 are electrically connected to the fourth via hole 423 through the third solder ball 417 . Referring to FIG. 3 , the pins of the control chip 200 can pass through the second solder ball 416, the third via hole 421, the second trace 422, the fourth via hole 423 and the third solder ball 417 to connect with the first memory chip 310 in sequence. The corresponding pins are electrically connected.

In the embodiment of the present application, by setting the above-mentioned chip system in the electronic device, by setting the control chip 200 and the memory chip 300 such as the first memory chip 310 on the first surface 110 of the first motherboard 100, that is, the first memory chip 310 is located in the control chip 200, a plurality of memory chips 300 are arranged on the second surface 120 of the first main board 100, wherein a part of the memory chips 300 located on the second surface 120 of the first main board 100, such as the second memory chip 320 and the control chip 200 are arranged in a staggered manner, Another part of the memory chip 300 such as the third memory chip 330 is arranged on the front and back of the control chip 200, that is, the third memory chip 330 and the control chip 200 have an overlapping area in the direction perpendicular to the first main board 100, so that the first main board 100 The space is fully utilized, increasing the number of memory chips on the first motherboard 100, thereby realizing a high-density memory layout, improving the total memory bandwidth of the entire chip system, and further improving the storage performance of the electronic device.

It should be understood that "electrical connection" in this application can be understood as the physical contact and electrical conduction of components; it can also be understood as an entity that can transmit electrical signals between different components in the circuit structure through printed circuit board copper foil or wires, etc. The form in which the lines are connected.

In the description of the embodiments of the present application, it should be noted that unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a An indirect connection through an intermediary may be an internal communication between two elements or an interaction relationship between two elements. Those of ordinary skill in the art can understand the specific meanings of the above terms in the embodiments of the present application according to specific situations.

The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of the embodiments of the present application and the above drawings are used to distinguish similar objects, while It is not necessarily used to describe a particular order or sequence.

Claims (23)

1. A chip system, characterized in that it comprises a first motherboard, a control chip, and a plurality of memory chips electrically connected to the control chip; The first motherboard includes a first surface and a second surface opposite to each other, the control chip is arranged on the first surface of the first motherboard, and the plurality of memory chips include a first memory chip and a second memory chip. and a third memory chip, the first memory chip is arranged on the first surface of the first motherboard, and the second memory chip and the third memory chip are arranged at intervals on the second surface of the first motherboard; Wherein, the third memory chip and the control chip have an overlapping area in a direction perpendicular to the first motherboard, and the second memory chip and the control chip have an overlapping area in a direction perpendicular to the first motherboard Stagger settings. 2. The chip system according to claim 1, wherein the chip system further comprises a second motherboard; The second main board is disposed on the second surface of the first main board, and the third memory chip is disposed on a side of the second main board facing away from the first main board. 3. The chip system according to claim 2, wherein the chip system comprises a plurality of first electrical connectors; Each of the first electrical connectors includes a first through hole formed in the first motherboard, one end of each of the first through holes is electrically connected to a corresponding pin of the control chip, and each of the The other end of the first through hole is electrically connected to the corresponding pin of the third memory chip. 4. The chip system according to claim 3, wherein each of the first electrical connectors further comprises a first via hole, a first trace and a second via hole connected in sequence, and the first The vias, the first wiring and the second vias are all located in the second main board; The first wiring is arranged parallel to the first surface of the first main board, one end of the first wiring is electrically connected to the corresponding first through hole through the first via hole, and the first The other end of the wire is electrically connected to a corresponding pin of the third memory chip through the second via hole. 5 . The chip system according to claim 4 , wherein the first via hole and the second via hole are both through holes penetrating the second main board. 6. The chip system according to claim 4 or 5, wherein a plurality of third memory chips are arranged at intervals on a side of the second main board facing away from the first main board, each of the third memory chips The corresponding pins of the three memory chips are electrically connected to the corresponding pins of the control chip through the corresponding electrical connectors. 7. The chip system according to claim 6, wherein the number of the second via holes is multiple, and the multiple second via holes are respectively connected to the corresponding pins of the multiple third memory chips. electrical connection. 8. The system-on-a-chip according to any one of claims 2-7, wherein the system-on-a-chip comprises a plurality of second electrical connectors, and each of the second electrical connectors includes a third via hole, The second trace, the fourth via hole and the fifth via hole; One end of the third via is electrically connected to the corresponding pin of the control chip, the other end of the third via is electrically connected to the second wiring, and the fourth via and the fifth One end of the via hole is electrically connected to the second trace; The other end of the fourth via is electrically connected to the corresponding pin of the first memory chip, and the other end of the fifth via is electrically connected to the corresponding pin of the second memory chip. 9. The chip system according to any one of claims 2-8, wherein the area of the projected area of the second motherboard on the second surface is smaller than the area of the second surface; The second memory chip and the second main board are staggered in a direction perpendicular to the first main board. 10. The chip system according to claim 9, wherein among the plurality of first electrical connectors of the chip system, each of the first electrical connectors further includes a first solder balls between the first main boards; One end of the first solder ball is connected to the corresponding first through hole in the first main board, and the other end of the first solder ball is connected to the corresponding first through hole in the second main board. 11. The chip system according to claim 10, characterized in that, the first solder balls in each of the first electrical connectors and the corresponding pins of the control chip are perpendicular to the first motherboard overlap in the direction. 12. The system-on-a-chip according to claim 10 or 11, wherein the system-on-a-chip further comprises a resistance-capacitance element; The resistance-capacitance element is arranged on the side of the second main board facing the first main board, and the resistance-capacitance element is arranged adjacent to the first solder ball, and the resistance-capacitance element and the first solder ball electrical connection; Wherein, the resistance-capacitance element includes at least one of a termination resistor and a filter capacitor. 13. The chip system according to claim 12, wherein there are a plurality of the resistance-capacitance elements, and the plurality of resistance-capacitance elements are arranged in one-to-one correspondence with the plurality of the first solder balls; And each of the resistance-capacitance elements is disposed adjacent to the corresponding first solder ball. 14. The chip system according to any one of claims 2-8, wherein the second main board is press-fitted on the second surface of the first main board; The second memory chip and the third memory chip are arranged at intervals on a side of the second main board facing away from the first main board. 15 . The chip system according to claim 14 , wherein, in each second electrical connector of the chip system, the second wiring is located in the second motherboard. 16 . 16. The chip system according to claim 15, wherein the part of the third via hole of the second electrical connector located on the second main board is a through hole penetrating through the second main board, and the first The part of the fourth via hole of the second electrical connector located on the second main board is a through hole penetrating the second main board, and the fifth via hole of the second electrical connector is a through hole penetrating the second main board. . 17. The chip system according to claim 15 or 16, wherein each of the second electrical connectors further includes a sixth via hole located in the second motherboard, one end of the sixth via hole The other end of the sixth via is electrically connected to the corresponding pin of the third memory chip. 18 . The chip system according to claim 15 , wherein, in each second electrical connector of the chip system, the second wiring is located in the first motherboard. 19 . 19. The chip system according to any one of claims 2-18, wherein the second memory chip and the first memory chip are arranged symmetrically with respect to the first motherboard; In each second electrical connector of the chip system, the fourth via hole communicates with the corresponding fifth via hole to form a second via hole perpendicular to the first main board. 20. The chip system according to any one of claims 2-19, wherein a plurality of first memory chips are arranged at intervals on the first surface of the first motherboard, and the fourth via hole of the chip system The number is multiple, and one end of the multiple fourth via holes is respectively electrically connected to the corresponding pins of the multiple first memory chips; Alternatively, the side of the second motherboard facing away from the first motherboard is provided with a plurality of second memory chips at intervals, the number of fifth via holes in the chip system is multiple, and the plurality of fifth via holes One end of each is electrically connected to corresponding pins of the plurality of second memory chips. 21. The chip system according to any one of claims 1-20, wherein at least one of each first electrical connector and each second electrical connector of the chip system further includes a second Solder balls, the pins of the control chip are electrically connected to the first surface of the first motherboard through the second solder balls. 22. The chip system according to any one of claims 1-21, wherein at least one of each first electrical connector and each second electrical connector of the chip system further includes a third Solder balls, the pins of the memory chip are welded on the first motherboard through the third solder balls. 23. An electronic device, comprising the chip system according to any one of claims 1-22.

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