CN116073810B - Electronic system and chip - Google Patents

Abstract

The invention provides an electronic system and a chip. The chip comprises a first welding pad, a second welding pad, a first voltage-controlled current element, a second voltage-controlled current element, a first biasing element and a second biasing element. The first to third bonding pads are respectively coupled with the drain electrode, the source electrode and the grid electrode of the first gallium nitride transistor, and the third to fifth bonding pads are respectively coupled with the drain electrode, the source electrode and the grid electrode of the second gallium nitride transistor. The first voltage-controlled current element is coupled to the first and the second welding pads. The second voltage-controlled current element is coupled to the third and fourth bonding pads. The first biasing element is coupled to the second and third pads. The second biasing element is coupled to the fourth and fifth pads. The first bias element adjusts the bias voltage of the second welding pad according to the control of the first voltage-controlled current element, and the second bias element adjusts the bias voltage of the fourth welding pad according to the control of the second voltage-controlled current element.

Description

Electronic system and chip

Technical Field

The present invention relates to a system and a chip, and more particularly, to an electronic system and a chip for coupling to a gallium nitride transistor.

Background

Gallium nitride (GaN) transistors are widely used for some advantages. On the other hand, gallium nitride transistors have low threshold voltages, which often results in large power consumption in the circuit.

Some enhanced (e-mode) gallium nitride transistors have been proposed in the prior art in an attempt to reduce the power consumption of the gallium nitride transistors. However, these enhancement-type gan transistors often require special processes to change the structure of the gan transistor, or by connecting the transistor in series (cascode) with the gan transistor, which often results in higher manufacturing cost, or the current of the gan transistor is limited by the transistors connected in series, thereby affecting the circuit performance of the gan transistor.

Disclosure of Invention

The invention is directed to an electronic system and chip that can improve the manufacturing cost of gallium nitride transistors without affecting the circuit performance of the gallium nitride transistors themselves.

According to an embodiment of the invention, the chip includes first to fifth pads, first and second voltage-controlled current elements, first and second bias elements. The first to third bonding pads are respectively coupled with the drain electrode, the source electrode and the grid electrode of the first gallium nitride transistor, and the third to fifth bonding pads are respectively coupled with the drain electrode, the source electrode and the grid electrode of the second gallium nitride transistor. The first voltage-controlled current element is coupled to the first and the second welding pads. The second voltage-controlled current element is coupled to the third and fourth bonding pads. The first biasing element is coupled to the second and third pads. The second biasing element is coupled to the fourth and fifth pads. The first bias element adjusts the bias voltage of the second welding pad according to the control of the first voltage-controlled current element, and the second bias element adjusts the bias voltage of the fourth welding pad according to the control of the second voltage-controlled current element.

According to an embodiment of the invention, an electronic system includes a chip, a first and a second gallium nitride transistor. The source of the first gallium nitride transistor is coupled to the drain of the second gallium nitride transistor. The chip comprises a first welding pad, a second welding pad, a first voltage-controlled current element, a second voltage-controlled current element, a first biasing element and a second biasing element. The first to third bonding pads are respectively coupled with the drain electrode, the source electrode and the grid electrode of the first gallium nitride transistor, and the third to fifth bonding pads are respectively coupled with the drain electrode, the source electrode and the grid electrode of the second gallium nitride transistor. The first voltage-controlled current element is coupled to the first and the second welding pads. The second voltage-controlled current element is coupled to the third and fourth bonding pads. The first biasing element is coupled to the second and third pads. The second biasing element is coupled to the fourth and fifth pads. The first bias element adjusts the bias voltage of the second welding pad according to the control of the first voltage-controlled current element, and the second bias element adjusts the bias voltage of the fourth welding pad according to the control of the second voltage-controlled current element.

Based on the above, the electronic system and the chip of the present invention control the operation of the gan transistor to be turned on and/or turned off by the coupling relationship of the gan transistor, the bias element and the voltage-controlled current element.

The electronic system and the chip can better control the on and/or off of the gallium nitride transistor without changing the structure of the gallium nitride transistor by an additional process and retaining the advantages of high current and quick switching of the gallium nitride transistor, thereby effectively avoiding the leakage current of the gallium nitride transistor and further improving the overall power consumption of the electronic system.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a block diagram of an electronic system according to an embodiment of the invention;

FIG. 2 is a block diagram of an electronic system according to an embodiment of the invention;

FIG. 3 is a block diagram of an electronic system according to an embodiment of the invention.

Description of the reference numerals

1.2, 3, An electronic system;

10. 20, 30 parts of a chip;

11. A driving circuit;

12, an upper bridge circuit;

13, a lower bridge circuit;

14. 16, 24, 26, 34, voltage controlled current elements;

15. 17, 25, 27;

38 bootstrap circuit;

210 a power supply circuit;

211, a controller;

212, a level shift circuit;

P1-P5 are bonding pads;

C1 and C2 are capacitors;

d1, a diode;

DS1, DS 2;

DS1', DS2': control signals;

GT1, GT2, gallium nitride transistors;

HVDD, GND, reference voltage;

MN1, MP 2;

R1-R4 are resistors;

T1, T2 and T3 are power transistors;

ZD1, ZD2, zener diode.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

Fig. 1 is a block diagram of an electronic system 1 according to an embodiment of the invention. The electronic system 1 comprises a chip 10 and gallium nitride transistors GT1, GT2. The chip 10 is provided with bonding pads P1-P5, and the chip 10 is coupled to the GaN transistors GT1, GT2 through the bonding pads P1-P5. The chip 10 may be used to drive gallium nitride transistors GT1, GT2.

In one embodiment, the gan transistors GT1 and GT2 may be gan transistors of a first on-type (e.g., n-type) that are turned on when a voltage difference received between their gates and sources is greater than or equal to a threshold voltage. The drain, source and gate of the GaN transistor GT1 may be coupled to the pads P1, P2 and P3, respectively. The drain, source and gate of the GaN transistor GT2 may be coupled to the pads P3, P4 and P5, respectively. On the other hand, the drain of the gan transistor GT1 may receive the reference voltage HVDD, and the source of the gan transistor GT2 may receive the reference voltage GND.

The chip 10 includes a driving circuit 11, an upper bridge circuit 12, a lower bridge circuit 13, voltage-controlled current elements 14, 16, and bias elements 15, 17. The voltage-controlled current device 14 has a first end and a second end, and is coupled to the pad P1 and the pad P2, respectively. The voltage-controlled current device 16 has a first end and a second end, and is coupled to the pad P3 and the pad P4, respectively. The upper bridge circuit 12 is coupled to the control terminal of the voltage-controlled current element 14, and the lower bridge circuit 13 is coupled to the control terminal of the voltage-controlled current element 16. The driving circuit 11 is coupled to the upper bridge circuit 12 and the lower bridge circuit 13.

In detail, the driving circuit 11 can generate driving signals DS1 and DS2 for controlling the operations of the upper and lower bridge circuits 12 and 13. The upper bridge circuit 12 and the lower bridge circuit 13 can generate control signals DS1 'and DS2' according to the driving signals DS1 and DS2, respectively, so as to control the voltage-controlled current devices 14 and 16 to selectively generate bias currents. When the voltage-controlled current device 14 generates a bias current, the bias current is provided to the bias device 15 to raise the voltage of the pad P2, so that the voltage difference between the gate and the source of the gan transistor GT1 is reduced to be less than a threshold voltage (e.g., -11V), resulting in turning off the gan transistor GT1 and disconnecting the drain and the source of the gan transistor GT 1. Similarly, when the voltage-controlled current device 16 generates a bias current, the bias current is provided to the bias device 17 to raise the voltage of the pad P4, so that the voltage difference between the gate and the source of the gan transistor GT2 is reduced to be less than the threshold voltage (e.g., -11V), resulting in turning off the gan transistor GT2 and disconnecting the drain and the source of the gan transistor GT 2.

Therefore, the chip 10 can control on and/or off of the gan transistor GT1 through the voltage-controlled current element 14 and the bias element 15, and control on and/or off of the gan transistor GT2 through the voltage-controlled current element 16 and the bias element 17. Specifically, when the voltage-controlled current device 14 is enabled or turned on, the voltage difference between the gate and the source of the gan transistor GT1 is reduced to be turned off, so that the gan transistor GT1 is preferably controlled to be disabled, and the leakage current of the gan transistor GT1 is avoided, thereby improving the power consumption.

In some embodiments, the voltage-controlled current device 14, the bias device 15 and the gan transistor GT1 can be regarded as a power transistor T1 as a whole to operate, and the power transistor T1 can have a first conduction type or a second conduction type, and the second conduction type (e.g., p-type) is exemplified below. A first terminal of the power transistor T1 (e.g., a drain of the power transistor T1) may be coupled to the pad P3, a second terminal of the power transistor T1 (e.g., a source of the power transistor T1) may receive the reference voltage HVDD, and a control terminal of the power transistor T1 (e.g., a gate of the power transistor T1) may receive the control of the upper bridge circuit 12. The power transistor T1 may control the conduction between the first terminal and the second terminal according to the voltage received by the control terminal.

When the control terminal of the power transistor T1, i.e. the voltage-controlled current element 14 receives the enabled control signal DS1', the gan transistor GT1 is turned off according to the control of the control signal DS1', and the voltage difference between the gate and the source of the gan transistor GT1 is greater than the threshold voltage when the voltage-controlled current element 14 does not provide the bias current to the bias element 15, so that the power transistor T1 is turned on. In contrast, when the control terminal of the power transistor T1 receives the disable control signal DS1', the gan transistor GT1 is turned on according to the control of the control signal DS1' to provide the bias current to the bias device 15, such that the source voltage of the gan transistor GT1 increases, and thus the voltage difference between the gate and the source of the gan transistor GT1 is smaller than the threshold voltage, so that the power transistor T1 is turned off.

Similarly, the voltage-controlled current device 16, the bias device 17 and the gan transistor GT2 can be regarded as a power transistor T2 as a whole to operate, and the power transistor T2 can have a first conduction type or a second conduction type, and the power transistor T2 is described below as an example having the first conduction type (for example, n-type). A first terminal of the power transistor T2 (e.g., a drain of the power transistor T2) may be coupled to the pad P3, a second terminal of the power transistor T2 (e.g., a source of the power transistor T2) may be coupled to the pad P5, and a control terminal of the power transistor T2 (e.g., a gate of the power transistor T2) may receive control of the lower bridge circuit 13. The power transistor T2 may control the conduction between the first terminal and the second terminal according to the voltage received by the control terminal.

When the control terminal of the power transistor T2, i.e. the voltage-controlled current element 16 receives the enabled control signal DS2', the gan transistor GT2 is turned off according to the control of the control signal DS2', and the voltage difference between the gate and the source of the gan transistor GT2 is greater than the threshold voltage when the voltage-controlled current element 16 does not provide the bias current to the bias element 17, so that the power transistor T2 is turned on. In contrast, when the control terminal of the power transistor T2 receives the disable control signal DS2', the gan transistor GT2 is turned on according to the control of the control signal DS2' to provide the bias current to the bias device 17, so that the source voltage of the gan transistor GT2 increases, and the voltage difference between the gate and the source of the gan transistor GT2 is smaller than the threshold voltage, so that the power transistor T2 is turned off.

Therefore, the electronic system 1 and the chip 10 can preferably control the on and/or off states of the gan transistors GT1, GT2 through the coupling relationship between the voltage-controlled current elements 14, 16 and the bias elements 15, 17 and the gan transistors GT1, GT2, so as to improve the overall power consumption. On the other hand, since the voltage-controlled current elements 14 and 16 are not connected in series with the gan transistors GT1 and GT2, the voltage-controlled current elements 14 and 16 do not limit the on-current of the gan transistors GT1 and GT2, and the advantages of high current and fast switching of the gan transistors GT1 and GT2 can be effectively maintained.

Fig. 2 is a schematic diagram of an electronic system 2 according to an embodiment of the invention. The electronic system 2 includes a chip 20 and gallium nitride transistors GT1, GT2. The chip 20 includes a drive circuit 21, an upper bridge circuit 12, a lower bridge circuit 13, voltage controlled current elements 24, 26, and bias elements 25, 27.

The drain, source and gate of the GaN transistor GT1 may be coupled to the pads P1, P2 and P3, respectively. The drain, source and gate of the GaN transistor GT2 may be coupled to the pads P3, P4 and P5, respectively. In some embodiments, the gan transistors GT1, GT2 may be gan transistors of a first on-type (e.g., n-type), and when the voltage difference between the gates and sources of the gan transistors GT1, GT2 is less than a threshold voltage, the gan transistors GT1, GT2 may be turned off and the connection between the drains and sources thereof may be disconnected. When the voltage difference between the gate and the source of the gan transistors GT1, GT2 is greater than the threshold voltage, the gan transistors GT1, GT2 may be turned on and the drain and the source thereof may be connected to each other.

In this embodiment, the driving circuit 21 includes a power supply circuit 210, a controller 211, and a level shift circuit 212. The power circuit 210 is used for providing a power voltage. The controller 211 is used for controlling the on and/or off of the power transistors T1, T2 by controlling the operation of the upper bridge circuit 12 and the lower bridge circuit 13. The level shifting circuit 212 is coupled to the controller 211 for shifting the voltage level provided by the controller 211 to generate driving signals DS1 and DS2 suitable for controlling the voltage-controlled current devices 24 and 26. Therefore, the upper bridge circuit 12 and the lower bridge circuit 13 can respectively receive the driving signals DS1 and DS2 to generate the control signals DS1 'and DS2', thereby driving the voltage-controlled current devices 24 and 26.

The power transistors T1, T2 are connected in series between the reference voltage HVDD and the reference voltage GND. The power transistor T1 may have, for example, a second on-state. A first terminal of the power transistor T1 (e.g., a drain of the power transistor T1) may be coupled to the pad P3, a second terminal of the power transistor T1 (e.g., a source of the power transistor T1) may receive the reference voltage HVDD, and a control terminal of the power transistor T1 (e.g., a gate of the power transistor T1) may be coupled to the upper bridge circuit 12. The power transistor T2 may have, for example, a first on-state. A first terminal of the power transistor T2 (e.g., a drain of the power transistor T2) may be coupled to the pad P3, a second terminal of the power transistor T2 (e.g., a source of the power transistor T2) may receive the reference voltage GND, and a control terminal of the power transistor T2 (e.g., a gate of the power transistor T2) may be coupled to the lower bridge circuit 13.

For the power transistor T1, the power transistor T1 includes a voltage-controlled current element 24, a bias element 25, and a gallium nitride transistor GT1. The voltage-controlled current device 24 is coupled to the upper bridge circuit 12 and the pads P1 and P2. The biasing element 25 is coupled to the pads P2 and P3.

The voltage-controlled current element 24 includes a resistor R1 and a transistor MN1. The resistor R1 and the transistor MN1 are connected in series between the pads P1 and P2. In this embodiment, the transistor MN1 may be, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) of a first on-type (for example, n-type), which is turned on when the gate of the transistor MN1 receives a relatively high voltage and turned off when the gate receives a relatively low voltage. The drain of the transistor MN1 receives the reference voltage HVDD through the resistor R1 and the pad P1, the source thereof is coupled to the pad P2, and the gate thereof is coupled to the upper bridge circuit 12. In some embodiments, the GaN transistor GT1 may have a higher operating voltage (e.g., about 600V), and the resistor R1 may step down the voltage received by the drain of the transistor MN1 to a voltage suitable for MOS operation (e.g., about 30V).

The bias element 25 includes a resistor R2 and a zener diode (ZD 1). The resistor R2 and the zener diode ZD1 are connected in series between the pads P2 and P3. One end of the resistor R2 is coupled to the pad P2 and the source of the transistor MN1, and the other end of the resistor R2 is coupled to the cathode of the zener diode ZD1. The anode of the zener diode ZD1 is coupled to the pad P3. In this way, when the bias current is provided to the bias device 25, the bias device 25 can provide a stable voltage difference through the resistor R2 and the zener diode ZD1.

For the power transistor T1 as a whole, when the control terminal of the power transistor T1 (i.e. the gate of the transistor MN 1) receives a relatively high voltage, the voltage-controlled current element 24 in the power transistor T1 provides a bias current to the bias element 25, so that the source voltage of the gan transistor GT1 increases. The rising source voltage causes the voltage difference between the gate and the source of the gan transistor GT1 to be smaller than the threshold voltage, thereby turning off the gan transistor GT1. Therefore, the control terminal of the power transistor T1 may be regarded as being turned off when receiving a relatively high level voltage. In contrast, when the control terminal of the power transistor T1 (i.e. the gate of the transistor MN 1) receives a relatively low voltage, the voltage-controlled current device 24 of the power transistor T1 does not provide the bias current to the bias device 25, so that the voltage difference between the gate and the source of the gan transistor GT1 is greater than the threshold voltage, thereby controlling the gan transistor GT1. The control terminal of the power transistor T1 is turned on when receiving a relatively low voltage.

Briefly, since the voltage-controlled current element 24 of the power transistor T1 is provided with the transistor MN1 having the first on-state, the power transistor T1 can be operated in the second on-state. That is, when the control terminal of the power transistor T1 is receiving a relatively high voltage level, the power transistor T1 may be turned off. The control terminal of the power transistor T1 may be turned on when receiving a relatively low voltage level.

For the power transistor T2, the power transistor T2 includes a voltage-controlled current element 26, a bias element 27, and a gallium nitride transistor GT2. The voltage-controlled current element 26 is coupled to the lower bridge circuit 13 and the pads P3 and P4. The biasing element is coupled to the pads P4 and P5.

The voltage-controlled current element 26 includes a resistor R3 and a transistor MP1. The resistor R3 and the transistor MP1 are connected in series between the pads P3 and P4. In this embodiment, the transistor MP1 may be, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) of a second on-type (e.g., p-type), which is turned on when the gate of the transistor MP1 receives a relatively low voltage and turned off when the gate receives a relatively high voltage. The source of the transistor MP1 is coupled to the pad P3 through the resistor R3, the drain is coupled to the pad P4, and the gate is coupled to the lower bridge circuit 13.

The biasing element 27 includes a resistor R4 and a zener diode (ZD 2). The resistor R4 and the zener diode ZD2 are connected in series between the pads P4 and P5. One end of the resistor R4 is coupled to the pad P4 and the drain of the transistor MP1, and the other end of the resistor R4 is coupled to the cathode of the zener diode ZD2. The anode of the zener diode ZD2 is coupled to the pad P5, and receives the reference voltage GND through the pad P5. In this way, when the bias current is provided to the bias device 27, the bias device 27 can provide a stable voltage difference through the resistor R4 and the zener diode ZD2.

For the power transistor T2 as a whole, when the control terminal of the power transistor T2 (i.e. the gate of the transistor MP 1) receives a relatively low voltage, the voltage-controlled current element 26 of the power transistor T2 provides a bias current to the bias element 27, so that the source voltage of the gan transistor GT2 increases. The rising source voltage causes the voltage difference between the gate and the source of the gan transistor GT2 to be smaller than the threshold voltage, thereby turning off the gan transistor GT2. Therefore, the control terminal of the power transistor T2 may be regarded as being turned off when receiving a relatively low level voltage. In contrast, when the control terminal of the power transistor T2 (i.e. the gate of the transistor MP 1) receives a relatively high voltage, the voltage-controlled current element 26 of the power transistor T2 does not provide the bias current to the bias element 27, so that the voltage difference between the gate and the source of the gan transistor GT2 is greater than the threshold voltage, thereby controlling the gan transistor GT2. Therefore, the control terminal of the power transistor T2 is turned on when receiving a relatively high voltage.

Briefly, since the voltage-controlled current element 26 of the power transistor T2 is provided with the transistor MP1 having the second on-state, the power transistor T2 can be operated in the first on-state. That is, when the control terminal of the power transistor T2 is receiving a relatively low voltage level, the power transistor T2 may be turned off. The control terminal of the power transistor T2 may be turned on when receiving a relatively high voltage level.

Therefore, in the electronic system 2, the voltage-controlled current elements 24, 26 and the bias elements 25, 27 are coupled with the gan transistors GT1, GT2, so that the voltage-controlled current element 24, the bias element 25 and the gan transistor GT1 are formed into the power transistor T1 having the second on-state, and the voltage-controlled current element 26, the bias element 27 and the gan transistor GT2 are formed into the power transistor T2 having the first on-state. The on and/or off of the gan transistors GT1, GT2 are controlled by the voltage-controlled current devices 24, 26 and the bias devices 25, 27 on the chip 20, so as to preferably avoid leakage current of the gan transistors GT1, GT2, thereby improving power consumption of the electronic system 2.

Fig. 3 is a schematic diagram of an electronic system 3 according to an embodiment of the invention. The chip 30 includes a driving circuit 21, an upper bridge circuit 12, a lower bridge circuit 13, voltage controlled current elements 34, 26, bias elements 25, 27, and a bootstrap (bootstrap) circuit 38. The electronic system 3 shown in fig. 3 is similar to the electronic system 2 shown in fig. 2, and therefore like elements are denoted by like reference numerals. The electronic system 3 comprises a chip 30 and gallium nitride transistors GT1, GT2. The electronic system 3 differs from the electronic system 2 in that in the chip 20 of the electronic system 2 the voltage controlled current element 24 is replaced by a voltage controlled current element 34 in the chip 30 of the electronic system 3. The chip 30 of the electronic system 3 further includes a bootstrap circuit 38 and a capacitor C2. Therefore, the operations of the driving circuit 21, the upper bridge circuit 12, the lower bridge circuit 13, the voltage-controlled current device 26, the bias devices 25, 27 are referred to the relevant paragraphs of the above paragraphs, and are not repeated here.

The voltage-controlled current element 34 includes a resistor R1 and a transistor MP2. The resistor R1 and the transistor MP2 are connected in series between the pads P1 and P2. In this embodiment, the transistor MP2 may be, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) of a second on-type (e.g., p-type), which is turned on when the gate of the transistor MP2 receives a relatively low voltage and turned off when the gate receives a relatively high voltage. The source of the transistor MP2 receives the reference voltage HVDD through the resistor R1 and the pad P1, the drain thereof is coupled to the pad P2, and the gate thereof is coupled to the upper bridge circuit 12. In some embodiments, the GaN transistor GT1 may have a higher operating voltage (e.g., about 600V), and the resistor R1 may step down the voltage received by the drain of the transistor MP2 to a voltage suitable for MOS operation (e.g., about 30V).

In some embodiments, the voltage-controlled current element 34, the bias element 25 and the gan transistor GT1 can be collectively regarded as a power transistor T3 for operation, and the power transistor T3 can have, for example, a first on-state. The first terminal of the power transistor T3 (e.g., the drain of the power transistor T3) may receive the reference voltage HVDD, the second terminal of the power transistor T3 (e.g., the source of the power transistor T3) may be coupled to the pad P3, and the control terminal of the power transistor T3 (e.g., the gate of the power transistor T3) may receive the control of the upper bridge circuit 12. The power transistor T3 may control the conduction between the first terminal and the second terminal according to the voltage received by the control terminal.

For the power transistor T3 as a whole, when the control terminal of the power transistor T3 (i.e. the gate of the transistor MP 2) receives a relatively low voltage, the voltage-controlled current element 34 of the power transistor T3 provides a bias current to the bias element 25, so that the source voltage of the gan transistor GT1 increases. The rising source voltage causes the voltage difference between the gate and the source of the gan transistor GT1 to be smaller than the threshold voltage, thereby turning off the gan transistor GT1. Therefore, the control terminal of the power transistor T3 may be regarded as being turned off when receiving a relatively low level voltage. In contrast, when the control terminal of the power transistor T3 (i.e. the gate of the transistor MP 2) receives a relatively high voltage, the voltage-controlled current element 34 of the power transistor T3 does not provide the bias current to the bias element 25, so that the voltage difference between the gate and the source of the gan transistor GT1 can be greater than the threshold voltage, thereby controlling the gan transistor GT1. The control terminal of the power transistor T3 is turned on when receiving a relatively high voltage.

Briefly, since the voltage-controlled current element 34 of the power transistor T3 is provided with the transistor MP2 having the second on-state, the power transistor T3 can be operated in the first on-state. That is, when the control terminal of the power transistor T3 is receiving a relatively low voltage level, the power transistor T3 may be turned off. The control terminal of the power transistor T3 may be turned on when receiving a relatively high voltage level.

The bootstrap circuit 38 is further disposed in the chip 30 corresponding to the power transistor T3 of the first on-state. The bootstrap circuit 38 includes a diode D1 and a capacitor C1 connected in series between the driving circuit 21 and the pad P3. The anode of the diode D1 is coupled to the power circuit 210 of the driving circuit 21, the cathode of the diode D1 is coupled to one end of the capacitor C1, and the other end of the capacitor C1 is coupled to the pad P3.

For the operation of the bootstrap circuit 38, when the power transistor T3 is turned off and the power transistor T2 is turned on, the voltage on the pad P3 is correspondingly pulled down. The upper plate of the capacitor C1 in the bootstrap circuit 38 is charged by the power circuit 210. When the power transistor T3 is turned on and the power transistor T2 is turned off, the voltage on the pad P3 is pulled up, and the upper plate voltage of the capacitor C1 is correspondingly raised. Thus, the bootstrap circuit 38 may generate a boosted supply voltage to the upper bridge circuit 12 through operation of the power transistors T3, T2.

Further, since the power transistor T3 is a power transistor having the first on-state, the voltage difference between the control terminal and the first terminal of the power transistor T3 can be controlled by the control signal DS1' generated by the raised power supply voltage to control the power transistor T3 to be turned off.

In summary, the electronic system and the chip of the invention can preferably control the on and/or off of the gallium nitride transistor without changing the structure of the gallium nitride transistor by an additional process and retaining the advantages of high current and fast switching of the gallium nitride transistor, thereby effectively avoiding the leakage current of the gallium nitride transistor and further improving the overall power consumption of the electronic system.

It should be noted that the above embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present invention.

Claims (14)

1. A chip, characterized in that it is used to control a first gallium nitride transistor and a second gallium nitride transistor, wherein the source of the first gallium nitride transistor is coupled to the drain of the second gallium nitride transistor, the chip comprising: The first pad, second pad, third pad, fourth pad, and fifth pad are respectively used to couple to the drain, source, and gate of the first gallium nitride transistor, and the third pad, fourth pad, and fifth pad are respectively used to couple to the drain, source, and gate of the second gallium nitride transistor. The first voltage-controlled current element has a first terminal and a second terminal, which are respectively coupled to the first pad and the second pad; The second voltage-controlled current element has a first terminal and a second terminal, which are respectively coupled to the third pad and the fourth pad; A first bias element is coupled between the second pad and the third pad; and The second bias element is coupled between the fourth and fifth pads. The first bias element adjusts the bias voltage of the second pad according to the control of the first voltage-controlled current element, and the second bias element adjusts the bias voltage of the fourth pad according to the control of the second voltage-controlled current element. 2. The chip according to claim 1, further comprising: The upper bridge circuit is coupled to the control terminal of the first voltage-controlled current element; and The lower bridge circuit is coupled to the control terminal of the second voltage-controlled current element. The first voltage-controlled current element provides a first bias current to the first bias element according to the control of the upper bridge circuit, so as to control the first gallium nitride transistor to be turned on or off. The second voltage-controlled current element provides a second bias current to the second bias element according to the control of the lower bridge circuit, so as to control the second gallium nitride transistor to be turned on or off. 3. The chip according to claim 1, wherein the first biasing element comprises: A first resistor having a first end coupled to the second pad; and The first diode has a cathode coupled to the second end of the first resistor and an anode coupled to the third pad. The second bias element includes: The second resistor has a first end coupled to the fourth pad; and The second diode has a cathode coupled to the second end of the second resistor and an anode coupled to the fifth pad. 4. The chip according to claim 2, characterized in that it comprises: A power supply circuit is coupled to the upper bridge circuit and the lower bridge circuit, and the power supply circuit is used to provide a first power supply voltage; A controller, coupled to the upper bridge circuit and the lower bridge circuit, is configured to generate a first drive signal and a second drive signal to control the operation of the upper bridge circuit and the lower bridge circuit; and A level shifting circuit is coupled to the controller, the upper bridge circuit, and the lower bridge circuit. The level shifting circuit is used to adjust the voltage levels of the first drive signal and the second drive signal. 5. The chip according to claim 4, wherein the first voltage-controlled current element comprises an n-type metal-oxide-semiconductor field-effect transistor, and when the first voltage-controlled current element receives a high logic level voltage, the first voltage-controlled current element provides the first bias current to the first bias element to control the first gallium nitride transistor to be off. The second voltage-controlled current element includes a p-type metal-oxide-semiconductor field-effect transistor. When the second voltage-controlled current element receives a low logic level voltage, the second voltage-controlled current element provides the second bias current to the second bias element to control the second gallium nitride transistor to be turned off. 6. The chip according to claim 4, wherein the first voltage-controlled current element includes a first p-type metal-oxide-semiconductor field-effect transistor, and when the first voltage-controlled current element receives a low logic level voltage, the first voltage-controlled current element provides the first bias current to the first bias element to control the first gallium nitride transistor to be off. The second voltage-controlled current element includes a second p-type metal-oxide-semiconductor field-effect transistor. When the second voltage-controlled current element receives the low logic level voltage, the second voltage-controlled current element provides the second bias current to the second bias element to control the second gallium nitride transistor to be turned off. 7. The chip according to claim 6, further comprising: A bootstrap circuit, coupled between the power supply circuit and the third pad, boosts the first power supply voltage to generate the boosted power supply voltage. The bootstrap circuit includes: A diode having an anode and a cathode, the anode of the diode being coupled to the power supply circuit; and A capacitor is coupled between the cathode of the diode and the third bonding pad. The bootstrap circuit generates a boosted first power supply voltage at the cathode of the diode and provides the boosted power supply voltage to the upper bridge circuit. 8. An electronic system, characterized in that it comprises: The first gallium nitride transistor has a drain, a source, and a gate; A second gallium nitride transistor has a drain, a source, and a gate, wherein the source of the first gallium nitride transistor is coupled to the drain of the second gallium nitride transistor; and A chip for controlling the operation of the first gallium nitride transistor and the second gallium nitride transistor, the chip comprising: A first pad, a second pad, a third pad, a fourth pad, and a fifth pad are respectively coupled to the drain, source, and gate of the first gallium nitride transistor, and the third pad, the fourth pad, and the fifth pad are respectively coupled to the drain, source, and gate of the second gallium nitride transistor. The first voltage-controlled current element has a first terminal and a second terminal, which are respectively coupled to the first pad and the second pad; The second voltage-controlled current element has a first terminal and a second terminal, which are respectively coupled to the third pad and the fourth pad; A first bias element is coupled between the second pad and the third pad; and The second bias element is coupled between the fourth and fifth pads. The first bias element adjusts the bias voltage of the second pad according to the control of the first voltage-controlled current element, and the second bias element adjusts the bias voltage of the fourth pad according to the control of the second voltage-controlled current element. 9. The electronic system according to claim 8, wherein the chip further comprises: The upper bridge circuit is coupled to the control terminal of the first voltage-controlled current element; and The lower bridge circuit is coupled to the control terminal of the second voltage-controlled current element. The first voltage-controlled current element provides a first bias current to the first bias element according to the control of the upper bridge circuit, so as to control the first gallium nitride transistor to be turned on or off. The second voltage-controlled current element provides a second bias current to the second bias element according to the control of the lower bridge circuit, so as to control the second gallium nitride transistor to be turned on or off. 10. The electronic system according to claim 8, wherein the first biasing element comprises: A first resistor having a first end coupled to the second pad; and The first diode has a cathode coupled to the second end of the first resistor and an anode coupled to the third pad. The second bias element includes: The second resistor has a first end coupled to the fourth pad; and The second diode has a cathode coupled to the second end of the second resistor and an anode coupled to the fifth pad. 11. The electronic system according to claim 9, wherein the chip comprises: A power supply circuit is coupled to the upper bridge circuit and the lower bridge circuit, and the power supply circuit is used to provide power supply voltage; A controller, coupled to the upper bridge circuit and the lower bridge circuit, is configured to generate a first drive signal and a second drive signal to control the operation of the upper bridge circuit and the lower bridge circuit; and A level shifting circuit is coupled to the controller, the upper bridge circuit, and the lower bridge circuit. The level shifting circuit is used to adjust the voltage levels of the first drive signal and the second drive signal. 12. The electronic system according to claim 11, wherein the first voltage-controlled current element comprises an n-type metal-oxide-semiconductor field-effect transistor, and when the first voltage-controlled current element receives a high logic level voltage, the first voltage-controlled current element provides the first bias current to the first bias element to control the first gallium nitride transistor to be off. The second voltage-controlled current element includes a p-type metal-oxide-semiconductor field-effect transistor. When the second voltage-controlled current element receives a low logic level voltage, the second voltage-controlled current element provides the second bias current to the second bias element to control the second gallium nitride transistor to be turned off. 13. The electronic system according to claim 11, wherein the first voltage-controlled current element comprises a first p-type metal-oxide-semiconductor field-effect transistor, and when the first voltage-controlled current element receives a low logic level voltage, the first voltage-controlled current element provides the first bias current to the first bias element to control the first gallium nitride transistor to be off. The second voltage-controlled current element includes a second p-type metal-oxide-semiconductor field-effect transistor. When the second voltage-controlled current element receives the low logic level voltage, the second voltage-controlled current element provides the second bias current to the second bias element to control the second gallium nitride transistor to be turned off. 14. The electronic system according to claim 13, wherein the chip further comprises: A bootstrap circuit, coupled between the power supply circuit and the third pad, boosts the power supply voltage to generate the boosted power supply voltage. The bootstrap circuit includes: A diode having an anode and a cathode, the anode of the diode being coupled to the power supply circuit; and A capacitor is coupled between the cathode of the diode and the third bonding pad. The bootstrap circuit generates a boosted first power supply voltage at the cathode of the diode and provides the boosted first power supply voltage to the upper bridge circuit.