CN116053123A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor device and a preparation method thereof, wherein a resistor groove is formed by etching and removing part of the thickness of a gate electrode layer in a region where a sheet resistor is required to be manufactured, and a resistor buffer layer, a resistor layer and an etching barrier layer are filled in the resistor groove, and a chemical mechanical polishing process corresponding to the etching barrier layer is matched, so that a sheet resistor circuit component can be manufactured without additionally increasing the thickness in the region of the sheet resistor, the depth of etching and filling required for a subsequent contact hole can be effectively reduced, the depth-to-width ratio of the contact hole is further reduced, and the manufacturing process window of the contact hole is increased. Meanwhile, the flatness of the device can be effectively improved, and the overall thickness of the device is reduced.

Description

Semiconductor device and manufacturing method thereof

technical field

The invention belongs to the field of design and manufacture of semiconductor integrated circuits, in particular to a semiconductor device and a preparation method thereof.

Background technique

In the logic chip circuit design, the required total circuit resistance (Resistance) requirement is conventionally used to reserve a part of the gate area, and the resistance value is adjusted by ion implantation (Ion implantation). However, since the surface of polysilicon is continuously exposed in the front end of line (FEOL) process, the subsequent junction resistance value varies with the process differences of different products.

In addition, in the advanced metal gate process, since the metal resistance is too small, the required resistance value cannot be obtained through this method. Conventionally, additional titanium nitride is deposited, and the resistance value area is defined by the photolithography process, so as to achieve the original Design results for polysilicon gates. In the process flow, it is necessary to deposit a certain thickness of silicon oxide dielectric layer as a buffer layer of titanium nitride; at the same time, silicon nitride will be deposited on top of titanium nitride as a stop layer (Contact Etch Stop Layer; CESL) for the subsequent contact hole etching process. Using titanium nitride as the source of circuit resistance is more stable and reliable than ion implantation to change the polysilicon gate resistance, but the process of additionally depositing a larger thickness of silicon oxide layer will cause the etching required in the subsequent contact hole process. The aspect ratio of the contact hole is too high, resulting in a greatly compressed process window for dry etching and depositing tungsten metal plugs in the contact hole process. At the same time, the silicon oxide layer and the resistance layer are prepared above the gate, which will affect the flatness of the device and increase the thickness of the device.

It should be noted that the above introduction to the technical background is only for the convenience of a clear and complete description of the technical solution of the present application, and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are known to those skilled in the art just because these solutions are described in the background technology section of this application.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which are used to solve the problem in the prior art that the process window of the contact hole will be compressed by adding a sheet resistor.

In order to achieve the above object and other related objects, the present invention provides a method for manufacturing a semiconductor device. The method includes: 1) providing a semiconductor structure, the semiconductor structure including a substrate and a gate structure located on the substrate , the gate structure includes a stacked gate dielectric layer and a gate electrode layer, and a spacer structure is formed around the gate structure; 2) a sheet resistance area and a non-sheet resistance area are defined by photolithography, and the sheet is removed by etching Partial thickness of the gate electrode layer in the resistance area forms a resistance groove; 3) deposits a resistance buffer layer in the resistance groove of the non-sheet resistance area and the sheet resistance area; 4) deposits a resistance layer on the resistance buffer layer; 5) Depositing an etch barrier layer on the resistance layer, wherein the resistance buffer layer, resistance layer and etch barrier layer are filled in the resistance groove; 6) Removing the non-sheet by chemical mechanical polishing The redundant etching barrier layer in the resistance area and the sheet resistance area, so that the etching barrier layer retained in the resistance groove of the sheet resistance area is flush with the top surface of the resistance layer in the non-sheet resistance area; 7 ) removing the resistive layer in the non-sheet resistive area, and retaining the resistive layer in the resistive slot in the sheet resistive area based on the etching barrier layer, so as to form a sheet resistive in the resistive slot.

Optionally, step 1) further includes the step of: depositing a first etch stop layer on the substrate, and the first etch stop layer covers the surface of the substrate, the sidewall structure of the gate structure and the The top surface of the gate structure, wherein the etch stop layer is used as a second etch stop layer.

Optionally, the gate structure includes a first type of gate and a second type of gate, the type of gate is located in the sheet resistance area, the second type of gate is located in the non-sheet resistance area, and the width of the first type of gate is larger than The width of the second type of gate, the sheet resistor is fabricated on the first type of gate.

Optionally, the gate dielectric layer of the first type gate includes one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer of the first type gate includes one of a polysilicon gate and a metal gate.

Optionally, the gate dielectric layer of the second type gate includes one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer of the second type gate includes one of a polysilicon gate and a metal gate.

Optionally, step 1) further includes the step of: depositing a dielectric layer on the substrate, the deposition thickness of the dielectric layer is greater than the height of the gate structure, and removing the material above the top surface of the gate structure by a chemical mechanical polishing process. The dielectric layer, so that the top surface of the dielectric layer is flush with the top surface of the gate structure.

Optionally, the material of the resistance buffer layer includes silicon dioxide, the material of the resistance layer includes titanium nitride or tantalum nitride, and the material of the etching stopper layer includes silicon nitride, silicon oxynitride and nitride Silicon and silicon oxynitride combination layer.

Optionally, step 7) removes the resistance layer on the substrate through a wet etching process or a dry etching process.

The present invention also provides a semiconductor device, including: a semiconductor structure, the semiconductor structure includes a substrate and a gate structure on the substrate, the gate structure includes a stacked gate dielectric layer and a gate electrode layer, the gate A sidewall structure is formed around the structure, and a part of the thickness of the gate electrode layer is removed to form a resistance groove; a resistance buffer layer is arranged in the resistance groove; a resistance layer is arranged on the resistance buffer layer; an etching stopper layer , arranged on the resistance layer, the resistance buffer layer, the resistance layer and the etching stopper layer are filled in the resistance groove to form a sheet resistance.

Optionally, the substrate is further provided with a first etch stop layer, the first etch stop layer covers the surface of the substrate and the sidewall structure of the gate structure, wherein the etch stop layer as a second etch stop layer.

Optionally, the gate structure includes a first type of gate and a second type of gate, the type of gate is located in the sheet resistance area, the second type of gate is located in the non-sheet resistance area, and the width of the first type of gate is larger than The width of the second type of gate, the sheet resistor is fabricated on the first type of gate.

Optionally, the gate dielectric layer of the first type of gate includes one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer of the first type of gate includes one of a polysilicon gate and a metal gate, so The gate dielectric layer of the second type of gate includes one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer of the second type of gate includes one of a polysilicon gate and a metal gate.

Optionally, the material of the resistance buffer layer includes silicon dioxide, the material of the resistance layer includes titanium nitride or tantalum nitride, and the material of the etching stopper layer includes silicon nitride, silicon oxynitride and nitride Silicon and silicon oxynitride combination layer.

As mentioned above, the semiconductor device and its preparation method of the present invention have the following beneficial effects:

In the present invention, in the gate manufacturing process, in the area where the sheet resistance needs to be manufactured, the partial thickness of the gate electrode layer is etched to form a resistance groove, and a resistance buffer layer, a resistance layer and an etching barrier layer are filled in the resistance groove. , with the chemical mechanical polishing process corresponding to the etching barrier layer, the chip resistance circuit component can be produced without adding additional thickness in the chip resistance area, which can effectively reduce the depth of etching and filling required for subsequent contact holes , thereby reducing the aspect ratio of the contact hole and increasing the manufacturing process window of the contact hole. At the same time, the application can effectively improve the flatness of the device and reduce the overall thickness of the device.

Description of drawings

The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and explain the principle of the present application together with the text description. Apparently, the drawings in the following description are only some embodiments of the present application.

FIG. 1 to FIG. 7 show the structural schematic diagrams presented in each step of the manufacturing method of the semiconductor device according to the embodiment 1 of the present invention.

8 to 14 are schematic structural diagrams presented in each step of the manufacturing method of the semiconductor device according to Embodiment 2 of the present invention.

FIG. 15 is a schematic structural diagram of a semiconductor device according to Embodiment 3 of the present invention.

Component designation description

10 Substrate

11 The first type of grid

111 The gate dielectric layer of the first type gate

112 The gate electrode layer of the first type gate

12 second type grid

121 The gate dielectric layer of the second type gate

122 The gate electrode layer of the second type gate

13 side wall structure

14 The first etch stop layer

15 medium layer

16 Resistive buffer layer

17 Resistive layer

18 etch stop layer

19 Resistor Slot

191 photoresist pattern

201, 301 metal grid

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

It should be emphasized that the term "comprising/comprising" when used herein refers to the presence of a feature, integer, step or component, but does not exclude the presence or addition of one or more other features, integers, steps or components.

Features described and/or illustrated with respect to one embodiment can be used in the same or similar manner in one or more other embodiments, in combination with, or instead of features in other embodiments .

For example, when describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

For the convenience of description, spatial relation terms such as "below", "below", "below", "below", "above", "on" etc. may be used herein to describe an element or element shown in the drawings. The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, structures described as having a first feature "on top of" a second feature may include embodiments where the first and second features are formed in direct contact, as well as additional features formed between the first and second features. Embodiments between the second feature such that the first and second features may not be in direct contact.

It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, so that only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

Example 1

As shown in Figures 1 to 7, this embodiment clearly provides a method for preparing a semiconductor device, the method comprising:

As shown in FIGS. 1-2 , step 1) is first performed to provide a semiconductor structure, the semiconductor structure includes a substrate 10 and a gate structure located on the substrate 10, and the gate structure includes stacked gate dielectric layers and the gate electrode layer, and a spacer structure 13 is formed around the gate structure.

In some embodiments, the substrate 10 may be, for example, a silicon substrate 10 . The substrate 10 may include various layers including conductive or insulating layers formed on the semiconductor substrate 10 . Additionally, substrate 10 may include various doping configurations depending on design requirements. The substrate 10 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. The substrate 10 may include compound semiconductors and/or alloy semiconductors, such as gallium nitride, gallium arsenide, and the like. Additionally, substrate 10 may optionally include an epitaxial layer (epi), may be strained to enhance performance, may include a silicon-on-insulator (SOI) structure, and/or have other suitable enhancement features.

In some embodiments, various device elements may be formed in and/or on substrate 10 . Examples of various device elements that may be formed in and/or on semiconductor substrate 10 include metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors, high voltage transistors, High frequency transistors, P-channel and/or N-channel field effect transistors, diodes, other suitable components or combinations thereof. The various device elements may be formed by various processes, such as deposition, etching, implantation, photolithography, annealing, planarization, one or more other suitable processes, or combinations thereof. Additionally, in some embodiments, isolation features may be formed within substrate 10 to define and isolate various device elements formed in and/or on substrate 10 . The isolation feature includes, for example, a Shallow Trench Isolation (STI) structure, or a Local Oxidation of Silicon (LOCOS) structure, and the like. The gate structure is a gate structure corresponding to one or more of the above device elements.

The material of the sidewall structure 13 shown can be, for example, silicon dioxide, silicon nitride, silicon oxynitride, or a stacked structure of the above materials.

In one embodiment, step 1) further includes the step of: depositing a first etch stop layer 14 on the substrate 10, the first etch stop layer 14 covers the surface of the substrate 10, the gate structure The side wall structure 13 and the top surface of the gate structure, the first etch stop layer 14 may expose the top surface of the gate structure, and may also completely cover the top surface of the gate structure, wherein the subsequently formed The etch stop layer 18 is used as a second etch stop layer.

As shown in Figures 1 to 2, in this embodiment, the gate structure includes a first type of gate 11 and a second type of gate 12, the type of gate is located in the sheet resistance area, and the second type of gate 12 is located in the In the non-sheet resistance region, the width of the first type gate 11 is greater than the width of the second type gate 12 , and the sheet resistance is fabricated on the first type gate 11 .

As an example, the gate dielectric layer 111 of the first type of gate may include one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer 112 of the first type of gate may include one of a polysilicon gate and a metal gate . The gate dielectric layer 121 of the second type of gate includes one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer 122 of the second type of gate includes one of a polysilicon gate and a metal gate. In this embodiment, the gate dielectric layer 111 of the first type gate is a silicon oxide layer, and the gate electrode layer 112 of the first type gate is a polysilicon gate. The gate dielectric layer 121 of the second type gate is a silicon oxide layer, and the gate electrode layer 122 of the second type gate is a polysilicon gate.

In one embodiment, step 1) further includes the step of: depositing a dielectric layer 15 on the substrate 10, the deposition thickness of the dielectric layer 15 is greater than the height of the gate structure, and removing the dielectric layer 15 by a chemical mechanical polishing process. The dielectric layer 15 above the top surface of the gate structure, so that the top surface of the dielectric layer 15 is flush with the top surface of the gate structure. The material of the dielectric layer 25 can be, for example, orthoethyl silicate (TEOS) oxide, carbon-containing silicon oxide, silicon oxide, porous dielectric material, undoped silicate glass or doped silicon oxide , for example, borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), etc. Deposition (PECVD), high-density plasma chemical vapor deposition (HDP), atomic layer deposition (ALD) and other processes.

As shown in Figures 3 to 4, step 2) is then performed. First, the sheet resistance area and the non-sheet resistance area are defined by photolithography, and part of the thickness of the gate electrode layer in the sheet resistance area is removed by etching to form Resistor slot 19.

In one embodiment, the photoresist material can be spin-coated on the substrate 10 first, and then the photoresist pattern 191 is formed by an exposure process and a development process, as an etching mask, and then by dry etching (such as reactive plasma) Etching etc.) removes part of the thickness of the gate electrode layer to form a resistance groove 19. In this embodiment, the resistance groove 19 completely covers the gate electrode layer in the lateral width of the gate structure. The depth of the resistance groove 19 can be set according to the thickness of the resistance buffer layer 16, the resistance layer 17 and the etching barrier layer 18 prepared subsequently, and the sheet resistance resistance value is related to the thickness of the resistance buffer layer 16 and the resistance layer 17. relevant. For example, the thickness of the resistance groove 19 can be designed so that after the resistance buffer layer 16, the resistance layer 17 and the etch barrier layer 18 of sufficient thickness are subsequently filled, the top surface of the etch barrier layer 18 can be in contact with the substrate 10. The top surface of the resistive layer 17 is flush with each other.

As shown in FIG. 5 , step 3) is then performed to deposit a resistance buffer layer 16 in the resistance groove 19 of the non-sheet resistance area and the sheet resistance area.

In one embodiment, the material of the resistance buffer layer 16 is silicon dioxide, which can be obtained by plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDP), atomic layer deposition (ALD), etc. process, wherein the resistance buffer layer 16 located in the resistance groove 19 covers the bottom and sidewalls of the resistance groove 19 .

As shown in FIG. 5 , step 4) is then performed to deposit a resistive layer 17 on the resistive buffer layer 16 .

In one embodiment, the resistance layer 17 can be a titanium nitride or tantalum nitride layer with a certain resistance value, which can be formed by processes such as CVD, PVD (such as sputtering process, evaporation process or MOCVD process) .

As shown in Figure 5, then proceed to step 5), depositing an etch barrier layer 18 on the resistance layer 17, wherein the resistance buffer layer 16, the resistance layer 17 and the etch barrier layer 18 are filled in the resistance layer 17. In slot 19.

In one embodiment, the material of the etching barrier layer 18 can be, for example, silicon nitride, silicon oxynitride, and a combination layer of silicon nitride and silicon oxynitride, which can be obtained by processes such as plasma enhanced chemical vapor deposition (PECVD). form. The etch stop layer 18 fills up the resistance groove 19 .

As shown in Figure 6, then carry out 6), remove the redundant etch barrier layer 18 of described non-sheet resistance area and sheet resistance area by chemical mechanical polishing process, make the described resistance groove 19 that remains in the described sheet resistance area The etch stop layer 18 is flush with the top surface of the resistive layer 17 in the non-sheet resistive region.

The etching barrier layer 18 retained in the resistance groove 19 can be used as a protective mask for the resistance layer 17 and the resistance buffer layer 16 below and on the sidewalls, so as to protect the subsequent removal of the resistance layer on the surface of the substrate 10. 17, so that the resistance layer 17 in the resistance groove 19 can be effectively retained and not affected by the etching or corrosion process, so as to ensure that the resistance layer 17 has a stable resistance value and a high film quality.

As shown in Figure 7, 7) remove the resistance layer 17 of the non-sheet resistance region, and retain the resistance layer 17 in the resistance groove 19 of the sheet resistance region based on the etching barrier layer 18, so as to be in the A sheet resistor is formed in the resistor slot 19 .

In one embodiment, step 7) may remove the resistance layer 17 on the substrate 10 through a wet etching process or a dry etching process.

In the subsequent process, it also includes depositing an insulating layer on the above-mentioned structure, and etching a contact hole in the insulating layer, and the contact hole includes a contact hole for gate extraction, and a contact for source and drain extraction. Holes, etc., and then fill the above-mentioned contact holes with metal conductors to realize the extraction of sources, drains, gates, etc. The present invention forms the resistance groove 19 by etching and removing part of the thickness of the gate electrode layer in the gate manufacturing process, and fills the resistance buffer layer 16, resistance layer 17 and The etch barrier layer 18, in conjunction with the chemical mechanical polishing process corresponding to the etch barrier layer 18, can realize the production of chip resistor circuit components without adding additional thickness in the chip resistor area, which can effectively reduce the etching required for subsequent contact holes and the required filling depth, thereby reducing the aspect ratio of the contact hole and increasing the manufacturing process window of the contact hole. At the same time, the application can effectively improve the flatness of the device and reduce the overall thickness of the device.

As shown in FIG. 7 , this embodiment also provides a semiconductor device. The semiconductor device includes: a semiconductor structure, the semiconductor structure includes a substrate 10 and a gate structure on the substrate 10, and the gate structure includes Stacked gate dielectric layer and gate electrode layer, sidewall structures 13 are formed around the gate structure, part of the thickness of the gate electrode layer is removed to form a resistance groove 19; resistance buffer layer 16 is arranged in the resistance groove 19 The resistance layer 17 is arranged on the resistance buffer layer 16; the etch stop layer 18 is arranged on the resistance layer 17, and the resistance buffer layer 16, the resistance layer 17 and the etch stop layer 18 are filled in the resistor slot 19 to form a sheet resistor.

In one embodiment, the substrate 10 further has a first etch stop layer 14, the first etch stop layer 14 covers the surface of the substrate 10 and the sidewall structure 13 of the gate structure, wherein , the etch stop layer 18 serves as a second etch stop layer.

In one embodiment, the gate structure includes a first type of gate 11 and a second type of gate 12, the type of gate is located in the sheet resistance area, the second type of gate 12 is located in the non-sheet resistance area, and the first type of gate is located in the non-sheet resistance area. The width of the grid 11 is greater than that of the second grid 12 , and the sheet resistor is fabricated on the first grid 11 . As an example, the gate dielectric layer 111 of the first type of gate may include one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer 112 of the first type of gate may include one of a polysilicon gate and a metal gate . The gate dielectric layer 121 of the second type of gate includes one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer 122 of the second type of gate includes one of a polysilicon gate and a metal gate. In this embodiment, the gate dielectric layer 111 of the first type gate is a silicon oxide layer, and the gate electrode layer 112 of the first type gate is a polysilicon gate. The gate dielectric layer 121 of the second type gate is a silicon oxide layer, and the gate electrode layer 122 of the second type gate is a polysilicon gate.

In one embodiment, the material of the resistance buffer layer 16 includes silicon dioxide, the material of the resistance layer 17 includes titanium nitride or tantalum nitride, and the material of the etching stopper layer 18 includes silicon nitride, nitrogen Combination layers of silicon oxide and silicon nitride and silicon oxynitride.

Example 2

As shown in Figures 8 to 14, this embodiment provides a semiconductor device preparation method, the basic steps of the preparation method can refer to the embodiment 1, wherein, the difference from the embodiment 1 is that the second The gate dielectric layer of the gate type is a high-k dielectric layer (such as a hafnium-based high-k dielectric material such as hafnium oxide), and the gate electrode layer of the second type gate is a metal gate 201 . The gate dielectric layer of the first type gate is a silicon oxide layer, and the gate electrode layer of the first type gate is a polysilicon gate. The material of the metal gate 201 may be, for example, one or more of TiAl, Al, Ta, Ti, W, Cu, HfCN, HfC, Pt, Ru, Mo or Ir.

Specifically, as shown in FIG. 8 to FIG. 9, the polysilicon gate of the second type of gate 12 in Embodiment 1 can be removed through processes such as etching or etching, and then filled with a metal process (such as sputtering, evaporation, etc.) , electroplating) and the like to fill the metal gate 201 in the cavity where the polysilicon gate is removed.

Example 3

As shown in Figure 15, this embodiment provides a semiconductor device preparation method, the basic steps of the preparation method can refer to embodiment 2, wherein, the difference from embodiment 2 is that the second type of gate The gate dielectric layer is a high-k dielectric layer (such as hafnium oxide, etc.), and the gate electrode layer of the second type of gate is a metal gate 201 . The gate dielectric layer of the first type gate is a high-k dielectric layer (such as hafnium oxide, etc.), and the gate electrode layer of the first type gate is a metal gate 301 . Specifically, the polysilicon gate of the first type of gate in Embodiment 2 can be removed at the same time by processes such as etching or etching, and then the polysilicon gate can be removed by metal filling processes (such as sputtering, evaporation, electroplating) and the like. The metal gate 301 is filled in the cavity.

As mentioned above, the semiconductor device and its preparation method of the present invention have the following beneficial effects:

The present invention forms the resistance groove 19 by etching and removing part of the thickness of the gate electrode layer in the gate manufacturing process, and fills the resistance buffer layer 16, resistance layer 17 and The etch barrier layer 18, in conjunction with the chemical mechanical polishing process corresponding to the etch barrier layer 18, can realize the production of chip resistor circuit components without adding additional thickness in the chip resistor area, which can effectively reduce the etching required for subsequent contact holes and the required filling depth, thereby reducing the aspect ratio of the contact hole and increasing the manufacturing process window of the contact hole. At the same time, the application can effectively improve the flatness of the device and reduce the overall thickness of the device.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (13)

1. A method of manufacturing a semiconductor device, the method comprising:

1) Providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a gate structure positioned on the substrate, the gate structure comprises a gate dielectric layer and a gate electrode layer which are stacked, and a side wall structure is formed on the periphery of the gate structure;

2) Defining a sheet resistance region and a non-sheet resistance region by photoetching, and etching to remove part of the thickness of the gate electrode layer in the sheet resistance region to form a resistance groove;

3) Depositing a resistance buffer layer in the resistance grooves of the non-sheet resistance area and the sheet resistance area;

4) Depositing a resistor layer on the resistor buffer layer;

5) Depositing an etching barrier layer on the resistor layer, wherein the resistor buffer layer, the resistor layer and the etching barrier layer are filled in the resistor groove;

6) Removing the non-sheet resistance region and the redundant etching barrier layer of the sheet resistance region through a chemical mechanical polishing process, so that the etching barrier layer reserved in the resistance groove of the sheet resistance region is flush with the top surface of the resistance layer of the non-sheet resistance region;

7) And removing the resistance layer of the non-sheet resistance region, and retaining the resistance layer in the resistance groove of the sheet resistance region based on the etching barrier layer so as to form a sheet resistance in the resistance groove.

2. The method of manufacturing a semiconductor device according to claim 1, characterized in that: step 1) further comprises the steps of: and depositing a first etching stop layer on the substrate, wherein the first etching stop layer covers the surface of the substrate, the side wall structure of the gate structure and the top surface of the gate structure, and the etching barrier layer is used as a second etching stop layer.

3. The method of manufacturing a semiconductor device according to claim 1, characterized in that: the grid structure comprises a first type grid and a second type grid, wherein the first type grid is located in a sheet resistance area, the second type grid is located in a non-sheet resistance area, the width of the first type grid is larger than that of the second type grid, and the sheet resistance is manufactured on the first type grid.

4. The method of manufacturing a semiconductor device according to claim 2, characterized in that: the gate dielectric layer of the first type gate comprises one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer of the first type gate comprises one of a polysilicon gate and a metal gate.

5. The method of manufacturing a semiconductor device according to claim 2, characterized in that: the gate dielectric layer of the second type gate comprises one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer of the second type gate comprises one of a polysilicon gate and a metal gate.

6. The method of manufacturing a semiconductor device according to claim 1, characterized in that: step 1) further comprises the steps of: and depositing a dielectric layer on the substrate, wherein the deposition thickness of the dielectric layer is larger than the height of the gate structure, and removing the dielectric layer above the top surface of the gate structure through a chemical mechanical polishing process so that the top surface of the dielectric layer is flush with the top surface of the gate structure.

7. The method of manufacturing a semiconductor device according to claim 1, characterized in that: the material of the resistance buffer layer comprises silicon dioxide, the material of the resistance layer comprises titanium nitride or tantalum nitride, and the material of the etching barrier layer comprises silicon nitride, silicon oxynitride and a silicon nitride-silicon oxynitride combined layer.

8. The method of manufacturing a semiconductor device according to claim 1, characterized in that: and 7) removing the resistance layer on the substrate through a wet etching process or a dry etching process.

9. A semiconductor device, comprising:

the semiconductor structure comprises a substrate and a gate structure positioned on the substrate, wherein the gate structure comprises a stacked gate dielectric layer and a gate electrode layer, a side wall structure is formed on the periphery of the gate structure, and a resistor groove is formed by removing part of the thickness of the gate electrode layer;

the resistor buffer layer is arranged in the resistor groove;

the resistor layer is arranged on the resistor buffer layer;

and the etching barrier layer is arranged on the resistor layer, and the resistor buffer layer, the resistor layer and the etching barrier layer are filled in the resistor groove to form a sheet resistor.

10. The semiconductor device according to claim 9, wherein: the substrate is also provided with a first etching stop layer, the first etching stop layer covers the surface of the substrate and the side wall structure of the gate structure, and the etching stop layer is used as a second etching stop layer.

11. The semiconductor device according to claim 9, wherein: the grid structure comprises a first type grid and a second type grid, wherein the first type grid is located in a sheet resistance area, the second type grid is located in a non-sheet resistance area, the width of the first type grid is larger than that of the second type grid, and the sheet resistance is manufactured on the first type grid.

12. The semiconductor device according to claim 9, wherein: the gate dielectric layer of the first type gate comprises one of a silicon oxide layer and a high-k dielectric layer, the gate electrode layer of the first type gate comprises one of a polysilicon gate and a metal gate, the gate dielectric layer of the second type gate comprises one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer of the second type gate comprises one of a polysilicon gate and a metal gate.

13. The semiconductor device according to claim 9, wherein: the material of the resistance buffer layer comprises silicon dioxide, the material of the resistance layer comprises titanium nitride or tantalum nitride, and the material of the etching barrier layer comprises silicon nitride, silicon oxynitride and a silicon nitride-silicon oxynitride combined layer.

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