CN116056511A

CN116056511A - Display panel, display module and display device

Info

Publication number: CN116056511A
Application number: CN202211574450.2A
Authority: CN
Inventors: 王迪; 朱修剑; 吕兰芬; 张金方; 杨杨
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd; Hefei Visionox Technology Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd; Hefei Visionox Technology Co Ltd
Priority date: 2022-12-08
Filing date: 2022-12-08
Publication date: 2023-05-02

Abstract

The invention provides a display panel, a display module and a display device. The display panel comprises a first area and a second area arranged on at least one side of the first area; the second area is provided with at least two rows of bonding pads, and the distances between bonding pads of different rows and the first area are different; the at least two rows of pads include a first pad and a second pad, the first pad being closer to the first region than the second pad; the second wiring connected with the second bonding pad extends to the first area; the orthographic projection of at least part of the second wire on the substrate of the display panel is positioned between the orthographic projections of the adjacent two first bonding pads on the substrate of the display panel, and the part of the second wire positioned between the adjacent two first bonding pads is provided with a first insulating layer between the first bonding pads. By adopting the scheme of the invention, the short circuit between the second wiring and the first bonding pad in the FPC binding process can be avoided, and the normal display effect is finally ensured.

Description

Display panel, display module and display device

Technical Field

The invention relates to a display panel, a display module and a display device, and belongs to the technical field of display.

Background

OLED (organic light-emitting diode) has a series of advantages of self-luminescence, wide viewing angle, light weight, thin weight, high brightness, low power consumption, quick response and the like, so that the OLED display panel becomes a very popular display device at home and abroad, and has wide application prospect.

In some schemes for manufacturing an OLED display panel, a portion of the display panel needs to be bent to the back, then an Integrated Circuit (IC) chip and a Flexible circuit board (Flexible PrintedCircuit, FPC) are bound to a PAD (i.e., a bonding PAD or a connection terminal) bent to the back through a binding process, and then the purpose of electrically connecting the display panel and a motherboard is achieved through an FPC. In a common scheme, the PADs are generally in a single-row structure, but in some schemes, the PADs are in a double-row structure, and part of wires are required to be arranged between the PADs in a penetrating way, so that the problem of short circuit between the PADs and the penetrating wires can occur in the binding process.

Disclosure of Invention

The invention provides a display panel, a display module and a display device, which are used for solving the problem of PAD and alternate wiring short circuit possibly occurring when a double-row PAD structure is bound.

In a first aspect, an embodiment of the present invention provides a display panel, including a first region and a second region disposed at least one side of the first region; the second region is provided with at least two rows of bonding pads, and the distances between bonding pads of different rows and the first region are different; the at least two rows of pads include a first pad and a second pad, the first pad being closer to the first region than the second pad; a second wire connected with the second bonding pad extends to the first region;

the orthographic projection of at least part of the second wire on the substrate of the display panel is positioned between the orthographic projections of two adjacent first bonding pads on the substrate of the display panel, and a first insulating layer is arranged between the part of the second wire positioned between the two adjacent first bonding pads and the first bonding pad.

Based on the above display panel, optionally, the second trace includes a first sub-line, a second sub-line, and a third sub-line that are sequentially connected, the first sub-line is connected to the second pad, and the third sub-line extends to the first region;

the orthographic projection of the second sub-line on the substrate of the display panel is positioned between the orthographic projections of the adjacent two first bonding pads on the substrate of the display panel, and the first insulating layer is positioned on one side of the second sub-line close to the first bonding pads and extends to one side of the first bonding pads close to the second sub-line.

Based on the above display panel, optionally, the first sub-line and the third sub-line are arranged in the same layer and are arranged in different layers from the second sub-line;

preferably, the bonding pad comprises a single metal layer, and the first sub-line and the third sub-line are arranged on the same layer as the bonding pad;

alternatively, the pad includes a plurality of metal layers, and the first sub-line and the third sub-line are disposed in the same layer as an uppermost metal layer of the pad.

Based on the above display panel, optionally, the first region includes a plurality of driving transistors, and the second sub-lines are disposed in the same layer as the gates of the driving transistors;

preferably, in the area where the second sub-line is located, the second area of the display panel includes a gate insulating layer, the second sub-line, a capacitor insulating layer, an interlayer dielectric layer, a planarization layer and a second insulating layer that are sequentially stacked.

Based on the above display panel, optionally, the first pad and the second pad are each electrically connected to a touch electrode disposed at the first region.

Based on the above display panel, optionally, the first sub-line and the third sub-line are arranged on the same layer, and a third insulating layer is arranged between the layer where the first sub-line and the third sub-line are located and the layer where the second sub-line is located, and the first sub-line and the third sub-line are electrically connected with the second sub-line through a line changing hole penetrating through the third insulating layer.

Based on the above display panel, optionally, the third insulating layer includes the first insulating layer, a planarization layer disposed on the first insulating layer, and a second insulating layer disposed on the planarization layer.

Based on the above display panel, optionally, the length of the second sub-line is greater than the length of the first pad.

In a second aspect, an embodiment of the present invention further provides a display module, which includes the display panel according to any one of the first aspect.

In a third aspect, an embodiment of the present invention further provides a display device, which includes the display module.

In the display panel, the display module and the display device provided by the invention, the display panel comprises a first area and a second area arranged on at least one side of the first area; the second area is provided with at least two rows of bonding pads, and the distances between bonding pads of different rows and the first area are different; the at least two rows of pads include a first pad and a second pad, the first pad being closer to the first region than the second pad; the second wiring connected with the second bonding pad extends to the first area; the orthographic projection of at least part of the second wire on the substrate of the display panel is positioned between the orthographic projections of the adjacent two first bonding pads on the substrate of the display panel, and the part of the second wire positioned between the adjacent two first bonding pads is provided with a first insulating layer between the first bonding pads. Therefore, the first insulating layer is arranged between the first bonding pads and the part, between the orthographic projections of the second wiring on the substrate of the display panel and the orthographic projections of the two adjacent first bonding pads on the substrate of the display panel, of the first insulating layer, so that the insulation between the second wiring and the first bonding pads can be ensured by the first insulating layer, and further, short circuits between the second wiring and the first bonding pads can be avoided during binding, and finally, the normal display effect is ensured.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. Furthermore, these drawings and the written description are not intended to limit the scope of the inventive concept in any way, but to illustrate the inventive concept to those skilled in the art by referring to the specific embodiments.

Fig. 1 is a schematic structural view of a display panel having double rows of pads;

FIG. 2 is a schematic diagram of a bonding pad structure of the display panel shown in FIG. 1;

fig. 3 is an enlarged schematic view of a region P in fig. 2;

FIG. 4 is a schematic cross-sectional view of the structure shown at AA' in FIG. 3;

fig. 5 is a schematic diagram of a pad structure of a display panel according to an embodiment of the present invention;

FIG. 6 is an enlarged schematic view of region Q of FIG. 5;

FIG. 7 is a schematic cross-sectional view of the BB' in FIG. 6;

FIG. 8 is a schematic cross-sectional view of the structure of the portion CC' in FIG. 6;

FIG. 9 is a schematic view of another cross-sectional structure at BB' in FIG. 6;

fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Reference numerals illustrate:

10-display area; 20-a non-display area; 30-bonding pads; 30 a-an uppermost metal layer of the pad; 301-a first bonding pad; 301 a-an uppermost metal layer of the first pad; 302-a second pad; 40-wiring; 401-a first trace; 402-a second trace; 402 a-a first sub-line; 402 b-a second sub-line; 402 c-a third sub-line; 50-a first insulating layer; 500-a capacitance insulating layer; 501-an interlayer dielectric layer; 502-planarizing layer; 503-a touch buffer layer; 504-a touch insulating layer; 505-a gate insulation layer; 60-a second insulating layer; 70-a third insulating layer; 701-line changing hole.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described in the following in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. The following embodiments and features of the embodiments may be combined with each other without conflict.

Summary of the application

In the display panel, the role of the pads includes for binding the IC and the FPC, and in practice, the number of pads may be adaptively set according to the number of binding pins the IC and the FPC have. For binding of the FPC, it is most common at present to arrange a single-row bonding pad, that is, a plurality of bonding pads are arranged in a single row, so that the design and binding of binding pins of the FPC are facilitated. However, in some scenarios, the number of FPC pads required is high, and when pads are arranged in a single row, the space is insufficient, so that in some schemes, arranging double rows of pads is considered.

Referring to fig. 1 to 4, fig. 1 is a schematic structural view of a display panel having double rows of pads, fig. 2 is a schematic structural view of pads of the display panel shown in fig. 1, fig. 3 is an enlarged schematic view of a region P of fig. 2, and fig. 4 is a schematic sectional structural view at AA' of fig. 3. As shown in fig. 1, the display panel includes a first area, which is a display area 10 in the present embodiment, and a second area, which is a non-display area 20. A plurality of array-arranged sub-pixels (not shown) are disposed in the display area 10, two rows of pads 30 exposed to the outside are disposed in the non-display area 20, the two rows of pads 30 are different in distance from the display area 10, one end of each pad 30 is electrically connected to a circuit device (not shown) in the display area 10, such as a touch electrode or a thin film transistor, etc., through a trace 40, and, as shown in fig. 1 and 2, the trace 40 of the pads 30 relatively far from the display area 10 needs to pass through a gap between the pads 30 relatively close to the display area 10 and then be connected to the circuit device in the display area 10.

In a subsequent process after forming the pad 30, the FPC may be bonded to the pad 30 through a bonding process for the purpose of electrical connection of the FPC with the circuit devices in the display area 10. The bonding process is mainly implemented based on ACF (anisotropic conductive film), wherein the ACF includes an adhesive and conductive particles, and when bonding, the conductive particles are used to implement a conductive function between the bonding pad 30 and a bonding pin of the FPC.

However, in the process of actually manufacturing the display panel, the inventor has found that a problem of short circuit between the pad 30 and the interposed trace 40 may occur when the FPC is bound, and after such a short circuit occurs, a problem of transmitting an error signal may occur in the display process, thereby affecting the final display effect. The inventors have found after study that the cause of the short circuit problem is as follows:

referring to fig. 3 and 4, the trace 40 passing between adjacent pads 30 is on the same layer as the uppermost metal layer 30a of the pad, that is, is etched from the same metal layer, and because the space between the pad 30 and the trace 40 is smaller, conductive particles may diffuse between the pad 30 and the trace 40 during the binding process, thereby shorting the pad 30 and the trace 40.

In order to solve the problems, the invention provides a scheme for insulating wires passing through adjacent bonding pads from the bonding pads through an insulating layer, so that the problem of short circuit in the binding process can be avoided, and the display effect is ensured. The specific implementations are described below without limitation by way of several examples or embodiments.

Exemplary display Panel

Referring to fig. 5 to 7, fig. 5 is a schematic diagram of a pad structure of a display panel according to an embodiment of the present invention, fig. 6 is an enlarged schematic diagram of a region Q in fig. 5, and fig. 7 is a schematic diagram of a cross-sectional structure at BB' in fig. 6.

The display panel of this embodiment is similar to the display panel shown in fig. 1, and includes a first region and a second region disposed on at least one side of the first region, where the first region may be the display region 10, the second region may be the non-display region 20, and the following embodiments will be described by taking this as an example, but it should be understood that the first region is not limited to the first region and the second region must be the non-display region.

Referring to fig. 5 to 7, the non-display area 20 is provided with at least two rows of pads, and the pads of different rows are different in distance from the display area 10. It should be noted that, in the drawings of the present embodiment, only two rows of pads are shown, but it is to be understood that the scheme of the present embodiment can be applied to schemes with more than two rows of pads, and this is not limited.

For the convenience of subsequent understanding and explanation, in the present embodiment, two rows of pads are shown to be divided into a plurality of first pads 301 and a plurality of second pads 302 according to the distance from the display area 10, wherein the first pads 301 are closer to the display area 10 than the second pads 302. It should be noted that the first pad 301 and the second pad 302 may be different only in the arrangement position, and the film structure, the shape, and the like may be the same.

Correspondingly, the wires connected to the first bonding pad 301 are the first wires 401, the wires connected to the second bonding pad 302 are the second wires 402, and both the first wires 401 and the second wires 402 extend into the display area 10, wherein the first bonding pad 301 can be electrically connected to a first device disposed in the display area 10 through the first wires 401, and the second bonding pad 302 can be electrically connected to a second device disposed in the display area 10 through the second wires 402. The first device and the second device may be, but not limited to, different touch electrodes corresponding to different touch positions, and so on. In addition, in each embodiment of the present invention, a plurality means at least two unless otherwise specified.

On this basis, at least part of the orthographic projection of the second trace 402 on the substrate of the display panel is located between the orthographic projections of the adjacent two first pads 301 on the substrate of the display panel, and the portion of the orthographic projection of the second trace 402 on the substrate of the display panel located between the orthographic projections of the adjacent two first pads 301 on the substrate of the display panel and the first pad 301 have the first insulating layer 50 therebetween.

Firstly, it should be noted that, in practice, the metal layer of the pad for the touch function (relative to the metal layers of the pads for other functions) is located at the side farthest from the substrate, so the foregoing short circuit problem is most likely to occur in the bonding process of the pad for the touch function to the FPC, and therefore, the solution of each embodiment described above is most suitable for the pad for the touch function. That is, the above-described schemes of the embodiments are most suitable for a scheme in which both the first pad 301 and the second pad 302 are electrically connected to the touch electrode disposed in the display area 10, for ensuring stable transmission of the touch signal, and avoiding occurrence of a short circuit abnormality. In this regard, in the embodiments of the present invention and the drawings, the example in which the first pad 301 and the second pad 302 are connected to the touch electrode is described. It will be appreciated that the schemes provided by the embodiments of the present invention are also contemplated for pads of other functions, and are not limited in this regard.

Specifically, there are various ways of realizing the provision of the above-described first insulating layer 50, and the following is exemplified by examples.

Referring to fig. 5 and 6, in some embodiments, the second trace 402 includes a first sub-line 402a, a second sub-line 402b, and a third sub-line 402c connected in sequence; the first sub-line 402a is connected to the second bonding pad 302, the third sub-line 402c extends to the display area 10, and the orthographic projection of the second sub-line 402b on the substrate of the display panel is located between the orthographic projections of the adjacent two first bonding pads 301 on the substrate of the display panel, that is, the second wiring 402 is divided into three sub-lines according to the extending direction from the second bonding pad 302 to the second device in this embodiment, namely, the first sub-line 402a, the second sub-line 402b and the third sub-line 402c. Also, the first insulating layer 50 is located at a side of the second sub-line 402b near the first pad 301 and extends to a side of the first pad 301 near the second sub-line 402b. Wherein, the first sub-line 402a and the third sub-line 402c are preferably arranged in the same layer and in a different layer from the second sub-line 402b. When the first sub-line 402a and the third sub-line 402c are arranged in the same layer, the first sub-line 402a and the third sub-line 402c can be formed in the same process stage by using the same metal film layer, so that the process steps are reduced. Of course, the first sub-line 402a and the third sub-line 402c may be provided in different layers as long as effective insulation between the second sub-line 402b and the first pad 301 can be ensured.

Specifically, in this embodiment, the second sub-line 402b may be formed at a corresponding position, then the entire first insulating layer 50 is formed on the second sub-line 402b to cover the second sub-line 402b, and then the structures such as the first bonding pad 301 and the second bonding pad 302 are formed on the first insulating layer 50, so that the second sub-line 402b and the first bonding pad 301 may be separated by the first insulating layer 50, and insulation therebetween is ensured. Based on this, in the subsequent FPC bonding process, even if the conductive particles diffuse from the first pad 301 to the gap between the adjacent two first pads 301, the conductive particles cannot contact the second sub-line 402b due to the blocking effect of the first insulating layer 50, so that the short circuit problem between the second sub-line 402b and the first pad 301 can be effectively avoided.

Further, in some embodiments, the display area 10 includes a plurality of driving transistors, and the second sub-line 402b is disposed at the same layer as the gate of the driving transistor.

Specifically, the driving transistor is disposed on the circuit array layer of the display panel, and is used for driving each sub-pixel of the display area 10 to emit light. In the driving transistor, an interlayer dielectric layer 501 made of an insulating material is disposed above the gate electrode, so as to ensure insulation between the gate electrode and the source/drain electrode. In this case, when the second sub-line 402b is provided in the same layer as the gate electrode of the driving transistor, the interlayer dielectric layer 501 may be used as the first insulating layer. Alternatively, in other embodiments, the capacitor insulating layer 500 and the interlayer dielectric layer 501 made of insulating materials are disposed above the gate electrode, and as shown in fig. 7, the interlayer dielectric layer 501 and the capacitor insulating layer 500 may be used together as the first insulating layer.

More specifically, in the process of forming the gate electrode, a semiconductor active layer is typically formed on a Buffer layer (Buffer), then a gate insulating layer is formed on the semiconductor active layer, then a whole first metal layer (which may be generally referred to as an M1 metal layer in the art, its material is typically molybdenum metal) is formed on the gate insulating layer, then the first metal layer is etched, the location where the gate electrode is to be formed is reserved, and the remaining metal material at the unwanted location is removed by etching. Based on this, in this embodiment, the etching position may be adjusted, and the metal material for forming the second sub-line 402b is reserved in a specific position in addition to the reserved gate electrode, that is, the second sub-line 402b is formed by etching in synchronization with the etching. Based on this, in some embodiments, as shown in fig. 7, in the area where the second sub-line 402b is located, the non-display area of the display panel includes a gate insulating layer 505, the second sub-line 402b, a capacitor insulating layer 500, an interlayer dielectric layer 501, a planarization layer 502, and a second insulating layer 60 that are stacked in order. The second insulating layer 60 may include a touch buffer layer 503 and a touch insulating layer 504, where the touch buffer layer 503 and the touch insulating layer 504 together perform an insulating and buffering function.

In this arrangement, there is no need to additionally prepare a metal material layer for forming the second sub-line 402b, so that process steps can be saved, and since the gate electrode is located on one side of the substrate closer to the display panel in each film layer of the entire display panel, the second sub-line 402b is formed farther from the first pad 301, so that an insulating effect between the two can be more effectively ensured.

Further, with continued reference to fig. 6, in some embodiments, the length of the second sub-line 402b is greater than the length of the first pad 301. In this way, the distances between the first sub-line 402a and the third sub-line 402c and the first pad 301 are increased, so that the insulation effect between the second trace 402 and the first pad 301 can be better ensured. Of course, it is understood that the length of the second sub-line 402b may be equal to or even smaller than the length of the first pad 301, and still improve the possible short circuit problem to some extent.

In addition, referring to fig. 8, fig. 8 is a schematic cross-sectional structure of the CC' in fig. 6, in some embodiments, the first sub-line 402a and the third sub-line 402c are disposed in the same layer, and a third insulating layer 70 is disposed between the layers of the first sub-line 402a and the third sub-line 402c and the layer of the second sub-line 402b, and the first sub-line 402a and the third sub-line 402c are electrically connected to the second sub-line 402b through a line exchanging hole 701 penetrating the third insulating layer 70.

Specifically, in this embodiment, the jumper design is equivalent to the jumper design through the line changing hole 701. That is, the second trace 402 extends from a position connected to the second pad 302 at the first side (upper side in fig. 8) of the third insulating layer 70 to a position penetrating into the gap between the two first pads 301, and the length of trace is the first sub-line 402a; the second trace 402 is then shifted to the second side (the lower side in fig. 8) of the third insulating layer 70 through a line shifting hole (not shown in fig. 8), and extends to a position away from the gap between the two first pads 301, where the second trace is the second sub-trace 402b; then, the second trace 402 is changed to the first side of the third insulating layer 70 through the line changing hole 701, and extends in the direction of the display area 10 all the way, and this section of trace is the third sub-line 402c. So configured, the first sub-line 402a and the third sub-line 402c can be made to follow the existing design scheme, while only the position and structure of the second sub-line 402b are adjusted so that the existing process is adjusted as little as possible.

With continued reference to fig. 8, when such a structure is employed, the third insulating layer 70 includes a capacitance insulating layer 500 and an interlayer dielectric layer 501 as the first insulating layer 50, and further includes a planarization layer 502 and a second insulating layer 60 sequentially provided on the first insulating layer 50.

For example, in some embodiments, as shown in fig. 6, the first pad 301 includes multiple metal layers, and the first sub-line 402a and the third sub-line 402c are disposed in the same layer as the uppermost metal layer 301a of the first pad. The uppermost metal layer 301a of the first pad, i.e., the metal layer farthest from the substrate of the display panel, is used for contacting with the ACF conductive paste and electrically connecting with the FPC. The arrangement of the first sub-line 402a and the third sub-line 402c in the same layer as the uppermost metal layer 301a of the first pad is consistent with the existing structure, so that the formation process thereof does not need to be adjusted by the existing process. In addition, the first bonding pad 301 is designed to include multiple metal layers, so that the first bonding pad 301 can be guaranteed to be better conducted, which is beneficial to the execution of subsequent processes. Among the multiple metal layers of the first pad 301, a part of the metal layers may be disposed in the same layer as a part of the metal layers in the display area 10 and formed in the same process stage, for example, a metal layer forming a source/drain electrode of the driving transistor may be used, and when the source/drain electrode is formed by etching, one of the metal layers of the first pad 301 is formed by etching simultaneously.

Of course, it is understood that in other embodiments, the first pad 301 may include only one metal layer, and the first sub-line 402a and the third sub-line 402c are disposed on the same layer as the first pad 301. In the case where the first bonding pad 301 includes only one metal layer, the binding function thereof can be also realized, while the film layer structure of the first bonding pad 301 can be simplified, but the conductive ability is inferior to that of a plurality of metal layers.

In addition, the specific structure of the second pad 302 may be the same as that of the first pad 301, and thus will not be described again.

In addition, another way of realizing the provision of the above-mentioned first insulating layer is as follows:

referring to fig. 9, fig. 9 is another cross-sectional structure diagram at BB' in fig. 6. As shown in fig. 9, in the present embodiment, the film structure at the first pad 301 is similar to the film structure at the first pad 301 shown in fig. 7, except that the second sub-line 402b is disposed above the interlayer dielectric layer 501, and at this time, the planarization layer 502, the touch buffer layer 503, and the touch insulating layer 504 are used together as the first insulating layer 50. Also, in practice, the second sub-line 402b may be disposed in the same layer as the lowermost or intermediate metal layer among the plurality of metal layers of the first pad 301 in order to reduce the adjustment of the process.

In addition, for other film structures not illustrated in fig. 9, reference may be made to the descriptions of the foregoing embodiments, and the descriptions are omitted here.

Of course, in addition to the two implementations listed above, the second sub-line 402b may be disposed in other film layers, and accordingly, the film layer position and the film layer structure of the first insulating layer 50 need only be correspondingly adjusted, which is not listed.

In the solutions of the foregoing embodiments, the first insulating layer is disposed between the first bonding pad and the portion of the second wire between the orthographic projections of the two adjacent first bonding pads on the substrate of the display panel, where the orthographic projections of the second wire on the substrate of the display panel are located, so that the first insulating layer can ensure insulation between the second wire and the first bonding pad, and further can avoid a short circuit between the second wire and the first bonding pad when the FPC is bound, and finally ensure that the display effect is normal.

In addition, the display panel includes other structures and film layers necessary for realizing the functions thereof, in addition to the structures and film layers mentioned in the above embodiments. Since the present invention may not be modified for these film layers, detailed description will not be given.

Exemplary display Module

The embodiment of the invention also provides a display device module, which comprises the display panel in any embodiment. The display module can further comprise a polarizer, an optical adhesive layer, a cover plate and the like which are arranged on the display side of the display panel, and a support film, a composite adhesive tape, an insulating adhesive tape and the like which are arranged on the non-display side of the display panel.

Exemplary display device

The embodiment of the invention also provides a display device, which comprises the display module. Fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention, where the display device may be a smart phone, a tablet computer, a digital camera, and the like.

Exemplary embodiments are described herein with reference to plan views as idealized exemplary figures. In the drawings, the size of the region is exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

Unless otherwise defined, technical or scientific terms used in the embodiments of the present invention should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present invention belongs. The terms "first," "second," and the like, as used in embodiments of the present invention, do not denote any order, quantity, or importance, but rather are used to avoid intermixing of components.

Throughout this specification, unless the context requires otherwise, the term "comprise" is to be construed in an open, inclusive sense, i.e. as "comprising, but not limited to. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "examples," "particular examples," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

Claims

1. A display panel comprising a first region and a second region disposed on at least one side of the first region; the second region is provided with at least two rows of bonding pads, and the distances between bonding pads of different rows and the first region are different; the at least two rows of pads include a first pad and a second pad, the first pad being closer to the first region than the second pad; a second wire connected with the second bonding pad extends to the first region;

2. The display panel of claim 1, wherein the second trace includes a first sub-line, a second sub-line, and a third sub-line connected in sequence, the first sub-line being connected to the second pad, the third sub-line extending to the first region;

3. The display panel of claim 2, wherein the first sub-line and the third sub-line are disposed in a same layer and are disposed in a different layer from the second sub-line;

4. The display panel of claim 2, wherein the first region includes a plurality of driving transistors, the second sub-lines being disposed in the same layer as gates of the driving transistors;

5. The display panel of claim 1, wherein the first pad and the second pad are each electrically connected to a touch electrode disposed at the first region.

6. The display panel according to claim 2, wherein the first sub-line and the third sub-line are arranged in the same layer, and a third insulating layer is arranged between the layer where the first sub-line and the third sub-line are arranged and the layer where the second sub-line is arranged, and the first sub-line and the third sub-line are electrically connected with the second sub-line through a line changing hole penetrating through the third insulating layer.

7. The display panel of claim 6, wherein the third insulating layer comprises the first insulating layer, a planarization layer disposed on the first insulating layer, and a second insulating layer disposed on the planarization layer.

8. The display panel of claim 2, wherein a length of the second sub-line is greater than a length of the first pad.

9. A display module comprising a display panel according to any one of claims 1-8.

10. A display device comprising the display module of claim 9.