CN116015279A - Clock configuration method, device, equipment and medium of programmable logic device - Google Patents

Abstract

The application belongs to the technical field of programmable logic devices, and discloses a clock configuration method, device, equipment and medium of a programmable logic device. The method provided by the application comprises the following steps: configuring a programmable logic device to convert a received clock input signal into a plurality of clock output signals of different phases; each functional module of the configuration programmable logic device receives the clock output signal respectively; the number of the functional modules is the same as the number of the clock output signals; according to the method, clock phase modulation is carried out on the clock input signals received by the programmable logic device, a plurality of clock output signals with different phases are separated, so that all functional modules of the programmable logic device originally under the same clock domain can operate in different phases under the same clock frequency, logic units and related circuit devices inside the programmable logic device avoid the scene of turning at the same moment, further clock radiation is obviously reduced, and electromagnetic interference can be improved on the basis of not increasing additional hardware cost.

Description

Clock configuration method, device, device and medium of programmable logic device

technical field

The application belongs to the technical field of programmable logic devices, and relates to a clock configuration method, device, equipment and medium of a programmable logic device.

Background technique

Electromagnetic Interference (EMI for short) refers to the influence of the circuit system on the peripheral circuit system of the circuit system through conduction interference or radiation interference during operation. Therefore, in order to ensure the normal operation of the entire circuit system, the research and development of electronic products It must comply with the electromagnetic compatibility specifications promulgated by relevant agencies to ensure that the electronic products on the market meet the specification requirements.

With the development of integrated circuit technology, the clock frequency of digital signals in programmable logic devices (FPGA, CPLD, etc.) is getting higher and higher. Improving the radiation interference caused by the clock of programmable logic devices has been faced by every application manufacturer. Problem, the traditional technical solution achieves the effect of improving electromagnetic interference by adding a spread spectrum chip between the crystal oscillator clock and the programmable logic device to configure the clock of the programmable logic device, but adding a spread spectrum chip will also increase the hardware cost of the product And research and development costs, and for programmable logic devices that have been mass-produced, adding a spread spectrum chip requires retesting the product, which greatly lengthens the project time.

Contents of the invention

The purpose of this application is to provide a clock configuration method, device, equipment and medium of a programmable logic device, so as to solve the technical problem of high cost required for improving electromagnetic interference in traditional technical solutions.

In order to solve the problems of the technologies described above, the technical scheme of the present application is as follows:

The present application provides a clock configuration method of a programmable logic device, including:

Configuring the programmable logic device to convert the received clock input signal into several clock output signals with different phases;

Each functional module of the programmable logic device is configured to receive the clock output signal respectively; wherein, the number of the functional modules is the same as the number of the clock output signal.

Further, the clock configuration method of the programmable logic device also includes:

Generate a configuration bit stream file, download the configuration bit stream file to the programmable logic device to configure the programmable logic device, the configured programmable logic device is used for:

receiving a clock input signal, converting the clock input signal into several clock output signals with different phases and outputting them to the functional modules of the programmable logic device respectively.

Further, the step of configuring the programmable logic device to convert the received clock input signal into several clock output signals with different phases includes:

The phase-locked loop module of the programmable logic device is configured according to the number of the functional modules, so that the clock input signal outputs several clock output signals with different phases through the phase-locked loop module.

Further, the step of configuring each functional module of the programmable logic device to respectively receive the clock output signal includes:

Instantiate the primitives of the programmable logic device, so that the clock output signal output by the phase-locked loop module is the clock signal of the global clock of the programmable logic device, or the clock signal of the local clock of the programmable logic device clock signal, and

The clock output signal output by the phase-locked loop module can drive each of the functional modules.

Further, after the step of instantiating the primitives of the programmable logic device, it also includes:

A data buffer is configured for the functional module, and the data buffer is used to implement data buffering in different clock domains of the programmable logic device.

Further, after the step of instantiating the data buffer, it also includes:

The functional modules are constrained to the layout positions of the functional modules according to the area constraints of the programmable logic device.

Further, the step of constraining the functional modules to the layout positions of the functional modules according to the area constraints of the programmable logic device further includes:

The functional modules are constrained to avoid layout locations that are seriously affected by electromagnetic interference.

Based on the clock configuration method of any of the above-mentioned programmable logic devices, the present application also provides a clock configuration method of a programmable logic device, and the device includes:

The first configuration module is used to configure the programmable logic device to convert the received clock input signal into several clock output signals with different phases;

The second configuration module is configured to configure each functional module of the programmable logic device to receive the clock output signal respectively; wherein, the number of the functional modules is the same as the number of the clock output signal;

The third configuration module is configured to generate a configuration bit stream file, and download the configuration bit stream file to the programmable logic device to configure the programmable logic device, and the configured programmable logic device is used for:

receiving a clock input signal, converting the clock input signal into several clock output signals with different phases and outputting them to the functional modules of the programmable logic device respectively.

Based on the clock configuration method of any of the above programmable logic devices, the present application also provides an electronic device, including:

A memory, a processor, and a computer program stored in the memory and operable on the processor, when the processor executes the computer program, the clock configuration method for any of the programmable logic devices described above is implemented step.

Based on the clock configuration method of any of the above-mentioned programmable logic devices, the present application also provides a computer-readable storage medium, the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any of the above-mentioned A step of the clock configuration method of a programmable logic device.

Compared with the prior art, the beneficial effects of the present application are:

The clock configuration method of the programmable logic device provided by the embodiment of the present application performs clock phase modulation on the clock input signal received by the programmable logic device, and separates a plurality of clock output signals with different phases, so that the programmable logic device is originally in the same Each functional module in the clock domain can run in different phases at the same clock frequency, so that the logic unit and related circuit devices inside the programmable logic device avoid the scene of flipping at the same time, and then the clock radiation is significantly reduced. EMI can be improved at the cost of additional hardware.

In addition, the clock configuration method for programmable logic devices provided by the embodiment of the present application can perform multiple iterations according to actual needs, which not only avoids the complexity of redesigning hardware, shortens the time period of project design, and allows products to be used in different applications. Under scenario requirements, the effect of electromagnetic interference can be improved by upgrading the bit stream of the programmable logic device. If it is necessary to further reduce the influence of electromagnetic interference after using the clock configuration method of the programmable logic device provided in the embodiment of this application, you can use the above The clock input signal continues to be decomposed on a one-use basis to further reduce electromagnetic interference.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the accompanying drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only for the application. For some embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without any creative effort.

FIG. 1 is a schematic diagram of a product structure for implementing a clock configuration of a programmable logic device in a conventional technical solution.

FIG. 2 is a flow chart of a clock configuration method for a programmable logic device provided by an embodiment of the present application.

FIG. 3 is a schematic diagram of a product structure for realizing the clock configuration of a programmable logic device by the method for configuring a clock of a programmable logic device provided in an embodiment of the present application.

FIG. 4 is a schematic diagram of a clock configuration device for a programmable logic device provided in an embodiment of the present application.

FIG. 5 is a schematic diagram of an electronic device provided by an embodiment of the present application.

Fig. 6 is a schematic diagram of a computer storage medium provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be clear that the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

The terms "first", "second" and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances such that the embodiments of the application can be practiced in sequences other than those illustrated or described herein. In addition, "and/or" in the specification and claims means at least one of the connected objects, and the character "/" generally means that the related objects are an "or" relationship.

FPGA (Field Programmable Gate Array, FieldProgrammableGateArray) and CPLD (FieldProgrammableGateArray, Complex Programmable Logic Device) are the main types of programmable logic devices on the market. Note, but it should be clear that the clock configuration method for programmable logic devices provided in the embodiments of the present application is also applicable to CPLDs.

Figure 1 is a schematic diagram of the product structure of the traditional technical solution to realize the clock configuration of the programmable logic device. As shown in Figure 1, the crystal oscillator clock is used to output the clock signal, the spread spectrum chip reduces the frequency radiation caused by the clock, and the phase-locked loop module of the FPGA receives After the clock input signal is received, the clock input signal is multiplied and frequency-divided by the phase-locked loop module and then output to each functional module, wherein the frequency and phase of the clock signal received by each functional module are the same; in the traditional technical solution, in order to Reduce the frequency radiation caused by the programmable logic device clock, and improve the effect by adding a spread spectrum chip. The working principle of the spread spectrum chip is to modulate the spike clock to make it change from a narrowband clock signal to a clock signal with edge The spectrum of the band disperses the peak energy of the clock to multiple frequency segments in the spread spectrum area, thereby achieving the effect of reducing peak energy and suppressing EMI. However, the addition of hardware device spread spectrum chips will significantly increase the cost of the product, especially for programmable logic devices that have been mass-produced. Adding spread spectrum chips also requires retesting of the entire programmable logic device, which greatly lengthens the project Time is extremely unfavorable for product development and production; in order to solve this technical problem, the embodiment of the present application provides a clock configuration method for programmable logic devices, which can reduce the frequency radiation caused by the clock without increasing the hardware cost. The electromagnetic interference of the programmable logic device is improved.

Fig. 2 is a flowchart of the clock configuration method of the programmable logic device provided by the embodiment of the present application. As shown in Fig. 2, the clock configuration method of the programmable logic device provided by the embodiment of the present application includes:

Step S1: configuring the programmable logic device to convert the received clock input signal into several clock output signals with different phases.

Step S2: configuring each functional module of the programmable logic device to receive the clock output signal respectively; wherein, the number of the functional modules is the same as the number of the clock output signal.

In the embodiment of the present application, the clock input signal received by the programmable logic device is clock phase modulated, and multiple clock signals with different phases are separated, so that each functional module of the programmable logic device originally in the same clock domain can operate at the same clock frequency. The operation of different phases under different phases makes the logic unit and related circuit devices inside the programmable logic device avoid the scene of flipping at the same time, so that the clock radiation is significantly reduced, and the electromagnetic interference can be improved without increasing additional hardware costs. .

In some embodiments, the clock configuration method of the programmable logic device provided in the embodiment of the present application further includes:

Step S3: generate a configuration bit stream file, and download the configuration bit stream file to the programmable logic device to configure the programmable logic device; it should be clear that the design of the programmable logic device and some complicated upgrades or modifications after leaving the factory are all done through EDA ( Electronic design automation (electronic design automation) software executes the design process, and finally downloads the generated bit stream file to the programmable logic device to complete the design; therefore, the embodiment of the present application realizes the configuration of the programmable logic device function in steps S1 and S2 Finally, the corresponding configuration bit stream file should be generated, and the configuration bit stream file should be downloaded to the programmable logic device to configure the programmable logic device to realize the functions of step S1 and step S2. After the configured programmable logic device is actually running After receiving the clock input signal, it will convert the clock input signal into several clock output signals with different phases and output them to the functional modules of the programmable logic device respectively, so that the functional modules of the programmable logic device originally in the same clock domain Ability to operate at different phases at the same clock frequency.

It should be clear that for programmable logic devices that have been shipped out of the factory, when implementing the clock configuration method for programmable logic devices provided by the embodiment of the present application, if only a simple upgrade or modification of the programmable logic device is required, for example, only the clock input When the signal is decomposed into a few clock output signals with different phases, it can be configured directly through the hardware of the programmable logic device (when it is decomposed into two or three clock output signals, or some programmable logic devices can customize which In this case, it can be directly configured), and at this time, it can be implemented without using EDA software.

In some embodiments, the clock configuration method of a programmable logic device provided by the embodiment of the present application, step S1: the step of configuring the programmable logic device to convert the received clock input signal into several clock output signals with different phases includes :

The phase-locked loop module of the programmable logic device is configured according to the number of functional modules, so that the clock input signal outputs several clock output signals with different phases through the phase-locked loop module.

Figure 3 is a schematic diagram of the product structure of the clock configuration method of the programmable logic device provided by the embodiment of the application to realize the clock configuration of the programmable logic device, as shown in Figure 3, the crystal oscillator clock is used to generate the clock input signal, and the clock input signal is locked The phase loop module (PLL) generates a clock output signal and transmits it to each functional module of the programmable logic device. Among them, the phase locked loop module can input the received clock according to the clock frequency and electromagnetic radiation requirements After the signal is multiplied and divided, it is converted into multiple clock output signals with the same frequency but different phases.

A phase-locked loop is a negative feedback control system that uses phase synchronization to generate a voltage to tune a voltage-controlled oscillator to produce a target frequency. The most basic phase-locked loop system mainly includes three basic modules: phase detector, loop filter, which is actually a low-pass filter, and voltage-controlled oscillator. In actual use, the phase-locked loop system will also add some frequency dividers, frequency multipliers, mixers and other modules according to requirements. The purpose of the embodiment of the present application is to phase-modulate the clock input signal into multiple clock output signals with different phases. The working principle of the phase-locked loop module to realize the frequency multiplication and frequency division of the clock signal also belongs to the conventional technical means in the field, so here Only a simple description of the working principle of the phase-locked loop module is given.

In some embodiments, in the clock configuration method of the programmable logic device provided in the embodiment of the present application, step S2: the step of configuring each functional module of the programmable logic device to receive the clock output signal respectively includes:

Instantiate the primitives of the programmable logic device, make the clock output signal output by the phase-locked loop module be the clock signal of the global clock of the programmable logic device, or the clock signal of the local clock of the programmable logic device, and make the output signal of the phase-locked loop module The clock output signal can drive each functional module. For the phase-locked loop module, the configuration of the programmable logic device can be realized by directly instantiating the corresponding primitives of the phase-locked loop module. When improving the electromagnetic interference in a certain area of the programmable logic device, the phase-locked The clock signal output by the loop module is configured as the clock signal of the regional clock. When improving the overall electromagnetic interference of the programmable logic device, the clock signal output by the phase-locked loop module can be configured as the clock signal of the global clock of the programmable logic device. Specifically, a global clock or a regional clock (local clock) can be selected for configuration according to actual requirements.

Among them, the primitive of the programmable logic device is primitive, which is the name of a series of commonly used modules developed by the manufacturer according to the characteristics of the device. It is the basic component of the chip and represents the hardware logic unit actually used by the programmable logic device. Primitives can be instantiated and used in the design, which is the most direct way of code input.

In some embodiments, the clock configuration method of the programmable logic device provided in the embodiment of the present application, after the step of configuring the primitives of the programmable logic device in step S2, further includes:

Configure the data buffer for the function module. The data buffer is used for data buffer when the clock phase of the programmable logic device is different. The data buffer of the function module of the programmable logic device usually uses FIFO or RAM; taking FPGA as an example, each internal FPGA The function modules implement data buffering through FIFO or RAM, so as to avoid the function abnormality of each function module when each function module receives data under different clock phases.

Among them, FIFO (FirstInFirstOut, first-in-first-out data buffer), the classification of FIFO is divided into synchronous FIFO and asynchronous FIFO according to the clock domain where FIFO works. Synchronous FIFO means that the read clock and write clock are the same clock. Read and write operations occur simultaneously at the clock edge. Asynchronous FIFO means that the read and write clocks are inconsistent, and the read and write clocks are independent of each other. Synchronous FIFOs are often used for data buffering of synchronous clocks, and asynchronous FIFOs are often used for transmission of data signals across clock domains.

In some embodiments, the clock configuration method of the programmable logic device provided in the embodiment of the present application further includes after the step of configuring the data buffer for the functional module:

The functional modules are constrained to the layout positions of the functional modules according to the area constraints of the programmable logic device. When the clock configuration method of the programmable logic device provided by the embodiment of the present application is implemented by EDA software, after step S1 and step S2 are configured, in order to realize the normal operation of the programmable logic device, the clock input signal is decomposed into different When outputting the phase clock signal, FIFO or RAM should be configured for each functional module to cache data, and to arrange each functional module to a corresponding layout position.

In some embodiments, when the original layout position of the functional module is seriously affected by electromagnetic interference, the functional module can also be rearranged so that the functional module avoids the area seriously affected by electromagnetic interference.

Among them, the layout of each functional module is realized through regional constraints. Taking FPGA as an example, the role of regional constraints in FPGA is: select a certain position of FPGA to define the basic design unit, because there are many gate-level structures in FPGA, synthesis and Layout and routing are carried out according to the design logic, and the specific location of layout resources may be random, so the location of FPGA layout resources can be limited by imposing area constraints.

The clock configuration method of the programmable logic device provided by the embodiment of the present application, by using the bit stream upgrade method for the programmable logic device, performs clock phase modulation on the clock input signal received by the programmable logic device, and separates multiple different phases The clock output signal of the programmable logic device allows each functional module of the programmable logic device to be in the same clock domain to run at different phases at the same clock frequency, so that the logic unit and related circuit devices inside the programmable logic device avoid the same time Flipping the scene, and then significantly reducing the clock radiation, can improve electromagnetic interference without adding additional hardware costs.

In addition, the clock configuration method for programmable logic devices provided by the embodiment of the present application can perform multiple iterations according to actual needs, which not only avoids the complexity of redesigning hardware, shortens the time period of project design, and allows products to be used in different applications. Under scenario requirements, the effect of electromagnetic interference can be improved by upgrading the bit stream of the programmable logic device. If it is necessary to further reduce the influence of electromagnetic interference after using the clock configuration method of the programmable logic device provided in the embodiment of this application, you can use the above The clock input signal continues to be decomposed on a one-use basis to further reduce electromagnetic interference.

Based on the above-mentioned clock configuration method for a programmable logic device, an embodiment of the present application also provides a clock configuration device 40 for a programmable logic device, as shown in FIG. 4 , the device 40 includes:

The first configuration module 100 is configured to configure the programmable logic device to convert the received clock input signal into several clock output signals with different phases;

The second configuration module 200 is used to configure each functional module of the programmable logic device to receive the clock output signal respectively; wherein, the number of the functional modules is the same as the number of the clock output signal;

The third configuration module 300 is configured to generate a configuration bit stream file, download the configuration bit stream file to the programmable logic device to configure the programmable logic device, and the configured programmable logic device is used for:

The clock input signal is received, and the clock input signal is converted into several clock output signals of different phases, which are respectively output to the functional modules of the programmable logic device.

For other details of implementing the above technical solution by each module in the clock configuration device of the programmable logic device, refer to the description in the clock configuration method of the programmable logic device provided in the above embodiment, and details are not repeated here.

Based on the clock configuration method of the above-mentioned programmable logic device, the embodiment of the present application also provides an electronic device 50, as shown in FIG. 5, including a memory 51, a processor 52, and a The computer program, when the processor executes the computer program, implements the steps of the method for configuring the clock of the programmable logic device provided in the above embodiment.

Based on the clock configuration method of the above programmable logic device, the embodiment of the present application also provides a computer-readable storage medium 60, as shown in Figure 6, the computer-readable storage medium 60 stores a computer program 61, and the computer program 61 is processed The steps of implementing the clock configuration method for a programmable logic device provided in the foregoing embodiments are implemented when the device is executed.

The above content is a further detailed description of the present application in conjunction with specific implementation modes, and it cannot be considered that the specific implementation of the present application is limited to these descriptions. For those of ordinary skill in the technical field to which this application belongs, some simple deduction or substitutions can be made without departing from the concept of this application, which should be regarded as the protection scope of this application.

Claims (10)

1. A clock configuration method of a programmable logic device, characterized in that, comprising: Configuring the programmable logic device to convert the received clock input signal into several clock output signals with different phases; Each functional module of the programmable logic device is configured to receive the clock output signal respectively; wherein, the number of the functional modules is the same as the number of the clock output signal. 2. the clock configuration method of programmable logic device as claimed in claim 1, is characterized in that, also comprises: Generate a configuration bit stream file, download the configuration bit stream file to the programmable logic device to configure the programmable logic device, the configured programmable logic device is used for: receiving a clock input signal, converting the clock input signal into several clock output signals with different phases and outputting them to the functional modules of the programmable logic device respectively. 3. the clock configuration method of programmable logic device as claimed in claim 1 is characterized in that, described configuration described programmable logic device is the clock input signal that will receive is converted into the clock output signal of several different phases steps, including: The phase-locked loop module of the programmable logic device is configured according to the number of the functional modules, so that the clock input signal outputs several clock output signals with different phases through the phase-locked loop module. 4. the clock configuration method of programmable logic device as claimed in claim 3 is characterized in that, each functional module of described configuration described programmable logic device receives the step of described clock output signal respectively, comprises: Instantiate the primitives of the programmable logic device, so that the clock output signal output by the phase-locked loop module is the clock signal of the global clock of the programmable logic device, or the clock signal of the local clock of the programmable logic device clock signal, and The clock output signal output by the phase-locked loop module can drive each of the functional modules. 5. the clock configuration method of programmable logic device as claimed in claim 4 is characterized in that, after the step of the primitive language of described instantiation described programmable logic device, also comprises: A data buffer is configured for the functional module, and the data buffer is used to implement data buffering in different clock domains of the programmable logic device. 6. the clock configuration method of programmable logic device as claimed in claim 5 is characterized in that, after the described step of disposing data register for described functional module, also comprises: The functional modules are constrained to the layout positions of the functional modules according to the area constraints of the programmable logic device. 7. the clock configuration method of programmable logic device as claimed in claim 6 is characterized in that, the step of constraining described functional module to the layout position of described functional module according to the regional constraint of described programmable logic device ,Also includes: The functional modules are constrained to avoid layout locations that are seriously affected by electromagnetic interference. 8. A clock configuration device for a programmable logic device, characterized in that, comprising: A first configuration module, configured to configure the programmable logic device to convert the received clock input signal into several clock output signals with different phases; The second configuration module is configured to configure each functional module of the programmable logic device to receive the clock output signal respectively; wherein, the number of the functional modules is the same as the number of the clock output signal; The third configuration module is configured to generate a configuration bit stream file, and download the configuration bit stream file to the programmable logic device to configure the programmable logic device, and the configured programmable logic device is used for: receiving a clock input signal, converting the clock input signal into several clock output signals with different phases and outputting them to the functional modules of the programmable logic device respectively. 9. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and operable on the processor, characterized in that, when the processor executes the computer program, the computer program according to claim The steps of the clock configuration method of the programmable logic device described in any one of 1 to 7. 10. A computer-readable storage medium, the computer-readable storage medium stores a computer program, characterized in that, when the computer program is executed by a processor, the programmable Steps of a clock configuration method for a logic device.

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