CN115995510A - Silicon wafer device with gallium oxide nanostructure, preparation method thereof, and semiconductor device - Google Patents

Abstract

The invention relates to a silicon wafer device with a gallium oxide nanostructure, a preparation method thereof, and a semiconductor device. The preparation method includes: providing a silicon wafer, the silicon wafer includes a silicon top layer, a buried oxide layer and a silicon base layer stacked in sequence; etching the silicon wafer, the etching direction is from the silicon top layer to the buried oxide layer vertical direction, a structured composite substrate with grooves is obtained, the grooves include a first groove penetrating through the silicon top layer, and a second groove extending from the first groove to the inside of the buried oxide layer, the second groove The depth of the groove is less than the thickness of the buried oxide layer; chemical vapor deposition is carried out on the structured composite substrate under the environmental conditions of carbon nanomaterials, gallium source and oxygen source, so that the gallium source is deposited and grown in the first groove, and a gallium oxide layer is obtained. Nanostructured Silicon Wafer Devices. The preparation method enables the gallium oxide nanostructure in the silicon wafer device to form an efficient electron transmission channel, and at the same time reduces the generation of a crystalline layer and avoids the transmission of electrons in the crystalline layer.

Description

Silicon wafer device with gallium oxide nanostructure and its preparation method, semiconductor device

technical field

The invention relates to the technical field of nano-device manufacturing, in particular to a silicon wafer device with a gallium oxide nano-structure, a preparation method thereof, and a semiconductor device.

Background technique

Gallium oxide (Ga ₂ O ₃ ) as a new wide bandgap semiconductor material has attracted widespread attention. The Ga ₂ ] ₃ material has a wider forbidden band than the third-generation semiconductor materials represented by gallium nitride (GaN) and silicon carbide (SiC). Through-field strength and radiation resistance, as well as good thermal and chemical stability, and very high transmittance in the visible and ultraviolet regions. Based on these excellent properties, Ga ₂ O ₃ materials have broad application prospects in solar-blind ultraviolet detectors, sensors, light-emitting devices, and high-power devices such as MOSFETs.

Nanomaterials have surface effect, small size effect and quantum size effect, which make them usually exhibit high photoresponsivity and low current, and exhibit excellent performance in light, sound, heat, electricity, magnetism, etc., especially It has broad application prospects in many fields such as catalysis, photoelectric devices, magnetic media and energy. Therefore, Ga ₂ O ₃ nanomaterials have wider potential application prospects in the fields of micro-nano optoelectronic devices, photodetection devices, electronic devices, environment and medicine.

The preparation of Ga ₂ O ₃ nanostructures mainly includes thermal evaporation, hydrothermal method, thermal oxidation method and chemical vapor deposition (CVD). Among them, the CVD method mainly includes metal organic compound chemical vapor deposition (MOCVD) and low pressure chemical vapor deposition. Deposition method (LPCVD). The CVD method is simple and cost-effective, and is the most widely used preparation method for growing Ga ₂ O ₃ nanostructures. However, there is a crystalline layer with a certain thickness between the Ga ₂ O ₃ nanostructure prepared by CVD and the substrate, which will affect the electrical properties of the device prepared by the nanostructure, thereby reducing the impact of the Ga ₂ ] ₃ nanostructure on the device performance. Advantage.

Contents of the invention

Based on this, it is necessary to address the above problems and provide a silicon wafer device with a gallium oxide nanostructure, a preparation method thereof, and a semiconductor device; the preparation method enables the gallium oxide nanostructure to form an efficient electron transport channel in the silicon wafer device , and at the same time reduce the generation of the crystalline layer, thereby effectively avoiding the transmission of electrons in the crystalline layer, which is conducive to obtaining a semiconductor device with excellent performance and high quality.

A method for preparing a silicon wafer device with a gallium oxide nanostructure, comprising the steps of:

providing a silicon wafer, the silicon wafer comprising a silicon top layer, a buried oxide layer and a silicon base layer stacked in sequence;

Etching the silicon wafer, the etching direction is the vertical direction from the silicon top layer to the buried oxide layer, to obtain a structured composite substrate with grooves, wherein the grooves include holes penetrating through the silicon top layer a first groove, and a second groove formed by extending from the first groove to the inside of the buried oxide layer, and the depth of the second groove is less than the thickness of the buried oxide layer;

The structured composite substrate is subjected to chemical vapor deposition under the conditions of carbon nanomaterials, gallium source and oxygen source environment, so that the gallium source is deposited and grown in the first groove, and a gallium oxide nanostructure is obtained. Silicon wafer devices.

In one of the embodiments, the thickness of the silicon top layer is 10nm-50nm;

And/or, the thickness of the buried oxide layer is 30nm-200nm;

And/or, the silicon base layer has a thickness of 500 μm-700 μm.

In one embodiment, the material of the buried oxide layer is selected from at least one of silicon dioxide, aluminum oxide, and quartz.

In one of the embodiments, the size of the carbon nanomaterial is 30nm-100nm;

And/or, the carbon nanomaterial is selected from at least one of nanodiamonds and carbon nanotubes.

In one embodiment, the gallium source is selected from gallium oxide powder.

In one of the embodiments, the flow rate of the oxygen source is 0.5 sccm-3 sccm;

And/or, the oxygen source is selected from oxygen.

In one embodiment, the temperature of the chemical vapor deposition is 900°C-1100°C, and the time is 3min-10min.

A silicon wafer device with a gallium oxide nanostructure prepared by the above-mentioned preparation method, comprising the structured composite substrate, and a gallium oxide nanostructure grown in the first groove, wherein, The gallium oxide nanostructure is composed of overlapping gallium oxide nanomaterials.

In one embodiment, when the gallium oxide nanomaterial is selected from gallium oxide nanowires, the aspect ratio of the gallium oxide nanowires is greater than 10 ⁴ .

A semiconductor device, comprising the above-mentioned silicon wafer device with gallium oxide nanostructure, the main current transmission direction of the semiconductor device is lateral.

According to the preparation method of the present invention, by constructing an insulating patterned structured composite substrate, the rough inner wall of the first groove is used to provide crystallization nuclei, and chemical vapor deposition is used to make gallium oxide nanomaterials on the basis of no catalyst. Nucleation and growth in the first groove, and the structural distribution of gallium oxide nanomaterials are effectively regulated by using carbon nanomaterials as reducing agents, and then on the insulating patterned structured composite substrate, the gallium oxide nanomaterials are overlapped to form nano Junction, forming a connected gallium oxide nanostructure, while retaining the blocking structure formed by the second groove, so that electrons can be efficiently transported only through the gallium oxide nanostructure, and the electron transmission efficiency is significantly improved.

Therefore, on the basis of chemical vapor deposition, this preparation method can construct efficient electron transport channels in silicon wafer devices only through simple and easy-to-operate structural design, while effectively reducing the generation of crystalline layers and eliminating crystallization. layer on the electrical performance of the nanostructure, and then make the semiconductor device prepared based on the silicon wafer device with the gallium oxide nanostructure have excellent electrical performance, and can be widely used in the fields of semiconductor devices such as detectors and sensors.

Description of drawings

1 is a flowchart of a method for preparing a silicon wafer device with a gallium oxide nanostructure in one embodiment of the present invention;

Fig. 2 is the scanning electron micrograph of gallium oxide nanostructure prepared in embodiment 1 of the present invention;

Fig. 3 is the scanning electron micrograph of the nanojunction in the gallium oxide nanostructure prepared in Example 1 of the present invention;

FIG. 4 is a scanning electron microscope image of a gallium oxide nanostructure prepared in Comparative Example 4 of the present invention.

Among them, 10, silicon wafer; 101, silicon top layer; 102, buried oxide layer; 103, silicon base layer; 104, groove; 1041, first groove; 1042, second groove; 20, gallium oxide nano Structure; 201, nanojunction; 202, gallium oxide nanomaterials.

Detailed ways

In order to facilitate the understanding of the present invention, the present invention will be described in more detail below. It should be understood, however, that the present invention may be embodied in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the disclosure of the present invention more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are only for the purpose of describing specific embodiments or examples, and are not intended to limit the present invention. The optional range of the term "and/or" used herein includes any one of two or more related listed items, and also includes any and all combinations of related listed items, any and all of which Combinations include combinations of any two of the related listed items, any more of the related listed items, or all of the related listed items.

As shown in FIG. 1, it is a method for preparing a silicon wafer device with a gallium oxide nanostructure in an embodiment of the present invention, including the following steps:

S1, providing a silicon wafer 10, the silicon wafer 10 includes a silicon top layer 101, a buried oxide layer 102, and a silicon base layer 103 that are sequentially stacked;

S2, etching the silicon wafer 10, the etching direction is the vertical direction from the silicon top layer 101 to the buried oxide layer 102, to obtain a structured composite substrate with grooves 104, wherein the grooves 104 It includes a first groove 1041 penetrating through the silicon top layer, and a second groove 1042 extending from the first groove 1041 to the inside of the buried oxide layer 102, and the depth of the second groove 1042 is less than the thickness of the buried oxide layer 102;

S3, performing chemical vapor deposition on the structured composite substrate under the conditions of carbon nanomaterials, gallium source and oxygen source environment, so that the gallium source is deposited and grown in the first groove 1041 to obtain gallium oxide Silicon wafer device with nanostructures 20 .

Different from the traditional single-layer silicon substrate, in step S1, a silicon wafer 10 with a stacked structure is designed as the substrate, wherein the silicon top layer 101 and the silicon base layer 103 are used as the conductive substrate layer, and the buried oxide layer 102 As an insulating substrate layer, a silicon top layer 101 and a silicon base layer 103 are separated by a buried oxide layer 102 to form a silicon wafer 10 with no vias in the vertical direction.

Optionally, the material of the buried oxide layer 102 is selected from at least one of silicon dioxide, aluminum oxide, and quartz.

In order to facilitate the subsequent construction of an insulating patterned structure and the formation of electron transport channels of nanomaterials, the thickness of the buried oxide layer 102 is 30nm-200nm, preferably 30nm-100nm.

Considering that the silicon base layer 103 in the silicon wafer 10 has a structural support function, if the thickness of the silicon base layer 103 is not enough, it will cause the silicon wafer 10 to easily produce cracks due to stress and strain during the process of growing and preparing the gallium oxide nanostructure 20, or even The silicon wafer 10 will be broken. Preferably, the thickness of the silicon base layer 103 is 500 μm-700 μm.

Preferably, in the silicon wafer 10, the thickness of the silicon top layer 101 is 10nm-50nm, the thickness of the buried oxide layer 102 is 30nm-200nm, and the thickness of the silicon base layer 103 is 500μm- 700 μm.

More preferably, in the silicon wafer 10, the thickness of the silicon top layer 101 is 10nm-50nm, the thickness of the buried oxide layer 102 is 30nm-100nm, and the thickness of the silicon base layer 103 is 500μm -700 μm.

In order to remove residual pollutants on the surface of the silicon wafer 10, the silicon wafer 10 is cleaned, which specifically includes: performing ultrasonic cleaning on the silicon wafer 10 in deionized water, ethanol and deionized water in sequence, and blowing dry with nitrogen.

In order to be applicable to different patterned semiconductor device structures, in step S2, the preparation method of mask etching is preferably used. The specific preparation steps include: masking the surface of the silicon top layer 101 of the cleaned silicon wafer 10, and Etching is carried out under the condition of a mask to form the groove 104, and then the mask is removed by using an organic substance to obtain a structured composite substrate.

Based on the fact that the groove 104 penetrates the silicon top layer 101, the silicon top layer 101 is patterned into a plurality of independent silicon points, and based on the buried oxide layer 102 connecting each silicon point as an insulating substrate layer, each silicon point is mutually Insulation state, which can not only effectively reduce the generation of crystalline layer, but also help to eliminate the influence of inefficient electron transport channels.

It should be noted that the present invention does not specifically limit the etching pattern, and those skilled in the art can choose according to the preparation requirements of the actual semiconductor device structure, and the etching method includes but is not limited to the mask method, and other methods that can realize silicon wafer 10 The method of structured etching is also applicable to the present invention, and the present invention does not list them one by one.

Considering the influence of impurities introduced during the etching process on the electrical properties of the product, it is preferable to perform the structured etching of the silicon wafer 10 in the ultra-clean room yellow light area.

In step S3, compared with the preparation of nanostructures by traditional chemical vapor deposition (CVD), the present invention does not require a catalyst, and only uses a simple and easy-to-operate structural design, using an insulating patterned structured composite substrate, to first The rough inner wall of the groove 1041 provides a crystallization nucleus, and the gallium oxide nanomaterial 202 is nucleated and grown in the first groove 1041 by chemical vapor deposition on the basis of no catalyst, and the oxidation is effectively regulated by using the carbon nanomaterial as a reducing agent. The structural distribution of the gallium nanomaterials 202, and then on the insulating patterned structured composite substrate, the gallium oxide nanomaterials 202 overlap each other in the first groove 1041 to form a nanojunction 201, and/or the first groove The gallium oxide nanomaterials 202 extended from 1041 overlap each other to form a nanojunction 201, forming a connected gallium oxide nanostructure 20, while retaining the blocking structure formed by the second groove, so that electrons only pass through the gallium oxide nanostructure 20 for efficient transport, significantly improving the efficiency of electron transport.

It should be noted that the gallium oxide nanomaterial 202 can be one or more of three-dimensional structures such as nanowires, nanorods, or nanosheets, depending on the amount of carbon nanomaterials, the amount of gallium sources, and other specific adjustments to the preparation conditions. The present invention does not specifically limit this, as long as the gallium oxide nanostructures 20 prepared according to the preparation method provided by the present invention fall within the protection scope of the present invention.

In order to more precisely control the growth of gallium oxide nanomaterials 202 and obtain more efficient electron transport channels, the size of the carbon nanomaterials is preferably 30nm-100nm.

Optionally, the carbon nanomaterial is selected from at least one of nanodiamond and carbon nanotube, preferably nanodiamond.

Considering the safety and convenience of the preparation process, as well as the diversification of the preparation of nanostructures, the gallium source in the present invention is preferably gallium oxide powder.

Optionally, the oxygen source is selected from oxygen, and the flow rate of the oxygen source is 0.5 sccm-3 sccm, preferably 1.5 sccm-2 sccm.

Based on the preparation method of the present invention, no catalyst is needed, and the etched first groove 1041 is used to provide the preparation principle of the crystallization nucleus growth gallium oxide nanomaterial 202. Compared with the preparation conditions of the traditional chemical vapor deposition to prepare nanostructures, the chemical vapor deposition The growth temperature required for deposition is lower, preferably 900°C-1100°C, more preferably 950°C-1000°C, and the time is 3min-10min, preferably 5min-10min.

In one embodiment, the preparation of gallium oxide nanostructures 20 by chemical vapor deposition specifically includes the following steps: put carbon nanomaterials, gallium sources and structured composite substrates into a deposition device, first evacuate the deposition device to vacuum, and preheat ; Then use high-purity argon as a carrier gas to purge to remove air and other impurity gases, and continue to feed argon to fill the deposition device with protective gas, and at the same time adjust the pressure to maintain it at a certain constant value; from preheating The temperature is continuously raised, and oxygen is introduced when the growth temperature reaches the critical value, and the growth temperature is maintained at a constant temperature of 900°C-1100°C for 3min-10min. After the growth is completed, the temperature is lowered, and a silicon wafer with a gallium oxide nanostructure 20 is obtained. device.

Therefore, the preparation method provided by the present invention is simple in process and low in cost, can construct an efficient electron transmission channel in a silicon wafer device, effectively reduce the generation of a crystalline layer, and eliminate the influence of the crystalline layer on the electrical properties of the nanostructure, so that it has The silicon wafer device of the gallium oxide nanostructure 20 has excellent electrical properties.

It should be noted that when the thickness of the silicon top layer 101 is 0, that is, the silicon wafer 10 only includes the buried oxide layer 102 and the silicon base layer 103 stacked in sequence, when the gallium oxide nanostructure 20 is prepared, the generation of the crystalline layer only affects Nanostructure growth time without compromising the generation of efficient electron transport channels. By delaying the preparation time to a certain extent, the prepared gallium oxide nanostructure 20 can also provide an efficient electron transport channel and avoid electron transport in the crystal layer.

The present invention also provides a silicon wafer device with a gallium oxide nanostructure 20 prepared by the above-mentioned preparation method, the silicon wafer device includes the structured composite substrate, and is grown on the first Gallium oxide nanostructures 20 in the groove 1041 , wherein the gallium oxide nanostructures 20 are formed by overlapping gallium oxide nanomaterials 202 .

Wherein, gallium oxide nanomaterials 202 overlap each other to form a nanojunction 201 , and the gallium oxide nanostructure 20 has at least one nanojunction 201 .

It should be noted that all the gallium oxide nanostructures 20 formed in the first groove 1041 may be located in the same horizontal direction, or may be uneven and located in different horizontal directions. When all the gallium oxide nanostructures 20 formed in the first groove 1041 are located in the same horizontal direction, the electron transmission efficiency is better.

In one embodiment, when the gallium oxide nanomaterial 202 is preferably a gallium oxide nanowire, the diameter of the gallium oxide nanowire can reach tens of nanometers, and the length can reach the order of microns, that is, the gallium oxide nanowire The aspect ratio is greater than 10 ⁴ , and the aspect ratio advantage can meet the structural requirements of the gallium oxide nanomaterial 202 in semiconductor devices.

The present invention also provides a semiconductor device, which includes the silicon wafer device with gallium oxide nanostructures 20 as described above, and the main current transmission direction of the semiconductor device is lateral.

The semiconductor device has excellent electrical performance, can meet the performance requirements of various electronic devices such as micro-nano optoelectronic devices, photodetector devices, etc., and has a wider application range and stronger adaptability.

Hereinafter, the silicon wafer device with gallium oxide nanostructure, its preparation method, and semiconductor device will be further described through the following specific examples.

Example 1

Select a silicon wafer, which includes a silicon top layer, a silicon dioxide layer, and a silicon base layer stacked in sequence, wherein the thickness of the silicon top layer is 30nm, the thickness of the silicon dioxide layer is 50nm, and the thickness of the silicon base layer is 500 μm. Silicon wafers were ultrasonically cleaned in deionized water, ethanol and deionized water in sequence to remove residual contaminants on the surface, and dried with nitrogen gas.

In the ultra-clean room yellow light area, a mask is attached to the silicon top layer surface of the cleaned silicon wafer for photoetching. The vertical depth of the etching is 50nm, and then the mask is removed by using organic matter to obtain a structured composite lining. end.

Put the nano-diamond (30nm), gallium oxide powder (99.8%) and the structured composite substrate into the tube furnace, first evacuate the tube furnace to a vacuum, and preheat it. Then high-purity argon is used as carrier gas to purge to remove air and other impurity gases, and argon gas with a flow rate of 100 sccm is continuously introduced to fill the deposition device with protective gas, while adjusting the pressure to maintain it at a certain constant value. Continue to heat up from the preheating temperature, and when it reaches the critical value of 960°C, introduce oxygen with a flow rate of 1.5 sccm, keep the constant temperature at 960°C for 10 minutes, and cool down to room temperature after the growth is completed, and obtain a silicon wafer with a gallium oxide nanostructure device.

It can be concluded from the photoelectric test after preparing the electrodes that the current of the silicon wafer device is four times that of the unstructured silicon wafer device of Comparative Example 1.

It can be seen from FIG. 2 that the gallium oxide nanomaterial is a nanowire with a diameter of about 50 nm and a length of up to hundreds of microns. And according to the further partially enlarged FIG. 3 , it can be seen that the nanowires are stacked and staggered to form multiple nanojunctions.

Example 2

Select a silicon wafer, which includes a silicon top layer, a silicon dioxide layer, and a silicon base layer stacked in sequence, wherein the thickness of the silicon top layer is 30nm, the thickness of the silicon dioxide layer is 50nm, and the thickness of the silicon base layer is 450 μm. Silicon wafers were ultrasonically cleaned in deionized water, ethanol and deionized water in sequence to remove residual contaminants on the surface, and dried with nitrogen gas.

In the ultra-clean room yellow light area, a mask is attached to the silicon top layer surface of the cleaned silicon wafer for photoetching. The vertical depth of the etching is 50nm, and then the mask is removed by using organic matter to obtain a structured composite lining. end.

Put the nano-diamond (45nm), gallium oxide powder (99.8%) and the structured composite substrate into the tube furnace, first evacuate the tube furnace to vacuum, and preheat it. Then high-purity argon is used as carrier gas to purge to remove air and other impurity gases, and argon gas with a flow rate of 100 sccm is continuously introduced to fill the deposition device with protective gas, while adjusting the pressure to maintain it at a certain constant value. Continue to heat up from the preheating temperature, and when it reaches the critical value of 1000°C, flow in oxygen with a flow rate of 1.2 sccm, keep the constant temperature at 1000°C for 8 minutes, and cool down to room temperature after the growth is completed, and obtain a silicon wafer with a gallium oxide nanostructure device.

Example 3

A silicon wafer is selected, and the silicon wafer includes a silicon top layer, an aluminum oxide layer, and a silicon base layer stacked in sequence, wherein the thickness of the silicon top layer is 30 nm, the thickness of the aluminum oxide layer is 250 nm, and the thickness of the silicon base layer is 500 μm . Silicon wafers were ultrasonically cleaned in deionized water, ethanol and deionized water in sequence to remove residual contaminants on the surface, and dried with nitrogen gas.

In the ultra-clean room yellow light area, a mask is attached to the surface of the silicon top layer of the cleaned silicon wafer for photoetching. The vertical depth of the etching is 100nm, and then the mask is removed by organic matter to obtain a structured composite lining. end.

Put the nano-diamond (60nm), gallium oxide powder (99.8%) and the structured composite substrate into the tube furnace, first evacuate the tube furnace to a vacuum, and preheat it. Then high-purity argon is used as carrier gas to purge to remove air and other impurity gases, and argon gas with a flow rate of 100 sccm is continuously introduced to fill the deposition device with protective gas, while adjusting the pressure to maintain it at a certain constant value. Continue to heat up from the preheating temperature, and when it reaches the critical value of 960°C, introduce oxygen with a flow rate of 1.5 sccm, keep the constant temperature at 960°C for 10 minutes, and cool down to room temperature after the growth is completed, and obtain a silicon wafer with a gallium oxide nanostructure device.

Example 4

Select a silicon wafer, which includes a silicon top layer, a silicon dioxide layer, and a silicon base layer stacked in sequence, wherein the thickness of the silicon top layer is 100 nm, the thickness of the silicon dioxide layer is 100 nm, and the thickness of the silicon base layer is 500 μm. Silicon wafers were ultrasonically cleaned in deionized water, ethanol and deionized water in sequence to remove residual contaminants on the surface, and dried with nitrogen gas.

In the ultra-clean room yellow light area, a mask is attached to the silicon top layer surface of the cleaned silicon wafer for photoetching, and the vertical depth of the etching is 150nm, and then organic matter is used to remove the mask to obtain a structured composite lining end.

Put the nano-diamond (75nm), gallium oxide powder (99.8%) and the structured composite substrate into the tube furnace, firstly evacuate the tube furnace to a vacuum, and preheat it. Then high-purity argon is used as carrier gas to purge to remove air and other impurity gases, and argon gas with a flow rate of 100 sccm is continuously introduced to fill the deposition device with protective gas, while adjusting the pressure to maintain it at a certain constant value. Continue to heat up from the preheating temperature, and when the critical value of 980°C is reached, the flow rate of 1.6 sccm of oxygen is introduced, and the temperature is maintained at 980°C for 10 minutes, and after the growth is completed, the temperature is lowered to room temperature, and a silicon wafer with a gallium oxide nanostructure is obtained. device.

Example 5

A silicon wafer is selected, and the silicon wafer includes a silicon top layer, a silicon dioxide layer, and a silicon base layer stacked in sequence, wherein the thickness of the silicon top layer is 100 nm, the thickness of the silicon dioxide layer is 300 nm, and the thickness of the silicon base layer is is 450 μm. Silicon wafers were ultrasonically cleaned in deionized water, ethanol and deionized water in sequence to remove residual contaminants on the surface, and dried with nitrogen gas.

In the ultra-clean room yellow light area, a mask is attached to the silicon top layer surface of the cleaned silicon wafer for photoetching, and the vertical depth of the etching is 150nm, and then organic matter is used to remove the mask to obtain a structured composite lining end.

Put the nano-diamond (100nm), gallium oxide powder (99.8%) and the structured composite substrate into the tube furnace. Firstly, the tube furnace is evacuated and preheated. Then high-purity argon is used as carrier gas to purge to remove air and other impurity gases, and argon gas with a flow rate of 100 sccm is continuously introduced to fill the deposition device with protective gas, while adjusting the pressure to maintain it at a certain constant value. Continue to heat up from the preheating temperature, and when it reaches the critical value of 960°C, introduce oxygen with a flow rate of 1.5 sccm, keep the constant temperature at 960°C for 10 minutes, and cool down to room temperature after the growth is completed, and obtain a silicon wafer with a gallium oxide nanostructure device.

Comparative example 1

Select a silicon wafer, which includes a silicon top layer, a silicon dioxide layer, and a silicon base layer stacked in sequence, wherein the thickness of the silicon top layer is 30nm, the thickness of the silicon dioxide layer is 50nm, and the thickness of the silicon base layer is 500 μm. Silicon wafers were ultrasonically cleaned in deionized water, ethanol and deionized water in sequence to remove residual contaminants on the surface, and dried with nitrogen gas.

Put nano-diamond (30nm), gallium oxide powder (99.8%), metal Au catalyst and structured composite substrate into a tube furnace, and first evacuate the tube furnace to a vacuum and preheat it. Then high-purity argon is used as carrier gas to purge to remove air and other impurity gases, and argon gas with a flow rate of 100 sccm is continuously introduced to fill the deposition device with protective gas, while adjusting the pressure to maintain it at a certain constant value. Continue to heat up from the preheating temperature, and when it reaches the critical value of 1100°C, flow in oxygen with a flow rate of 1.5 sccm, keep the constant temperature at 1100°C for 10 minutes, and cool down to room temperature after the growth is completed, to obtain silicon crystals with gallium oxide nanostructures on the surface round device.

Comparative example 2

The only difference between Comparative Example 2 and Example 1 is that the vertical depth of etching is 10 nm.

Because the etching depth is too small, the etched groove cannot penetrate the top layer of silicon, and the nanomaterials are connected through the top layer of conductive silicon, so that the nanostructures are connected to each other, and electrons are preferentially transmitted through the top layer of silicon, which cannot be fully utilized. The unique advantages of nanomaterials, and in the process of preparing gallium oxide nanostructures, based on the material growth mechanism, more crystalline layers are generated between the nanostructures and the silicon top layer, which hinders the electron transport channel and reduces the conductivity efficiency. The resulting silicon wafer devices with gallium oxide nanostructures had poor electrical properties.

Comparative example 3

The only difference between Comparative Example 3 and Example 1 is that the vertical depth of etching is 100 nm.

Because the etching depth is too large, the etched grooves pass through the silicon top layer and the silicon dioxide layer in turn, and extend into the silicon base layer. The silicon dioxide layer makes each silicon point insulated from each other, but in the preparation In the process of gallium oxide nanostructure, nanomaterials need a longer growth time to reach the length across the blocking structure and form nanojunction conductive channels, but too long nanomaterials will reduce the electron transport efficiency, which is not conducive to the formation of efficient electrons. Transmission channels, and thus the prepared silicon wafer devices with gallium oxide nanostructures have poor electrical properties.

Comparative example 4

The only difference between Comparative Example 4 and Example 1 is that diamond powder (1 μm) is used as the reducing agent.

Due to the large size of the reducing agent, the precise control of the gallium oxide material cannot be realized. It can be seen from Figure 4 that the prepared gallium oxide material is a nano-short rod with a large diameter, which loses the advantage of the high specific surface area of the nanostructure, so it has Silicon wafer devices with a gallium oxide structure have poor electrical performance.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (10)

1. A method for preparing a silicon wafer device with a gallium oxide nanostructure, the method comprising the steps of:

providing a silicon wafer, wherein the silicon wafer comprises a silicon top layer, a buried oxide layer and a silicon bottom layer which are sequentially stacked;

etching the silicon wafer, wherein the etching direction is the vertical direction from the silicon top layer to the buried oxide layer, and a structured composite substrate with grooves is obtained, the grooves comprise first grooves penetrating through the silicon top layer and second grooves formed by extending from the first grooves to the inside of the buried oxide layer, and the depth of the second grooves is smaller than the thickness of the buried oxide layer;

and carrying out chemical vapor deposition on the structured composite substrate under the conditions of a carbon nanomaterial, a gallium source and an oxygen source environment, so that the gallium source is deposited and grown in the first groove, and a silicon wafer device with a gallium oxide nanostructure is obtained.

2. The method of fabricating a silicon wafer device having a gallium oxide nanostructure according to claim 1, wherein the thickness of the silicon top layer is 10nm to 50nm;

and/or the thickness of the buried oxide layer is 30nm-200nm;

and/or the thickness of the silicon substrate layer is 500-700 mu m.

3. The method for manufacturing a silicon wafer device having a gallium oxide nanostructure according to claim 1, wherein the buried oxide layer is made of at least one material selected from the group consisting of silicon dioxide, aluminum oxide, and quartz.

4. The method for manufacturing a silicon wafer device having a gallium oxide nanostructure according to claim 1, wherein the carbon nanomaterial has a size of 30nm to 100nm:

and/or the carbon nanomaterial is selected from at least one of nano diamond and carbon nano tube.

5. The method of fabricating a silicon wafer device having gallium oxide nanostructures of claim 1, wherein the gallium source is selected from gallium oxide powders.

6. The method of fabricating a silicon wafer device with gallium oxide nanostructures of claim 1, wherein the oxygen source flow is 0.5sccm to 3sccm;

and/or the oxygen source is selected from oxygen.

7. The method for fabricating a gallium oxide nanostructured silicon wafer device according to claim 1, wherein the chemical vapor deposition is performed at a temperature of 900 ℃ to 1100 ℃ for a time of 3min to 10min.

8. A gallium oxide nanostructured silicon wafer device produced by the production method according to any one of claims 1 to 7, wherein the gallium oxide nanostructured silicon wafer device comprises the structured composite substrate and gallium oxide nanostructures grown in the first grooves, wherein the gallium oxide nanostructures are formed of gallium oxide nanomaterial overlapping each other.

9. The silicon wafer device with gallium oxide nanostructures of claim 8, wherein when the gallium oxide nanomaterial is selected from gallium oxide nanowires, the aspect ratio of the gallium oxide nanowires is greater than 10 ⁴ 。

10. A semiconductor device, wherein the semiconductor device comprises the silicon wafer device with gallium oxide nano-structure according to claim 8 or 9, and the main current transmission direction of the semiconductor device is transverse.

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