CN115985863A - Integrated circuit package product - Google Patents

Abstract

An integrated circuit package product. The integrated circuit package product comprises: a carrier, a connection layer and a lid. The connecting layer is formed on the carrier plate. The cap is formed over the connection layer. The space enclosed by the lid and the carrier is configured to accommodate an integrated circuit die. The connection layer includes a passage that penetrates the connection layer and communicates with the space.

Description

IC packaging products

technical field

This application is related to the field of semiconductors, in detail, it is related to an integrated circuit packaging product.

Background technique

In the prior art, integrated circuit packaged products (such as but not limited to flip-chip ball grid array products) lack heat dissipation design, so that the operating efficiency of integrated circuit packaged products is easily reduced due to overheating during operation.

Contents of the invention

In view of this, the present application proposes an integrated circuit packaging product to solve the above problems.

According to an embodiment of the present application, an integrated circuit packaging product is provided. The integrated circuit packaging product includes: a carrier board, a connecting layer and a cover. The connection layer is formed on the carrier board. The cover is formed on the connection layer. A space enclosed by the cover and the carrier is configured to accommodate an integrated circuit chip. The connecting layer includes a channel passing through the connecting layer and communicating with the space.

According to an embodiment of the present application, the connecting layer includes an adhesive layer. The cover is bonded on the carrier board through the adhesive layer.

According to an embodiment of the present application, the connection layer includes an insulating member. The insulator is disposed between the carrier board and the cover.

According to an embodiment of the present application, the number of the channels is one or more.

According to an embodiment of the present application, the distribution of the plurality of channels on the carrier plate is symmetrical.

According to an embodiment of the present application, the width of the channel is in the range of 2-3 mm.

According to an embodiment of the present application, the height of the channel is in the range of 2-40 microns.

According to an embodiment of the present application, the integrated circuit chip is connected to the top surface of the carrier board through a conductor connector.

According to an embodiment of the present application, the cover is bonded to the top surface of the integrated circuit chip by thermal interface adhesive.

According to an embodiment of the present application, the integrated circuit package product further includes a heat sink. The heat sink is bonded to the top surface of the cover.

The integrated circuit packaging product proposed by this application is provided with a channel as an exhaust channel between the cover and the carrier, so that the inner space and the outer space covered by the cover and the carrier can generate heat exchange, thereby increasing the integrated circuit package. Product cooling efficiency.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present application, and constitute a part of the description, together with the following specific embodiments, are used to explain the present application, but do not constitute a limitation to the present application. In the attached picture:

FIG. 1 illustrates a schematic block diagram of an integrated circuit package product according to an embodiment of the present application.

FIG. 2 illustrates a cross-sectional view of an integrated circuit package product according to an embodiment of the present application.

FIG. 3A illustrates a top view of distribution of connection layers on a carrier according to an embodiment of the present application.

FIG. 3B illustrates a side view of the distribution of connection layers on a carrier according to an embodiment of the present application.

FIG. 4A illustrates a top view of the distribution of connection layers on a carrier according to another embodiment of the present application.

FIG. 4B illustrates a top view of the distribution of connection layers on the carrier according to another embodiment of the present application.

FIG. 5 illustrates a cross-sectional view of an integrated circuit package product according to an embodiment of the present application.

Detailed ways

The following disclosure provides various implementations or illustrations, which can be used to achieve different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. It will be appreciated that these descriptions are merely examples and are not intended to limit the disclosure. For example, in the description below, forming a first feature on or over a second feature may include some embodiments wherein the first and second features are in direct contact with each other; and may also include In some embodiments, additional components are formed between the first and second features, such that the first and second features may not be in direct contact. In addition, this disclosure may reuse reference symbols and/or labels in various embodiments. Such repetition is for the sake of brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.

Furthermore, the use of spatially relative terms such as "below", "below", "below", "above", "above" and the like here may be for the convenience of explaining the The relationship between one component or feature shown with respect to another or more components or features. These spatially relative terms are intended to cover various orientations of the device during use or operation in addition to the orientation depicted in the drawings. The device may be otherwise positioned (eg, rotated 90 degrees or at other orientations) and these spatially relative descriptors should be construed accordingly.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the application are approximations, the relative numerical values set forth in the specific examples are reported here as precisely as possible. Any numerical value, however, inherently inherently contain standard deviations resulting from their individual testing methodology. As used herein, "about" generally means that the actual value is within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the term "about" means that the actual value falls within an acceptable standard error of the mean, as considered by one of ordinary skill in the art to which this application pertains. It should be understood that, except for the experimental examples, or unless otherwise clearly stated, all ranges, quantities, numerical values and percentages used herein (for example, to describe the amount of material used, the length of time, temperature, operating conditions, ratios of quantities and others) similar) are modified by "about". Therefore, unless otherwise stated to the contrary, the numerical parameters disclosed in the specification and the appended claims are approximate values and may be changed as required. At least these numerical parameters should be understood as the value obtained by applying the normal rounding method to the indicated effective digits. Herein, numerical ranges are expressed as being from one endpoint to another endpoint or between two endpoints; unless otherwise stated, the numerical ranges stated herein are inclusive of the endpoints.

FIG. 1 illustrates a schematic block diagram of an integrated circuit package product 1 according to an embodiment of the present application. In some embodiments, the integrated circuit package product 1 may be a flip-chip ball grid array product. In some embodiments, the integrated circuit package product 1 includes a carrier 10 , a connection layer 11 and a cover 12 . In some embodiments, the connection layer 11 is formed on the carrier 10 . In some embodiments, the cover 12 is formed on the connection layer 11 . In some embodiments, the space enclosed by the cover 12 and the carrier 10 is configured to accommodate an integrated circuit chip. In some embodiments, the connecting layer 11 includes a channel passing through the connecting layer 11 and communicating with the space.

FIG. 2 illustrates a cross-sectional view of an integrated circuit package product 2 according to an embodiment of the present application. In some embodiments, integrated circuit package product 2 may be a flip-chip ball grid array product. In some embodiments, the integrated circuit packaged product 2 can be used to implement the integrated circuit packaged product 1 in the embodiment of FIG. 1 . In some embodiments, the integrated circuit package product 2 includes a carrier 20 , a connection layer 21 and a cover 22 .

In some embodiments, the carrier board 20 includes elements such as a substrate, a lead frame, and a PCB board. In some embodiments, the connection layer 21 is formed on the carrier 20 . In some embodiments, the connection layer 21 includes an adhesive layer. In some embodiments, the glue layer is an AD glue. In some embodiments, the cover 22 is formed on the connection layer 21 . In some embodiments, the cover 22 is bonded on the carrier 20 through the adhesive layer. In some embodiments, cover 22 is a metal cover. In some embodiments, the space A22 enclosed by the cover 22 and the carrier 20 is configured to accommodate the integrated circuit chip 23 .

In some embodiments, the cover 22 is bonded to the top surface of the integrated circuit chip 23 by a thermal interface glue G23. In some embodiments, the integrated circuit chip 23 is electrically connected to the carrier board 20 . In some embodiments, the integrated circuit chip 23 is connected to the top surface of the carrier board 20 through the conductor connection P23. In some embodiments, the conductor connector P23 may be a solder ball. In some embodiments, an underfill T23 may be included between the integrated circuit chip 23 and the carrier 20 , and the underfill T23 encapsulates the conductor connector P23 therein.

Referring to FIG. 2, FIG. 3A and FIG. 3B at the same time, FIG. 3A demonstrates a top view of the distribution of the connection layer 21 on the carrier board 20 according to an embodiment of the present application, and FIG. 3B demonstrates a top view of the distribution of the connection layer 21 on the carrier board according to an embodiment of the present application. Distribution side view on 20. In some embodiments, the connection layer 21 includes a channel C21 passing through the connection layer 21 and communicating with the space A22. In some embodiments, the channel C21 is configured as an exhaust channel, so that the space A22 can exchange heat with the external space, thereby increasing the heat dissipation efficiency of the integrated circuit package product 2 .

In some embodiments, the width WC21 of the channel C21 is in the range of 2-3 millimeters. In some embodiments, the height HC21 of the channel C21 is in the range of 20-40 microns. In some embodiments, the number of channels C21 may be one or more. In some embodiments, the channels C21 are distributed symmetrically on the carrier board 20 to increase heat dissipation efficiency. As shown in FIG. 3A , there are two channels C21 on the carrier board 20 , and the two channels C21 are respectively located on the left and right sides of the carrier board 20 . Under such setting, it is beneficial to air convection and increases heat dissipation efficiency.

However, the number and distribution of the channels C21 are not limited to those shown in FIG. 3A . Referring to FIG. 4A , FIG. 4A illustrates a top view of the distribution of the connection layer 21 on the carrier 20 according to another embodiment of the present application. As shown in FIG. 4A , the number of channels C21 on the carrier board 20 is four. As shown in FIG. 4A , the four channels C21 on the carrier board 20 are respectively located on four sides of the carrier board 20 . Under such setting, it is beneficial to increase the air intake and heat dissipation efficiency.

Those skilled in the art should be able to understand that the number and distribution of the channels C21 can be adjusted according to actual needs, as long as a channel that penetrates the connecting layer 21 and communicates with the space A22 can be provided in the connecting layer 21 between the carrier board 20 and the cover 22 The use of C21 to increase heat dissipation efficiency should belong to the scope of this application.

In some embodiments, the distribution of the channels C21 can be adjusted according to the quantity and distribution of the integrated circuit chips 23 in the inner space A22. Referring to FIG. 4B , FIG. 4B illustrates a top view of the distribution of the connection layer 21 on the carrier 20 according to another embodiment of the present application. As shown in Figure 4B, the inner space A22 accommodates a plurality of integrated circuit chips 23, wherein one side of the carrier plate 20 is provided with more (3 as shown) integrated circuit chips 23, and the other side of the carrier plate 20 A small number (one as shown) of integrated circuit chips 23 are provided. Since more integrated circuit chips 23 will generate more heat energy, more channels C21 (two as shown) can be provided on the side close to more integrated circuit chips 23 to increase heat dissipation efficiency.

Although in the above embodiments, the distribution of the connecting layers 21 is roughly rectangular. However, depending on the contact surface between the cover 22 and the carrier 20 , the distribution of the connecting layer 21 may also have different shapes. For example, the cover 22 may be a hemispherical cover, therefore, the contact surface between the cover 22 and the carrier 20 will be circular. Under such setting, the distribution of the connection layer 21 can be roughly circular, and as long as the channels C21 are left between the circumferences, the purpose of increasing heat dissipation efficiency can be achieved.

The manufacturing process of the integrated circuit packaging product 2 is generally described as follows: firstly, the integrated circuit chip 23 is placed on the carrier board 20 , and the carrier board 20 and the integrated circuit chip 23 are connected by the conductor connector P23 . Next, the thermal interface glue G23 is coated on the top surface of the integrated circuit chip 23 . Next, a connection layer 21 is formed on the carrier 20 . When the connection layer 21 is formed with an AD glue layer, the AD glue layer is coated on the carrier plate 20 by a machine, and when the AD glue layer is coated, intermittent glue is used, thereby leaving a gap between the AD glue layers, The channel C21 is thereby formed. Finally, cover the cover 22 so that the cover 22 is formed on the connecting layer 21 and bonded to the top surface of the integrated circuit chip 23 through the thermal interface adhesive G23 at the same time.

In the above embodiments, the connecting layer 21 may be formed by an AD adhesive layer. However, this is not a limitation of the present application. In other embodiments, the connection layer 21 may be an insulating member formed on the carrier 20 . The cover member 22 is formed on the insulating member, and is bonded to the top surface of the integrated circuit chip 23 by the thermal interface glue G23 at the same time. By changing the shape of the insulator, a channel C21 can be left in the insulator to increase heat dissipation efficiency.

FIG. 5 illustrates a cross-sectional view of an integrated circuit package product 3 according to an embodiment of the present application. In some embodiments, the integrated circuit package product 3 may be a flip-chip ball grid array product. In some embodiments, the integrated circuit packaged product 3 can be used to implement the integrated circuit packaged product 1 in the embodiment of FIG. 1 . In some embodiments, the integrated circuit packaged product 3 is substantially the same as the integrated circuit packaged product 2 , the only difference being that the integrated circuit packaged product 3 additionally includes a heat sink 31 and a circuit board 32 . Therefore, the same parts of the integrated circuit package product 3 and the integrated circuit package product 2 are omitted here to save space.

In some embodiments, the heat sink 31 is bonded to the top surface of the cover 22 . In some embodiments, the heat sink 31 is welded on the circuit board 32 through the copper pin P31. In some embodiments, the circuit board 32 is electrically connected to the bottom surface of the carrier board 20 . In some embodiments, the circuit board 32 is connected to the bottom surface of the carrier board 20 through conductive connectors (such as solder balls). The integrated circuit package product 3 accelerates heat dissipation by adding a heat sink 31 on the cover 22 .

As used herein, the terms "approximately," "substantially," "substantially," and "about" are used to describe and take into account small variations. When used in connection with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs exactly as well as instances in which the event or circumstance occurs in close proximity. As used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to the other or as between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified. The term "substantially coplanar" may refer to two surfaces that are positioned along the same plane within a few micrometers (μm), eg, within 10 μm, within 5 μm, within 1 μm, or within 0.5 μm of being positioned along the same plane. When referring to "substantially" the same numerical value or characteristic, the term may refer to a value that is within ±10%, ±5%, ±1%, or ±0.5% of the mean value of the stated value.

As used herein, the terms "approximately," "substantially," "substantially," and "about" are used to describe and account for minor variations. When used in connection with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs exactly as well as instances in which the event or circumstance occurs in close proximity. For example, when used in conjunction with a numerical value, the term may refer to a variation of less than or equal to ±10% of the stated numerical value, for example, less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3% , less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values is less than or equal to ±10% of the mean of the stated values (e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values can be considered "substantially" or " About" is the same. For example, "substantially" parallel may refer to an angular range of less than or equal to ±10° relative to 0°, for example, less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, Less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, "substantially" perpendicular may refer to an angular range of less than or equal to ±10° relative to 90°, for example, less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, Less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

For example, two surfaces may be considered coplanar or substantially coplanar if the displacement between them is 5 μm or less, 2 μm or less, 1 μm or less, or 0.5 μm or less . A surface may be considered planar or substantially planar if the displacement between any two points on the surface relative to the plane is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm .

As used herein, the terms "conductive", "electrically conductive" and "electrical conductivity" refer to the ability to transfer electric current. Conductive materials generally indicate those materials that offer little or no resistance to the flow of electrical current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, a conductive material is one that has an electrical conductivity greater than approximately 104 S/m (eg, at least 105 S/m or at least 106 S/m). The electrical conductivity of a material can sometimes vary with temperature. Conductivity of materials is measured at room temperature unless otherwise specified.

As used herein, the singular terms "a" and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided "on" or "over" another component may encompass situations where the former component is directly on (eg, in physical contact with) the latter component, and one or more The case where an intermediate component is located between the previous component and the next component.

As used herein, spatial relative terms such as "below", "below", "lower", "above", "upper", "lower", "left side", "right side" may be used herein for ease of description. ” and the like describe the relationship of one component or feature to another component or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will be understood that when a component is referred to as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component or intervening components may be present.

The foregoing summarizes features of several embodiments and details of the disclosure. The embodiments described in this disclosure may be readily used as a basis for designing or modifying other processes and structures for performing the same or similar purposes and/or obtaining the same or similar advantages of the embodiments incorporated herein. These equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and alterations may be made without departing from the spirit and scope of the present disclosure.

Claims (10)

1. An integrated circuit package product, comprising:

a carrier plate;

the connecting layer is formed on the carrier plate;

a lid formed over the connection layer, a space enclosed by the lid and the carrier configured to receive an integrated circuit die;

wherein the connection layer includes a channel that penetrates the connection layer and communicates with the space.

2. The ic package product of claim 1, wherein the connection layer comprises a glue layer, and the lid is adhered to the carrier by the glue layer.

3. The integrated circuit package product of claim 1, wherein the connection layer comprises an insulator disposed between the carrier and the lid.

4. The integrated circuit package product of claim 1, wherein the number of vias is one or more.

5. The integrated circuit package product of claim 4, wherein the plurality of vias are distributed symmetrically on the carrier.

6. The integrated circuit package product of claim 1, wherein the width of the channel is in the range of 2-3 millimeters.

7. The integrated circuit package product of claim 1, wherein the height of the via is in the range of 20-40 microns.

8. The integrated circuit package product of claim 1, wherein the integrated circuit die is connected to the top surface of the carrier board by conductor connections.

9. The integrated circuit package product of claim 1, wherein the lid is bonded to the top surface of the integrated circuit die by a thermal interface adhesive.

10. The integrated circuit package product of claim 1, further comprising:

and the radiating fin is adhered to the top surface of the cover piece.

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