CN115952084A

CN115952084A - Method and system for verifying access component

Info

Publication number: CN115952084A
Application number: CN202211615838.2A
Authority: CN
Inventors: 袁媛; 高军; 刘晓燕; 游柏青; 赖彬
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2022-12-15
Filing date: 2022-12-15
Publication date: 2023-04-11

Abstract

The application provides a method and a system for verifying a memory access component, wherein the method comprises the following steps: running a test case to acquire a target virtual address to be converted from the memory access component; converting the target virtual address into a corresponding target physical address according to pre-established mapping relationship information, wherein the mapping relationship information is used for recording the one-to-one mapping relationship between the virtual address and the physical address of the memory; generating a memory access result according to the target physical address; and verifying the memory access component according to the memory access result. According to the embodiment of the application, the virtual address and the physical address in the memory verification process can be converted through one-time query according to the one-to-one mapping relation of the virtual address and the physical address in the memory, and the conversion efficiency of the virtual address and the physical address in the verification process is improved.

Description

Method and system for verifying access component

Technical Field

The present application relates to the field of computers, and more particularly, to a method and system for verifying a memory access component.

Background

The memory access component serves as a bridge for exchanging data with external storage in the processor core, and the functional correctness of the memory access component plays a significant role in the stability of the whole processor system.

At present, in order to improve performance, a concept of a virtual memory is introduced into a main stream processor, and therefore, in a verification process of a memory access component, conversion between a virtual address and a physical address is often required. If the memory access component is verified according to the current paging mechanism common to the virtual memory, the conversion efficiency of the virtual address and the physical address is low, thereby affecting the verification efficiency of the memory access component.

Disclosure of Invention

The application provides a method and a system for verifying a memory access component. Various aspects of embodiments of the present application are described below.

In a first aspect, a method for authenticating a memory access component is provided, the method comprising: running a test case to acquire a target virtual address to be converted from the memory access component; converting the target virtual address into a corresponding target physical address according to pre-established mapping relationship information, wherein the mapping relationship information is used for recording a one-to-one mapping relationship between the virtual address and the physical address of the memory; generating a memory access result according to the target physical address; and verifying the memory access component according to the memory access result.

As a possible implementation manner, the virtual address recorded in the mapping relationship information is a virtual address associated with the test case.

As a possible implementation manner, the converting the target virtual address into a corresponding target physical address according to the pre-established mapping relationship information includes: and inquiring the mapping relation information by using the target virtual address as an index and utilizing a search function to obtain the target physical address.

As a possible implementation manner, the mapping relationship information is further used to record attribute information and valid identification bits corresponding to the virtual address in the memory.

As a possible implementation manner, the attribute information includes one or more of the following: cacheability of a virtual address, shareability of a virtual address, security state of a virtual address.

In a second aspect, a system for verifying a memory access component is provided, the system comprising: the test case generator is used for generating a test case; the memory access component to be verified is used for generating a target virtual address to be converted according to the test case; the virtual memory model is used for acquiring the target virtual address and converting the target virtual address into a corresponding target physical address according to pre-established mapping relation information, wherein the mapping relation information is used for recording the one-to-one mapping relation between the virtual address and the physical address of the memory; the memory access component to be verified is also used for generating a memory access result according to the target physical address; and the result checking module is used for verifying the memory access component according to the memory access result.

As a possible implementation, the virtual memory model is configured to: and inquiring the mapping relation information by using the target virtual address as an index and utilizing a search function to obtain the target physical address.

According to the embodiment of the application, the virtual address and the physical address in the memory verification process can be converted through one-time query according to the one-to-one mapping relation of the virtual address and the physical address in the memory, and the conversion efficiency of the virtual address and the physical address in the verification process is improved.

Drawings

Fig. 1 is a schematic structural diagram of a general verification platform according to an embodiment of the present application.

Fig. 2 is a schematic flowchart of a method for verifying a memory access component according to an embodiment of the present application.

Fig. 3 is a schematic structural diagram of a virtual memory model according to an embodiment of the present disclosure.

Fig. 4 is a schematic diagram of a virtual-real address mapping table according to an embodiment of the present disclosure.

Fig. 5 is a schematic structural diagram of a system for verifying a memory access component according to an embodiment of the present application.

Fig. 6 is a schematic system structure diagram of another memory access verification component according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments.

Modern general processors are processors of a load/store architecture, access to a memory is realized mainly through load and store instructions, so that a memory access component for executing the load and store instructions plays a role of a bridge for exchanging data with external memory in a processor core, and the functional correctness of the memory access component plays a crucial role in the stability of the whole processor system.

In order to ensure the correctness of the function of the memory access component, the memory access component is usually verified. Fig. 1 is a schematic structural diagram of a general authentication platform. The verification platform 100 may include a test case generator 110, a driver 120, a reference model (REF) 130, a module under verification (DUT) 140, a monitor 150, and a scoreboard 160. In some cases, the verification platform 100 may also add other modules to adapt to the needs of the module to be verified.

The test case generator 110 is configured to generate one or more test cases required by the module to be verified, where the type of the test case may be determined according to the function of the module to be verified. The driver 120 may be used to communicate test cases to the reference model 130 and to the module to be verified 140. The reference model 130 is used for simulating the function of the model 140 to be verified, and provides a judgment basis for the verification result of the model 140 to be verified. Generally, the reference model 130 and the to-be-verified module 140 execute the same test case, and the execution result of the reference model 130 is used as the expected result of the to-be-verified model 140 executing the same test case, i.e. the judgment basis of the verification result of the to-be-verified model 140. The monitor 150 may collect the outputs of the reference model 130 and the model to be verified 140 and send the expected results and the actual results to the scoreboard 160. The scoreboard 160 may score the comparison of expected and actual results. Whether the function of the module to be verified 140 is normal can be judged according to the scoring result of the scoring board 160.

At present, in order to improve performance, a concept of a virtual memory is introduced into a main stream processor, and a basic idea of the main stream processor is that sizes of programs and data can exceed sizes of an actual physical memory, a consistent address space is provided for each process, memory management such as linking, loading, sharing and memory allocation can be simplified, and in addition, the virtual memory can manage and control access rights of a page table, so that rights management of the programs such as program protection and sharing is achieved.

The most common Virtual Memory (VM) implementation at present is a virtual memory based on a paging mechanism, wherein the paging mechanism may include two implementations of a single-level page table and a multi-level page table. A single-level page table includes a mapping relationship between pages of the entire virtual address space and pages of the physical address space (or may also be referred to as blocks of the physical address space) of the memory, and in general, an operating system provides a separate page table for each process, so that when multiple processes run simultaneously, a large amount of physical memory space is occupied by using the single-level page table. Considering that the memory occupied by most processes is limited, the implementation of multi-level page tables is proposed. Compared with a single-level page table, the multi-level page table can effectively reduce the occupation of a page table on a physical storage space. However, the translation between a Virtual Address (VA) and a Physical Address (PA) based on a multi-level page table needs to be completed by accessing multiple page tables, and this management method has a disadvantage of low memory address translation efficiency.

As one implementation, the function of the memory access component can be verified by using a verification platform as shown in FIG. 1. However, based on the virtual memory technology described above, the memory access address generated by the memory access component is usually a virtual address, and therefore, in order to implement the functional verification of the memory access component, the verification platform needs to add a virtual memory model to complete the conversion between the virtual address and the physical address. The virtual memory model is used as an important component of the verification platform, and influences the quality and efficiency of the whole verification process of the memory access component function.

The traditional paging-based virtual memory has the defects of low page table utilization rate and low virtual-real conversion efficiency, and if the virtual memory model in the memory access component verification platform is realized by adopting the hardware circuit based on the multi-level page table, the time cost and the running cost of the memory access component function verification are undoubtedly greatly increased due to the lower memory address conversion efficiency.

In view of the above problems, embodiments of the present application provide a method for verifying a memory access component, where the method can implement, according to a one-to-one mapping relationship between a virtual address and a physical address in a memory, a conversion between the virtual address and the physical address in a memory access component verification process through one query, which is helpful for improving the conversion efficiency of the virtual address and the physical address in the verification process.

Fig. 2 is a schematic flowchart of a method for verifying a memory access component according to an embodiment of the present application. The method for verifying the memory access component provided in the embodiment of the present application is described in detail below with reference to fig. 2.

Referring to fig. 2, the method 200 includes steps S210 to S240. The method can be used for verifying the access component by the verification platform. For example, the method can be used for module-level verification of the memory access component, and can also be used for verification of a subsystem or a system containing the memory access component.

In step S210, a test case is run to obtain a target virtual address to be converted from the memory access component.

In the running process of the test case, an access or storage instruction of data can be generated. The memory access component can obtain the corresponding target virtual address according to the received data access or storage instruction. If an access instruction of the data is received, the memory access component can acquire a target virtual address of the data to be accessed; if a data storage instruction is received, the memory access component can acquire the data to be stored and the target virtual address of the data to be stored.

As mentioned above, the translation between virtual and physical addresses is important in the verification of memory accesses. The target virtual address may be obtained from the memory access component in order to implement the conversion between the virtual address and the physical address.

In step S220, the target virtual address is converted into a corresponding target physical address according to the pre-established mapping relationship information.

The pre-established mapping relationship information may be used to record a one-to-one mapping relationship between virtual addresses and physical addresses of the memory, in other words, the mapping relationship information may be used to record a one-to-one direct mapping relationship between each virtual address and a physical address of the memory. The mapping relationship information may be recorded by a mapping table or an array. The storage mode of the mapping relation information is not limited in the application.

Taking the example of recording mapping relationship information through a mapping table, the one-to-one mapping relationship between virtual addresses and physical addresses is further explained. If the number of virtual addresses of the memory is N, the mapping table may include N entries, and the content of each entry includes one virtual address and a physical address corresponding to the virtual address. That is, based on the mapping table, the physical address corresponding to the virtual address can be directly obtained without performing other processing.

In order to further simplify the verification process of the memory access component, the virtual address recorded in the mapping relation information may be a virtual address associated with the test case. Based on this, the amount of mapping relationship information, for example, the depth of the mapping table, may be related to the test case, that is, the mapping relationship information may only record the virtual address and the corresponding physical address related to the test case during the running process. In some implementations, the mapping relationship information of the virtual address and the physical address can be generated based on a storage structure of the test case.

As mentioned above, the virtual memory can simplify memory management, such as linking, loading, sharing and memory allocation, and can manage and control the access rights of the memory page table, thereby implementing rights management of programs, such as program protection and sharing. Therefore, in order to retain these advantages during the verification process, the mapping relationship information may further include attribute information (ATTR) and VALID flag (VALID) corresponding to the virtual address in the memory. The attribute information corresponding to the virtual address may include one or more of the following: cacheability of virtual addresses, shareability of virtual addresses, security state of virtual addresses, and size of page tables, among others. The valid flag may be used to indicate whether the physical address corresponding to the virtual address has been loaded into memory.

The role of the attribute information will be described by taking the simplified memory sharing management as an example. Typically each process will call the same operating system kernel code and each C program will call a program in the C standard, such as printf. The operating system can map certain virtual addresses in different processes to the same physical address, and the attribute of the part of the virtual address is set to be shareable, so that the sharing of the part of the code by multiple processes can be realized without the need of including a copy of kernel code and a C standard library in each process.

Based on the target virtual address, the mapping relation information is inquired, and a target physical address corresponding to the target virtual address can be obtained. Because the target virtual address can often be directly obtained in the running process of the test case, as an implementation manner, the target physical address corresponding to the target virtual address can be obtained by taking the target virtual address as an index. As an example, a lookup function may be constructed, and the lookup function is used to automatically obtain a target physical address corresponding to a target virtual address by using the target virtual address as an index.

In step S230, a memory access result is generated according to the target physical address.

And according to the converted target physical address, data access or storage can be carried out, so that a memory access result is generated. Generally, the memory access component may interact with the memory according to the target physical address, so as to generate a memory access result.

In order to match the interface of the memory access component, the converted target physical address can be processed and further converted into interface information which can be identified by the memory access component. In some embodiments, the target physical address may be processed by a post-processing function into interface information that the memory access component is able to recognize. The memory access component may obtain the target physical address based on a processing result of the post-processing function, and then generate a memory access result.

If the mapping relationship information also includes attribute information, valid flag bit and other information, the converted information of the target physical address, attribute information, valid flag bit and other information can be processed and converted into interface information that can be recognized by the memory access component. Likewise, the above information may be converted based on a post-processing function.

In step S240, the memory access component is verified according to the memory access result.

The memory access component may be verified, typically based on the memory access result and the expected memory access result. Generally, the memory access result is compared with the expected memory access result of the test case, and the verification result of the memory access component can be obtained according to the comparison result. For example, the execution results of all instructions in the test case output by the memory access component may be compared with the expected memory access results one by one, and if the memory access results of all instructions of the test case are correct, the function of the memory access component is correct, and the memory access component passes verification.

When a multi-level page table is adopted to convert a virtual address and a physical address in the related technology, firstly, a page where the virtual address is located and an address page where the corresponding physical address is located can be found by looking up the table for many times; secondly, the translation between the virtual address and the physical address needs to be completed based on the address page and the offset (offset) contained in the virtual address. Taking the current general four-level page table as an example, the related art needs 4 table lookup operations and one address translation to complete one translation between a virtual address and a physical address.

The method for verifying the memory access component provided by the embodiment of the application realizes the conversion between the virtual address and the physical address in the memory access component verification process according to the one-to-one mapping relation between the virtual address and the physical address in the memory, can obtain the physical address corresponding to the virtual address only through one table look-up operation, and greatly improves the conversion efficiency of the address. Particularly, in the verification process of the memory access component, a large number of test cases are generally required to be operated, and the verification efficiency of the memory access component can be effectively improved by improving the address conversion efficiency. Meanwhile, virtual and real address conversion is realized through mapping relation information, and the method is high in expandability and good in universality.

In order to describe the method for verifying the memory access component provided in the present application in more detail, the method is specifically described below by taking the virtual memory model shown in fig. 3 as an example.

First, the virtual memory model shown in fig. 3 will be described. Referring to FIG. 3, a virtual memory model 300 may be used to translate virtual memory addresses issued by memory access components into physical addresses that are actually accessed. The virtual memory model 300 may include an obtaining module 310, a searching module 320, a virtual-real mapping table 330, and a coupling module 340.

The virtual-real mapping table 330 may be constructed in advance based on the storage structure of the test case. The virtual-to-real mapping table may include a mapping relationship of virtual addresses and physical addresses associated with the test cases. In some embodiments, the virtual-to-real mapping table 330 may further include attribute information and valid identification bits related to the virtual address.

The obtaining module 310 may be configured to obtain a virtual memory address to be converted by the memory access component. The searching module 320 may obtain the corresponding physical address according to the virtual memory address based on the virtual-real mapping table 330, and may also obtain the corresponding physical address and information such as the attribute information and the valid flag bit of the address. For example, the lookup module 320 may return the physical address PA and the related attribute information and valid flag by using the lookup function with the virtual address VA as an index. The coupling module 340 may be configured to convert a result returned by the lookup function into interface information that can be recognized by the memory access component. The above-described functions may be implemented by post-processing functions, for example.

Secondly, based on the virtual memory model 300, the method for verifying the memory access component may include the following steps 1 to 6.

In step 1, the test case generator generates 1 test case in advance.

In step 2, a memory virtual-real address mapping table (memory map) is constructed in advance based on the memory structure of the test case in step 1. Fig. 4 shows a schematic diagram of a virtual-real address mapping table. The virtual-real address mapping table may include a virtual address, a physical address corresponding to the virtual address, attribute information, and a valid identification bit. The index of the virtual-to-real address mapping table may be a virtual address (e.g., va0 to van).

In step 3, the obtaining module obtains a virtual address to be converted of the memory access component to be tested, such as va =0x80000000.

In step 4, the lookup module performs lookup in the memory mapping table based on the virtual address obtained in step 3, obtains a corresponding physical address, and returns the lookup result to the coupling module 340. For example, the lookup module may find a row in the virtual-real address mapping table that matches va to be converted by the lookup function, where the information of the row may include, for example, va =0x80000000, pa =0x1a000000, attr includes cacheability, sharing, security status, page table size, and the like. According to the search result, the physical address corresponding to the virtual address 0x80000000 is 0x1a000000.

In step 5, the coupling module 340 processes the physical address and attribute information returned by the lookup module in step 4, converts the physical address and attribute information into interface information recognizable by the memory access component to be verified, and returns the interface information to the memory access component to be verified, thereby completing a conversion process from a virtual address to a physical address.

And 6, generating a memory access result corresponding to the test case according to the target physical address. And (3) completing the execution of each instruction in the test case to be tested, and if all execution results are correct, completing the test flow of the test case, and enabling the memory access component to be verified to have correct functions.

The method for verifying the memory access component is not limited by a memory management implementation mode based on paging management in a traditional hardware circuit, has high virtual-real address conversion efficiency, and can effectively optimize the running time and running cost of a verification process. In addition, the method for verifying the access memory component can be extended to a higher-level verification system.

Method embodiments of the present application are described in detail above in conjunction with fig. 1-4, and apparatus embodiments of the present application are described in detail below in conjunction with fig. 5-6. It is to be understood that the description of the method embodiments corresponds to the description of the apparatus embodiments, and therefore reference may be made to the method embodiments above for parts which are not described in detail.

Fig. 5 is a schematic structural diagram of a system for verifying a memory access component according to an embodiment of the present application. Referring to FIG. 5, a system 500 for verifying memory access components includes a test case generator 510, a memory access component 520 to be verified, a virtual memory model 530, and a result checking module 540.

A test case generator 510 for generating test cases.

And the memory access component 520 to be verified is used for generating a target virtual address to be converted according to the test case.

The virtual memory model 530 is configured to obtain the target virtual address, convert the target virtual address into a corresponding target physical address according to pre-established mapping relationship information, and enable the memory access component to generate a memory access result according to the target physical address, where the mapping relationship information is used to record a one-to-one mapping relationship between a virtual address and a physical address of a memory. Virtual memory model 530 may be virtual memory model 300, as mentioned above.

And the result checking module 540 is configured to verify the memory access component according to the memory access result. In some embodiments, the result checking module 540 may include the monitor 150 and scoreboard 160 in the universal verification platform 100 mentioned previously.

Optionally, the virtual address recorded in the mapping relationship information is a virtual address associated with the test case.

Optionally, the virtual memory model is used to: and inquiring the mapping relation information by using the target virtual address as an index and utilizing a search function to obtain the target physical address.

Optionally, the mapping relationship information is further used to record attribute information and valid identification bits corresponding to the virtual address in the memory.

Optionally, the attribute information includes one or more of: cacheability of a virtual address, shareability of a virtual address, security state of a virtual address.

FIG. 6 is a block diagram of another system for verifying memory access components. The system 600 for verifying memory access components may include a test case generator 510, a memory access component 520 to be verified, a virtual memory model 530, a result checking module 540, and a reference model 610.

And the test case generator 510 is used for generating the test cases required by the memory access component.

And the memory access component 520 to be verified is used for generating a target virtual address to be converted according to the test case. For example, the memory access component 520 to be verified may parse the target virtual address to be accessed from the memory access instruction in the test case.

The virtual memory model 530, which is an important component of a system for verifying a memory access component, is responsible for converting a target virtual memory address sent by the memory access component of a processor core to be verified into an actual physical address to be accessed, thereby completing interaction between data and a memory bank.

As an implementation manner, the virtual memory model 530 may convert the target virtual address into a corresponding target physical address according to pre-established mapping relationship information, where the mapping relationship information is used to record a one-to-one mapping relationship between the virtual address and the physical address of the memory. In order to preserve the advantages of the virtual memory, the mapping relationship information may also be used to record attribute information and valid flag bits corresponding to the virtual addresses in the memory. The attribute information includes one or more of: cacheability of a virtual address, shareability of a virtual address, security state of a virtual address.

In some embodiments, the virtual address recorded in the mapping relationship information is a virtual address associated with the test case. In other embodiments, the virtual memory model 530 uses the target virtual address as an index, and may query the mapping relationship information by using a lookup function to obtain the corresponding target physical address.

The reference model 610 may provide a basis for determining the execution result of the memory access component 520 to be verified.

The result checking module 540 may compare the execution result of the memory access component 520 to be verified with the result of the same test case executed by the reference model 610 to verify the function of the memory access component 520 to be verified.

According to the system for verifying the memory access component, all required information can be obtained only by searching once in the conversion process of the virtual address and the physical address, time consumption is short, and meanwhile time cost and running cost for running a test case are effectively reduced, so that the convergence process of verification of the memory access component is accelerated, and a powerful guarantee is provided for the functional stability of the whole processor core.

It should be understood that, in the embodiment of the present application, the processor may be a Central Processing Unit (CPU), and the processor may also be other general-purpose processors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It should be understood that in the embodiment of the present application, "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.

It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not imply any order of execution, and the order of execution of the processes should be determined by their functions and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

In the above embodiments, all or part of the implementation may be realized by software, hardware, firmware, or any combination thereof. When implemented in software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer readable storage medium may be any available medium that can be read by a computer or a data storage device including one or more available media integrated servers, data centers, and the like. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a Digital Versatile Disk (DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), among others.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of authenticating a memory access component, comprising:

running a test case to acquire a target virtual address to be converted from the memory access component;

converting the target virtual address into a corresponding target physical address according to pre-established mapping relationship information, wherein the mapping relationship information is used for recording a one-to-one mapping relationship between the virtual address and the physical address of the memory;

generating a memory access result according to the target physical address;

and verifying the memory access component according to the memory access result.

2. The method according to claim 1, wherein the virtual address recorded in the mapping relationship information is a virtual address associated with the test case.

3. The method of claim 1, wherein the converting the target virtual address to a corresponding target physical address according to pre-established mapping relationship information comprises:

and inquiring the mapping relation information by using the target virtual address as an index and utilizing a search function to obtain the target physical address.

4. The method according to claim 1, wherein the mapping relationship information is further used for recording attribute information and a valid flag bit corresponding to the virtual address in the memory.

5. The method of claim 4, wherein the attribute information comprises one or more of: cacheability of a virtual address, shareability of a virtual address, security state of a virtual address.

6. A system for authenticating a memory access component, comprising:

the test case generator is used for generating a test case;

the memory access component to be verified is used for generating a target virtual address to be converted according to the test case;

the virtual memory model is used for acquiring the target virtual address and converting the target virtual address into a corresponding target physical address according to pre-established mapping relation information, so that the memory access component generates a memory access result according to the target physical address, wherein the mapping relation information is used for recording the one-to-one mapping relation between the virtual address and the physical address of the memory;

and the result checking module is used for verifying the memory access component according to the memory access result.

7. The system according to claim 6, wherein the virtual address recorded in the mapping relationship information is a virtual address associated with the test case.

8. The system of claim 6, wherein the virtual memory model is configured to:

9. The system according to claim 6, wherein the mapping relationship information is further configured to record attribute information and a valid flag corresponding to the virtual address in the memory.

10. The system of claim 9, wherein the attribute information comprises one or more of: cacheability of a virtual address, shareability of a virtual address, security state of a virtual address.