CN115910816A - A kind of chip, three-dimensional chip and chip preparation method - Google Patents

Abstract

The present application discloses a chip, a three-dimensional chip and a method for preparing the chip, which relate to the technical field of integrated chips, and can improve the problem that the bumps of the existing three-dimensional chip are unevenly arranged, which easily causes poor packaging of the three-dimensional chip. The chip includes: a first chip unit, the first chip unit is provided with communication bumps, support bumps and grooves, and the communication bumps are partially embedded in the grooves; the communication bumps include The first metal layer; the supporting bump includes a second metal layer; the size of the first metal layer is larger than the size of the second metal layer.

Description

A kind of chip, three-dimensional chip and chip preparation method

technical field

The present application relates to the technical field of integrated chips, in particular to a chip, a three-dimensional chip and a method for preparing the chip.

Background technique

Chip hybrid bonding technology is a wafer-level electrical connection technology developed in recent years. Among them, a large number of I/O (input and output interface) connections have been completed at the wafer level, and some clock signals, data signals, etc. It needs to be led out to the packaging substrate through bumps, which are raised structures set on the wafer. The pitch of the bumps can be made very small, which can realize denser communication connections and shorter communication lines.

However, the setting of bumps usually needs to be based on the line position of signal input and output, and the setting position of bumps is usually uneven, and unevenly distributed bumps are likely to cause problems such as poor packaging of three-dimensional chips.

Contents of the invention

The embodiments of the present application provide a chip, a three-dimensional chip, and a method for manufacturing the chip, which can improve the problem of uneven placement of bumps on the existing three-dimensional chip, which easily causes poor packaging of the three-dimensional chip.

According to the first aspect of the embodiments of the present application, a chip is provided, including:

A first chip unit, the first chip unit is provided with communication bumps, support bumps and grooves, and the communication bumps are partially embedded in the grooves;

The communication bumps include a first metal layer;

The supporting bumps include a second metal layer;

The size of the first metal layer is larger than the size of the second metal layer.

In some embodiments, the orthographic projection of the communication bump on the first chip unit and the orthographic projection of the support bump on the first chip unit are both circular, and the communication bump is The diameter of the orthographic projection on the first chip unit is greater than the diameter of the support bump on the first chip unit.

In some embodiments, the orthographic projection of the first metal layer on the first chip unit is a first projection, and the orthographic projection of the second metal layer on the first chip unit is a second projection, The area of the first projection is larger than the area of the second projection.

In some embodiments, both the first projection and the second projection are circular, and the difference between the diameter of the first projection and the diameter of the second projection is a set threshold.

In some embodiments, the value range of the set threshold is 5-8 μm.

In some embodiments, the communication bump further includes: a first bump, and the first metal layer is disposed between the first bump and the first chip unit;

The supporting bump further includes: a second bump, the second metal layer is disposed between the second bump and the first chip unit;

The area of the orthographic projection of the first bump on the first chip unit is larger than the area of the orthographic projection of the second bump on the first chip unit.

In some embodiments, the first chip unit includes a first area and a second area, the communication bump is disposed in the first area, and the support bump is disposed in the second area.

In some embodiments, the first chip unit includes a top metal layer, a passivation layer and a buffer layer, and the passivation layer is disposed between the top metal layer and the buffer layer;

The supporting bumps are connected to the buffer layer;

The passivation layer is provided with a first through hole, the buffer layer is provided with a second through hole, and the first through hole communicates with the second through hole to form the groove.

In some embodiments, a first pad is provided on a side of the top metal layer close to the passivation layer;

The first metal layer is connected to the first pad through the first through hole, and the first bump passes through the second through hole and is connected to the first metal layer.

In the second aspect of the embodiments of the present application, a three-dimensional chip is provided, including:

The chip as described in the first aspect;

A second chip unit, the second chip unit is arranged on the side of the first chip unit away from the communication bump, and the second chip unit is electrically connected to the first chip unit.

The third aspect of the embodiments of the present application provides a method for preparing a chip, which is applied to prepare the chip as described in the first aspect, and the method includes:

disposing a first metal layer and a second metal layer on the first chip unit, wherein the size of the first metal layer is larger than the size of the second metal layer;

Communication bumps are set based on the first metal layer, and support bumps are set based on the second metal layer, wherein grooves are set on the first chip unit, and the communication bumps are partially embedded in the inside the groove.

In some embodiments, the disposing the first metal layer and the second metal layer on the first chip unit includes:

According to the fact that the height of the communication bump is positively correlated with the size of the first metal layer, and the height of the support bump is positively correlated with the size of the second metal layer, the first chip unit is provided with the The first metal layer and the second metal layer, and the size of the first metal layer is larger than the size of the second metal layer.

The chip, the three-dimensional chip, and the method for preparing the chip provided in the embodiments of the present application, by setting communication bumps and support bumps on the first chip unit, the communication bumps are used to realize the communication connection of the first chip unit, and the support bumps can It plays a supporting role, and the supporting function of the supporting bumps can disperse the stress concentration caused by the uneven distribution of the communication bumps. And, the supporting bumps can fill the area where the communication bumps are not provided, which can make the distribution of the communication bumps and the supporting bumps tend to be even, and can avoid the problem of stress concentration on the chip caused by the uneven distribution of the bumps on the first chip unit. Combined with the setting of the groove, by setting the size of the first metal layer larger than the size of the second metal layer, the size of the support bump after reflow soldering is reduced to reduce the height difference between the communication bump and the support bump, which can make the support The bumps can fully share the support burden of the communication bumps, and at the same time ensure that the communication bumps and the packaging substrate can be in normal contact to achieve a stable electrical connection.

Description of drawings

FIG. 1 is a schematic diagram of a partial structure of a chip provided in an embodiment of the present application;

FIG. 2 is a partial top view of a chip provided by an embodiment of the present application;

FIG. 3 is a schematic diagram of a partial structure of another chip provided in an embodiment of the present application;

FIG. 4 is a schematic structural diagram of a support bump provided in an embodiment of the present application;

FIG. 5 is a schematic diagram of a partial structure of another chip provided in the embodiment of the present application;

FIG. 6 is a schematic diagram of a partial structure of a three-dimensional chip provided by an embodiment of the present application;

FIG. 7 is a schematic flow chart of a chip manufacturing method provided in an embodiment of the present application.

Detailed ways

In order to better understand the technical solutions provided by the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below through the drawings and specific examples. The detailed description of the technical solutions of the embodiments is not a limitation to the technical solutions of this specification. In the case of no conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

In this document, relational terms such as first and second etc. are used only to distinguish one entity or operation from another without necessarily requiring or implying any such relationship between these entities or operations. Actual relationship or sequence. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element. The term "two or more" includes two or more cases.

The hybrid bonding technology of three-dimensional chips is a wafer-level electrical connection technology developed in recent years, which connects two or more chips through metal bonding. A large number of I/O (input and output interface) connections have been completed at the wafer level, and a small number of clock signals, data signals, etc. need to be led out to the packaging substrate through bumps, which are raised structures set on the wafer. However, the setting of bumps usually needs to be based on the line position of signal input and output, and the setting position of bumps is usually uneven, and unevenly distributed bumps are likely to cause problems such as poor packaging of three-dimensional chips.

In view of this, the present application provides a chip, a three-dimensional chip, and a method for manufacturing the chip, which can improve the problem of uneven placement of bumps on the existing three-dimensional chip, which easily causes poor packaging of the three-dimensional chip.

A first aspect of the embodiments of the present application provides a chip, and FIG. 1 is a schematic diagram of a partial structure of the chip provided by the embodiments of the present application. As shown in Figure 1, the chip provided by the embodiment of the present application includes: a first chip unit 100, on which a communication bump 110, a supporting bump 120 and a groove 101 are arranged; the communication bump 110 is partially embedded The communication bump 110 includes a first metal layer 112 ; the support bump 120 includes a second metal layer 122 ; the size of the first metal layer 112 is larger than the size of the second metal layer 122 . It should be noted that the size refers to the length and width of a rectangle or the diameter of a circle, and the size may also refer to the area of the first metal layer 112 or the second metal layer 122 on a plane parallel to the first chip unit 100. The thickness of the first metal layer 112 and the second metal layer 122 can generally be the same, and the thickness refers to the thickness in a direction perpendicular to the first chip unit 100 .

It should be noted that the chip may be at least one of a die (die or chip) and a wafer (wafer), but is not limited thereto, and may be any replacement conceivable by those skilled in the art. Wherein, a wafer refers to a silicon wafer used for manufacturing a silicon semiconductor circuit, and a chip or a die refers to a silicon wafer obtained by dividing the aforementioned wafer on which a semiconductor circuit is manufactured. In the specific embodiments of the present application, a chip is taken as an example for introduction.

It is easy to understand that the chip is integrated with electronic devices and connection lines, and some signals in the chip need to be led out from the chip to the packaging substrate, and the packaging substrate then outputs the signals to other electronic devices or circuits, which is not specifically limited in this application. Communication bumps can be provided on the chip to realize signal transmission between part of the signals in the chip and the packaging substrate through the communication bumps. Usually, it is necessary to set the communication bumps based on the specific position of the signal input and output lines. Therefore, the distribution of the communication bumps on the chip is uneven, which is easy to cause stress concentration on the chip, resulting in chip cracking or bump cracking. , affecting the reliability and service life of the chip. As shown in Figure 1, the chip provided by the embodiment of the present application is provided with a communication bump 110 and a support bump 120 on the same side of the first chip unit 100, the communication bump 110 is electrically connected to the first chip unit 100, and the support bump 120 can play a supporting role, and the supporting function of the supporting bumps 120 can disperse the stress concentration caused by the uneven distribution of the communication bumps 110 . And, the supporting bumps 120 can fill the area where the communication bumps 110 are not provided, can make the distribution of the communication bumps 110 and the supporting bumps 120 tend to be even, and can avoid bumps on the first chip unit 100 (communication bumps 110 and The uneven distribution of the supporting bumps 120) causes the problem of stress concentration on the chip. Usually, since the communication bump 110 needs to be electrically connected with the first chip unit 100, by setting the groove 101, the communication bump 110 will be partially embedded in the film layer of the first chip unit 100; 120 does not need to be electrically connected with the first chip unit 100, the support bump 120 can be directly connected to the surface of the first chip unit 100 side; therefore, when preparing the communication bump 110 and the support bump 120, it is easy to cause the support bump. The height difference between the dots 120 and the communication bumps 110 may easily cause poor electrical connection between the communication bumps 110 and the packaging substrate, resulting in chip failure. The difference between the height of the communication bump 110 and the height of the support bump 120 is less than the height difference threshold, so that the support bump 120 can fully play the role of sharing the support burden of the communication bump 110, while ensuring that the communication bump 110 and the package substrate It can make normal contact to realize stable electrical connection. It should be noted that the height of the communication bump 110 can be greater than the height of the support bump 120, and the height of the communication bump 110 can be smaller than the height of the support bump 120, as long as the height of the communication bump 110 and the height of the support bump 120 are satisfied. The difference can be smaller than the height difference threshold. The height difference threshold can be understood as the error value allowed by the packaging process in the packaging process section. The height difference threshold can be adaptively set according to the size of the chip and the size of the communication bump 110. This application does not make Specific limits. As long as the difference between the height of the communication bump 110 and the height of the support bump 120 is less than the height difference threshold, the reliability of the electrical connection between the communication bump 110 and the package substrate can be guaranteed. The preparation process of the communication bump 110 and the support bump 120 usually adopts a reflow soldering process. According to the characteristics of the reflow soldering process, the size of the first metal layer 112 can determine the height of the communication bump 110, and the size of the second metal layer 122 can also be determined. The size of the supporting bump 120, in order to realize that the difference between the height of the communication bump 110 and the height of the supporting bump 120 is less than the height difference threshold, the size of the first metal layer 112 is set to be larger than the size of the second metal layer 122, which can make the communication bump The height of 110 is greater than that of the supporting bump 120, and the supporting bump can fully share the support burden of the communication bump, while ensuring normal contact between the communication bump and the packaging substrate to achieve a stable electrical connection. It should be noted that both the communication bumps 110 and the support bumps 120 are bump structures prepared on one side of the chip.

For the chip provided in the embodiment of the present application, by setting communication bumps and support bumps on the first chip unit 100, the communication bumps 110 are used to realize the communication connection of the first chip unit 100, and the support bumps 120 can play a supporting role. , the supporting function of the supporting bumps 120 can disperse the stress concentration caused by the uneven distribution of the communication bumps 110 . And, the support bumps 120 can fill the area where the communication bumps 110 are not provided, which can make the distribution of the communication bumps 110 and the support bumps 120 tend to be even, and can avoid uneven distribution of the bumps on the first chip unit 100, which may cause chip damage. The problem of stress concentration. Combined with the setting of the groove 101, by setting the size of the first metal layer 112 larger than the size of the second metal layer 122, the size of the supporting bump 120 after reflow soldering is reduced. The size of the supporting bump 120 can specifically refer to the height, to Reducing the height difference between the communication bump 110 and the support bump 120 can make the support bump 120 fully play the role of sharing the support burden of the communication bump 110, and at the same time ensure that the communication bump 110 can be in normal contact with the package substrate to achieve stability. electrical connection.

In some embodiments, the first chip unit includes a first area and a second area, the communication bumps are arranged in the first area, and the support bumps are arranged in the second area.

Exemplarily, FIG. 2 is a partial top view of a chip provided by an embodiment of the present application. As shown in FIG. 2 , the first chip unit 100 includes a first area 130 and a second area 140 , the communication bump 110 is disposed in the first area 130 , and the support bump 120 is disposed in the second area 140 . The distribution of the communication bumps 110 and the support bumps 120 shown in FIG. 2 , and the positional relationship between the first area 130 and the second area 140 are only schematic, and are not intended to be specific limitations of the present application. The first area 130 and the second area 140 can be used to define the position distribution of the communication bumps 110 and the support bumps 120, the first area 130 is used to set the communication bumps 110, and the second area 140 is used to set the support bumps 120. Exemplarily, in FIG. 2, the communication bump 110 is not provided in the second region 140, and the communication bump 110 is arranged in the first region 130, which will cause uneven stress at the position of the second region 140, so in the second Setting the support bumps 120 in the area 140 can disperse the stress of the communication bumps 110 and avoid the stress concentration caused by the uneven distribution of the communication bumps 110 .

The number of communication bumps 110 and the number of support bumps 120 shown in FIG. 1 and FIG. 2 are only schematic, and are not intended to be specific limitations of the present application.

In the chip provided by the embodiment of the present application, by setting the support bumps 120 in the second area 140, the support bumps 120 can disperse the stress concentration formed by the communication bumps in the first area 130, and the support bumps 120 can fill the gap where no communication bumps are set. The area of the dots 110 can make the distribution of the communication bumps 110 and the support bumps 120 tend to be uniform, and can avoid the stress concentration problem of the chip caused by the uneven distribution of the bumps on the first chip unit 100 .

In some implementation manners, for example, FIG. 3 is a schematic diagram of a partial structure of another chip provided in an embodiment of the present application. As shown in FIG. 3 , a buffer layer 170 is provided on one side of the first chip unit 100, and the support bump 120 is in direct contact with and connected to the buffer layer 170. The first chip unit 100 is provided with a groove in the first area for communication. The bump 110 is partially embedded in the groove, and the bottom of the groove is provided with a first pad 180. The communication bump 110 includes a first metal layer 112, and the first metal layer 112 is connected to the first pad 180 to realize a communication bump. Point 110 is electrically connected to the first chip unit 100, the first pad 180 is usually electrically connected to the circuit in the first chip unit 100, and the circuit is usually arranged inside the first chip unit 100, therefore, the first pad 180 Usually set in a groove. In order to simplify the manufacturing process, usually the communication bump 110 and the support bump 120 can be prepared at the same time, and the same material is used for preparation. Since the support bump 120 is connected to the buffer layer 170 on the surface of the first chip unit 100, the buffer layer 170 uses If the insulating material is used, no electrical connection will be formed between the supporting bumps 120 and the first chip unit 100 . The communication bump 110 and the support bump 120 prepared in the same preparation process are usually close in size, but because the communication bump 110 is partially embedded in the groove, it is easy to cause the height difference between the support bump 120 and the communication bump larger. As shown in FIG. 3 , the difference between the height H1 of the communication bump 110 and the height H2 of the support bump 120 is less than the height difference threshold, so that the support bump 120 can fully share the supporting burden of the communication bump 110. It is ensured that the communication bump 110 can be in normal contact with the packaging substrate to achieve a stable electrical connection.

It should be noted that the height H1 of the communication bump 110 is the height of the communication bump 110 beyond the surface of the first chip unit 100. Similarly, the height H2 of the support bump 120 is the height of the support bump 120 beyond the surface of the first chip unit 100. high.

In some embodiments, the orthographic projection of the communication bump on the first chip unit and the orthographic projection of the support bump on the first chip unit are both circular, and the diameter of the orthographic projection of the communication bump on the first chip unit is larger than The diameter of the orthographic projection of the support bump on the first chip unit. Exemplarily, both the communication bumps and the support bumps may be spherical in shape, and the diameter of the communication bumps is larger than the diameter of the support bumps. In the case where both the communication bump and the support bump are spherical, since the communication bump is partially embedded in the groove, by setting the diameter of the communication bump 110 larger than the diameter of the support bump 120, the communication bump 110 can be made The difference between the height H1 and the height H2 of the supporting bump 120 is smaller than the height difference threshold.

In some embodiments, the communication bump includes a first bump; the support bump includes a second bump, and the first metal layer is disposed between the first bump and the first chip unit; the second metal layer is disposed between the second between the bump and the first chip unit. The orthographic projection of the first metal layer on the first chip unit is a first projection, the orthographic projection of the second metal layer on the first chip unit is a second projection, and the area of the first projection is larger than the area of the second projection. The first bump can be further bonded with the first metal layer through a reflow process to form a communication bump; the second bump can be further bonded with the second metal layer through a reflow process to form Support bumps. According to the characteristics of the reflow soldering process, the size of the first metal layer can determine the size of the first bump, and the size of the second metal layer can also determine the size of the second bump. Therefore, the area of the first projection is larger than the area of the second projection , can make the size of the communication bump larger than the size of the support bump, so that the difference between the height of the communication bump and the height of the support bump is less than the height difference threshold, and the support bump can fully play the role of sharing the supporting burden of the communication bump At the same time, it is ensured that the communication bumps and the packaging substrate can be in normal contact to achieve a stable electrical connection.

Exemplarily, continuing to refer to FIG. 3 , the communication bump 110 includes a first bump 111 ; the support bump 120 includes a second bump 121 ; the first metal layer 112 is disposed between the first bump 111 and the first chip unit 100 Between; the second metal layer 122 is disposed between the second bump 121 and the first chip unit 100 . The preparation materials of the first metal layer 112 and the second metal layer 122 can be the same, and the preparation materials of the first bump 111 and the second bump 121 can be the same; the preparation materials of the first metal layer 112 and the second metal layer 122 can include For metals such as copper and nickel, the first bump 111 and the second bump 121 can be prepared by using solder material, and the solder material can be tin-silver alloy, which is not specifically limited in this application. The preparation process is usually as follows: Firstly, the first metal layer 112 and the second metal layer 122 are prepared, and then the first bump 111 and the second bump 121 are prepared; at the same time, the first bump 111 and the second bump 121 are reflowed Soldering process to form the communication bump 110 and the support bump 120. Both the first bump 111 and the second bump 121 can be prepared by electroplating in the same process flow, which is not specifically limited in this application.

The orthographic projection of the first metal layer 112 on the first chip unit 100 is the first projection, and the orthographic projection of the second metal layer 122 on the first chip unit 100 is the second projection, and the area of the first projection is larger than that of the second projection. area. If both the first projection and the second projection are circular, and the diameter of the first projection is greater than the diameter of the second projection, the difference between the diameter of the first projection and the diameter of the second projection can be set as a set threshold. The set threshold can be set according to the size requirements of the communication bumps 110 and the support bumps 120 , which is not specifically limited in this application. Exemplarily, the value range of the set threshold can be 5-8 μm. The area of the orthographic projection of the first bump 111 on the first chip unit 100 is greater than the area of the orthographic projection of the second bump 121 on the first chip unit 100 .

Exemplarily, the first projection and the second projection may also be shapes such as ellipses and polygons, which are not specifically limited in this application.

Exemplarily, according to the process characteristics of reflow soldering, the size of the first bump 111 is usually based on the size of the first metal layer 112, and the size of the second bump 121 is usually based on the size of the second metal layer 122. It can be understood that the first The size of a bump 111 is positively correlated with the size of the first metal layer 112 , and the size of the second bump 121 is positively correlated with the size of the second metal layer 122 . FIG. 4 is a schematic structural diagram of a support bump provided by an embodiment of the present application. As shown in FIG. 4 , when the orthographic projection of the second metal layer 122 on the first chip unit 100 is a circle, the radius of the second metal layer 122 is r, and the second bump after the reflow soldering process is spherical. The radius of is R, and the height from the center of the spherical second bump to the surface of the second metal layer is h, then the height of the supporting bump is R+h. According to the process characteristics of reflow soldering, the radius r of the second metal layer 122 can determine h and R, and then the radius r of the second metal layer 122 can affect the height R+h of the supporting bump. Therefore, the height of the second bump 121 after reflow can be reduced by setting the size of the second metal layer 122 smaller than the size of the first metal layer 112, so as to reduce the height difference between the communication bump 110 and the support bump 120, so that The difference between the height H1 of the communication bump 110 and the height H2 of the support bump 120 is smaller than the height difference threshold. Specifically, the area of the first projection may be set to be larger than the area of the second projection. If both the first projection and the second projection are circular, the difference between the diameter of the first projection and the diameter of the second projection is a set threshold. It can also be set that the area of the orthographic projection of the first bump 111 on the first chip unit 100 is larger than the area of the orthographic projection of the second bump 121 on the first chip unit 100 .

For the chip provided in the embodiment of the present application, according to the process characteristics of reflow soldering, the size of the first bump 111 is positively related to the size of the first metal layer 112, and the size of the second bump 121 is positively related to the size of the second metal layer 122. , then by setting the size of the second metal layer 122 smaller than the size of the first metal layer 112, the height of the second bump 121 after reflow soldering is reduced to reduce the height difference between the communication bump 110 and the support bump 120, so that the communication The difference between the height H1 of the bump 110 and the height H2 of the support bump 120 is less than the height difference threshold, so that the support bump 120 can fully play the role of sharing the support burden of the communication bump 110, while ensuring that the communication bump 110 is compatible with the package. The substrate can be in normal contact to achieve a stable electrical connection.

In some embodiments, referring to FIG. 3 , the first chip unit 100 includes a top metal layer 150, a passivation layer 160, and a buffer layer 170, and the passivation layer 160 is disposed between the top metal layer 150 and the buffer layer 170; the top metal layer The layer 150 includes circuits of the first chip unit, which is not specifically limited in this application. The supporting bump 120 is connected to the buffer layer 170; the passivation layer 160 is provided with a first through hole, the buffer layer 170 is provided with a second through hole, and the first through hole communicates with the second through hole to form a groove. The top metal layer 150 is provided with a first pad 180 on the side close to the passivation layer 160; the first metal layer 112 is connected to the first pad 180 through the first through hole, and the first bump 111 is penetrated through the second through hole , and connected to the first metal layer 112 . The buffer layer 170 may be made of a polymer material, and the function of the buffer layer 170 may be to relieve the stress of the passivation layer 160 and improve the toughness of the first chip unit 100 .

In the chip provided by the embodiment of the present application, a first through hole is opened on the passivation layer 160, a second through hole is opened on the buffer layer 170, the first through hole is connected with the second through hole to form a groove, and the communication bump 110 part Embedded in the groove, the first metal layer 112 of the communication bump 110 is connected to the first pad 180 to realize the electrical connection between the communication bump 110 and the first chip unit 100 . Both the communication bumps 110 and the supporting bumps 120 are made of conductive materials, and the supporting bumps are connected to the buffer layer 170 , so the supporting bumps are not electrically connected to the first chip unit 100 .

Exemplarily, continuing to refer to FIG. 3 , the buffer layer 170 may have a thickness in the range of 5-10 μm, and the upper surface of the first pad 180 may be lower than the upper surface of the passivation layer 160 by 2-3 μm. According to the precision requirements of the packaging process, When the height difference threshold is greater than 12 μm, poor contact between the communication bump 110 and the package substrate is likely to occur, resulting in disconnection of the circuit and failure of the product. Therefore, the height difference threshold cannot be greater than 12 μm.

In some embodiments, the chip provided in the embodiment of the present application further includes a package substrate, and the communication bump and the support bump are arranged between the first chip unit and the package substrate, and the communication bump is electrically connected to the first chip unit and the package substrate respectively. connect. Filling glue is arranged between the first chip unit and the packaging substrate.

Exemplarily, FIG. 5 is a schematic diagram of a partial structure of another chip provided in an embodiment of the present application. As shown in FIG. 5 , the chip provided by the embodiment of the present application further includes: a package substrate 200 , a printed circuit board 300 and a heat sink 400 . The communication bumps 110 and the supporting bumps are disposed between the first chip unit 100 and the package substrate 200 , and the communication bumps 110 are electrically connected to the first chip unit 100 and the package substrate 200 respectively. The package substrate 200 and the printed circuit board 300 can be connected by solder balls 310, the solder balls 310 can provide electrical signal transmission between the package substrate 200 and the printed circuit board 300, the solder balls 310 can be made of tin-silver material, printed circuit The pads at the corresponding positions of the board 300 and the solder balls 310 may be plated with copper, which is not specifically limited in this application. The packaging substrate 200 and the printed circuit board 300 may also be electrically connected through solder balls, which is not specifically limited in this application. Filling glue 210 is provided between the first chip unit 100 and the packaging substrate 200, and the filling glue 210 can fill the gap between the communication bump 110 and the supporting bump 120, and fill the gap between the first chip unit 100 and the packaging substrate 200. The filling glue 210 can relieve the stress, protect the communication bumps 110 and the support bumps 120 , and prevent the package substrate 200 , the communication bumps 110 and the support bumps 120 from cracking. The heat sink 400 can provide the first heat dissipation channel A and the third heat dissipation channel C for the first chip unit 100, and the first chip unit 100 can also dissipate heat through the second heat dissipation channel B formed by the package substrate 200 and the printed circuit board 300, This application does not make specific limitations. The package substrate 200 may be provided with a second pad, and the end of the communication bump 110 and the support bump away from the first chip unit 100 may be connected to the second pad, which is not specifically limited in this application.

In the chip provided in the embodiment of the present application, communication bumps 110 and support bumps 120 are provided between the first chip unit 100 and the packaging substrate 200, the communication bumps 110 are used to electrically connect the first chip unit 100 and the packaging substrate 200, and support The bumps 120 are used to disperse the support stress concentration caused by the communication bumps 110, and avoid chip breakage caused by the support stress concentration caused by the communication bumps 110; in addition, in combination with the setting of the groove 101, by setting the The size is greater than the size of the second metal layer 122 to reduce the size of the support bump 120 after reflow soldering, to reduce the height difference between the communication bump 110 and the support bump 120, and to avoid the communication bump 110 and the support bump after reflow soldering. The problem of poor contact between the communication bump 110 and the packaging substrate 200 is caused by the excessive height difference of 120 .

The second aspect of the embodiments of the present application provides a three-dimensional chip, including the chip as described in the first aspect;

The second chip unit is arranged on the side of the first chip unit away from the communication bump, and the second chip unit is electrically connected to the first chip unit.

Exemplarily, FIG. 6 is a schematic diagram of a partial structure of a three-dimensional chip provided in an embodiment of the present application.

As shown in Figure 6, the three-dimensional chip provided by the embodiment of the present application includes:

The chip 1000 as described in the first aspect;

The second chip unit 2000 , the second chip unit 2000 is disposed on the side of the first chip unit 100 away from the communication bump 110 , and the second chip unit 2000 is electrically connected to the first chip unit 100 . The second chip unit 2000 and the first chip unit 100 can be electrically connected through the connection structure 2100, and the connection structure 2100 can be realized by metal bonding. For example, the connection structure 2100 can be a copper-copper metal bonding structure. Not specifically limited.

It should be noted that the three-dimensional chip provided in the embodiment of the present application may further include more chip units, which is not specifically limited here.

In the three-dimensional chip provided by the embodiment of the present application, by setting communication bumps and support bumps on the first chip unit 100, the communication bumps 110 are used to realize the communication connection of the first chip unit 100, and the support bumps 120 can play a supporting role. The supporting function of the supporting bumps 120 can disperse the stress concentration caused by the uneven distribution of the communication bumps 110 . And, the support bumps 120 can fill the area where the communication bumps 110 are not provided, which can make the distribution of the communication bumps 110 and the support bumps 120 tend to be even, and can avoid uneven distribution of the bumps on the first chip unit 100, which may cause chip damage. The problem of stress concentration. Combined with the setting of the groove 101, by setting the size of the first metal layer 112 larger than the size of the second metal layer 122, the size of the support bump 120 after reflow soldering is reduced, so as to reduce the height of the communication bump 110 and the support bump 120 Poor, can make the support bump 120 fully play the role of sharing the support burden of the communication bump 110, and at the same time ensure that the communication bump 110 can be in normal contact with the packaging substrate to achieve a stable electrical connection.

A third aspect of the embodiments of the present application provides a chip manufacturing method, and FIG. 7 is a schematic flowchart of a chip manufacturing method provided in the embodiments of the present application. As shown in Figure 7, the chip preparation method provided in the embodiment of the present application is applied to prepare the chip as described in the first aspect, and the method includes:

S100: Disposing a first metal layer and a second metal layer on the first chip unit, wherein the size of the first metal layer is larger than the size of the second metal layer.

S200: disposing communication bumps based on the first metal layer, and disposing support bumps based on the second metal layer, wherein the first chip unit is provided with a groove, and the communication bump is partially embedded in the groove. Referring to FIG. 1, the preparation process of the communication bump 110 and the support bump 120 usually adopts a reflow soldering process. According to the characteristics of the reflow soldering process, the size of the first metal layer 112 can determine the height of the communication bump 110, and the size of the second metal layer 122 The size can also determine the size of the support bump 120. In order to realize that the difference between the height of the communication bump 110 and the height of the support bump 120 is less than the height difference threshold, the size of the first metal layer 112 is set to be larger than the size of the second metal layer 122, which can The height of the communication bumps 110 is greater than the height of the support bumps 120, and the support bumps can fully share the support burden of the communication bumps, while ensuring normal contact between the communication bumps and the packaging substrate to achieve stable electrical connection. It should be noted that both the communication bumps 110 and the support bumps 120 are bump structures prepared on one side of the chip.

In some embodiments, step S100 includes:

According to the positive correlation between the height of the communication bump and the size of the first metal layer, and the positive correlation between the height of the support bump and the size of the second metal layer, the first metal layer and the second metal layer are arranged on the first chip unit, and The size of the first metal layer is larger than the size of the second metal layer. As shown in FIG. 3, the first bump 111 is set on the first metal layer 112, and the second bump 121 is set on the second metal layer 122; reflow soldering is performed on the first bump 111 and the second bump 121 at the same time process to form the communication bumps 110 and the support bumps 120 . In the communication bump 110, the first metal layer 112 and the first bump 111 are bonded together, and in the support bump 120, the second metal layer 122 and the second bump 121 are bonded together. Process characteristics, the volume of the first bump 111 before reflow soldering is the same as the volume of the communication bump 110 obtained after reflow soldering, and the volume of the second bump 121 before reflow soldering is the same as that of the support bump 120 obtained after reflow soldering Same volume. Exemplarily, taking the support bump 120 as an example, the second bump 121 is set to be spherical, and the radius of the second bump 121 before reflow soldering is n, then the calculation formula of the volume V1 of the second bump 121 before reflow soldering is as follows:

4, when the orthographic projection of the second metal layer 122 supporting the bump 121 on the first chip unit 100 shown in FIG. The bump 120 includes a spherical part and a second metal layer, the radius of the spherical part is R, the height from the center of the sphere to the surface of the second metal layer is h, and the thickness of the second metal layer is k, then the height of the supporting bump is R+ h. The volume V2 of the supporting bump after reflow soldering is the volume of the spherical part plus the volume of the second metal layer. The calculation formula of V2 is as follows:

V1=V2, then

Then the radius r of the second metal layer 122 can determine h and R, and then the radius r of the second metal layer 122 can affect the height R+h of the supporting bump. Therefore, the height of the second bump 121 after reflow can be reduced by setting the size of the second metal layer 122 smaller than that of the first metal layer 112 , so as to reduce the height difference between the communication bump 110 and the support bump 120 .

While the preferred embodiments of the present specification have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once the basic inventive concept is appreciated. Therefore, it is intended that the appended claims be interpreted to cover the preferred embodiment as well as all changes and modifications that fall within the scope of this specification.

Obviously, those skilled in the art can make various changes and modifications to this description without departing from the spirit and scope of this description. In this way, if these modifications and variations of this specification fall within the scope of the claims of this specification and their equivalent technologies, this specification also intends to include these modifications and variations.

Claims (12)

1. A chip, comprising:

the chip comprises a first chip unit, a second chip unit and a third chip unit, wherein the first chip unit is provided with a communication bump, a supporting bump and a groove, and the communication bump is partially embedded in the groove;

the communication bump comprises a first metal layer;

the support bump comprises a second metal layer;

the size of the first metal layer is larger than that of the second metal layer.

2. The chip of claim 1, wherein an orthographic projection of the communication bump on the first chip unit and an orthographic projection of the support bump on the first chip unit are both circular, and wherein a diameter of the orthographic projection of the communication bump on the first chip unit is larger than a diameter of the orthographic projection of the support bump on the first chip unit.

3. The chip of claim 1, wherein an orthographic projection of the first metal layer on the first chip unit is a first projection, and an orthographic projection of the second metal layer on the first chip unit is a second projection, and an area of the first projection is larger than an area of the second projection.

4. The chip of claim 3, wherein the first projection and the second projection are both circular, and a diameter of the first projection differs from a diameter of the second projection by a set threshold.

5. The chip of claim 4, wherein the threshold is set to a value in a range of 5-8 μm.

6. The chip of claim 3, wherein the communication bump further comprises: a first bump, the first metal layer being disposed between the first bump and the first chip unit;

the support bump further includes: the second metal layer is arranged between the second bump and the first chip unit;

the area of the orthographic projection of the first bump on the first chip unit is larger than the area of the orthographic projection of the second bump on the first chip unit.

7. The chip of claim 6, wherein the first chip unit comprises a first region and a second region, the communication bump is disposed in the first region, and the support bump is disposed in the second region.

8. The chip of claim 7, wherein the first chip unit comprises a top metal layer, a passivation layer and a buffer layer, the passivation layer being disposed between the top metal layer and the buffer layer;

the supporting convex points are connected with the buffer layer;

the passivation layer is provided with a first through hole, the buffer layer is provided with a second through hole, and the first through hole is communicated with the second through hole to form the groove.

9. The chip of claim 8, wherein a side of the top metal layer adjacent to the passivation layer is provided with a first pad;

the first metal layer is connected with the first bonding pad through the first through hole, and the first bump penetrates through the second through hole and is connected with the first metal layer.

10. A three-dimensional chip, comprising:

the chip of any one of claims 1-9;

and the second chip unit is arranged on one side of the first chip unit, which is deviated from the communication bump, and is electrically connected with the first chip unit.

11. A method for preparing a chip, for use in preparing a chip according to any one of claims 1 to 9, the method comprising:

arranging a first metal layer and a second metal layer on a first chip unit, wherein the size of the first metal layer is larger than that of the second metal layer;

and arranging a communication bump based on the first metal layer and arranging a support bump based on the second metal layer, wherein a groove is arranged on the first chip unit, and the communication bump is partially embedded in the groove.

12. The method for manufacturing a chip according to claim 11, wherein the disposing a first metal layer and a second metal layer on the first chip unit comprises:

according to the height of the communication bump and the size of the first metal layer are positively correlated, and the height of the supporting bump and the size of the second metal layer are positively correlated, the first metal layer and the second metal layer are arranged on the first chip unit, and the size of the first metal layer is larger than that of the second metal layer.

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