CN115903994A - Band gap reference circuit and chip - Google Patents

Abstract

The invention discloses a bandgap reference circuit and a chip. The bandgap reference circuit includes: a first MOS transistor, a first triode, a second triode, a first resistor, a second resistor, a third resistor, an amplifier and Adjustable resistance unit. According to the device bandgap reference circuit and chip of the present invention, compared with the traditional bandgap reference circuit structure, the circuit structure of the present invention is simple, the output voltage accuracy is high, and the noise of the power supply and the ground has good suppression ability, which can be easily It can well solve the interference to the reference voltage caused by the large ground noise in circuits such as DCDC converters, and can be widely used in semiconductor integrated circuits as a high-performance reference circuit.

Description

Band gap reference circuit and chip

technical field

The invention relates to the field of integrated circuits, in particular to a bandgap reference circuit and chip.

Background technique

As an indispensable basic module in semiconductor integrated circuits, bandgap reference circuits are widely used in amplifiers, analog-to-digital converters, digital-to-analog converters, radio frequency, sensors and power management chips. Traditional bandgap reference circuits include voltage references based on Zener diode reverse breakdown characteristics, voltage references based on PN junction forward conduction characteristics, and bandgap references. Because the bandgap reference has the advantages of small temperature drift and high voltage accuracy, it has been widely used.

In the design of power management chips and analog/digital converters (ADC), digital/analog converters (DAC), dynamic memory (DRAM), Flash memory and other chip designs, the bandgap with low temperature coefficient, low power consumption and high anti-interference Benchmark design is critical.

In the bandgap reference circuit in the prior art, the anti-interference design of the circuit is mainly optimized for the power supply rejection ratio (PSSR), but it does not have a good ability to suppress ground noise. The power management chip, especially the noise in the DCDC converter chip is generally relatively large, and the noise will greatly interfere with the output voltage of the bandgap reference circuit, thereby affecting the performance of the entire chip.

The information disclosed in this Background section is only for enhancing the understanding of the general background of the present invention and should not be taken as an acknowledgment or any form of suggestion that the information constitutes the prior art that is already known to those skilled in the art.

Contents of the invention

The purpose of the present invention is to provide a bandgap reference circuit, which can improve the ability to suppress ground noise.

To achieve the above object, an embodiment of the present invention provides a bandgap reference circuit, comprising: a first MOS transistor, a first triode, a second triode, a first resistor, a second resistor, a third resistor, amplifier and adjustable resistance unit.

The source of the first MOS transistor is connected to the power supply voltage, the drain of the first MOS transistor is connected to the collector and the base of the first triode and the collector and the base of the second triode and used To output the reference voltage, the emitter of the first transistor is connected to the first terminal of the third resistor and the first input terminal of the amplifier, and the emitter of the second transistor is connected to the first terminal of the first resistor connected, the second end of the first resistor is connected to the second input end of the amplifier and the first end of the second resistor, the output end of the amplifier is connected to the gate of the first MOS transistor, and the third resistor The second end is connected with the second end of the second resistor and the first end of the adjustable resistance unit, and the second end of the adjustable resistance unit is connected with the ground voltage.

In one or more embodiments of the present invention, the adjustable resistance unit includes a fourth resistance and several resistance units, and the fourth resistance and resistance units are connected in series.

In one or more embodiments of the present invention, the resistor unit includes a fifth resistor and a second MOS transistor, the drain of the second MOS transistor is connected to the first end of the fifth resistor, and the second MOS transistor The source of the transistor is connected to the second end of the fifth resistor, and the gate of the second MOS transistor is used to receive a control signal.

In one or more embodiments of the present invention, the bandgap reference circuit further includes a startup circuit, and the startup circuit is used to switch the bandgap reference circuit from a degenerate state to a normal working state.

In one or more embodiments of the present invention, the startup circuit includes an eighth resistor, a ninth resistor, a third MOS transistor, and a fourth MOS transistor;

The first end of the eighth resistor and the first end of the ninth resistor are connected to the power supply voltage, and the second end of the eighth resistor is connected to the gate of the third MOS transistor and the drain of the fourth MOS transistor, so The second end of the ninth resistor is connected to the drain of the third MOS transistor, and the gate of the fourth MOS transistor and the source of the third MOS transistor are connected to the collectors of the first transistor and the second transistor , the source of the fourth MOS transistor is connected to the ground voltage.

In one or more embodiments of the present invention, the bandgap reference circuit further includes a filter circuit for filtering the reference voltage.

In one or more embodiments of the present invention, the bandgap reference circuit further includes a BG_OK generating circuit for outputting a BG_OK signal when the reference voltage is higher than a preset value.

In one or more embodiments of the present invention, the BG_OK generating circuit includes a tenth resistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, a first inverter, a second inverter and a three inverters;

The gate of the fifth MOS transistor is connected to the gate of the sixth MOS transistor for receiving a reference voltage, the first end of the tenth resistor is connected to the power supply voltage, and the second end of the tenth resistor is connected to the first The input terminal of the inverter is connected to the drain of the fifth MOS transistor, the source of the fifth MOS transistor is connected to the drain of the sixth MOS transistor and the drain of the seventh MOS transistor, and the drain of the sixth MOS transistor The source and the source of the seventh MOS transistor are connected to the ground voltage, the output terminal of the first inverter is connected to the gate of the seventh MOS transistor and the input terminal of the second inverter, and the second inverter The output end of the inverter is connected to the input end of the third inverter, and the output end of the third inverter is used to output the BG_OK signal.

In one or more embodiments of the present invention, the bandgap reference circuit further includes a first capacitor, the first terminal of the first capacitor is connected to the gate of the first MOS transistor, and the first terminal of the first capacitor is The two terminals are connected with the drain of the first MOS transistor.

The invention also discloses a chip, comprising: the bandgap reference circuit.

Compared with the prior art, the bandgap reference circuit and chip according to the embodiment of the present invention, compared with the traditional bandgap reference circuit structure, the circuit structure of the present invention is simple, the output voltage accuracy is high, and the noise of the power supply and the ground is not affected. Good suppression ability can well solve the interference on the reference voltage caused by the large ground noise in circuits such as DCDC converters, and can be widely used in semiconductor integrated circuits as a high-performance reference circuit.

Description of drawings

FIG. 1 is a circuit schematic diagram of a bandgap reference circuit according to an embodiment of the present invention.

FIG. 2 is a graph showing the variation of the reference voltage generated by the bandgap reference circuit with temperature according to an embodiment of the present invention.

FIG. 3 is a graph showing the suppression ability of the reference voltage generated by the bandgap reference circuit against power supply noise according to an embodiment of the present invention.

FIG. 4 is a graph showing the suppression ability of the reference voltage generated by the bandgap reference circuit to ground noise according to an embodiment of the present invention.

Detailed ways

The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations thereof such as "includes" or "includes" and the like will be understood to include the stated elements or constituents, and not Other elements or other components are not excluded.

As shown in Figure 1, a bandgap reference circuit includes: a first MOS transistor MP1, a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, and a third resistor R3 The core circuit 10 composed of the amplifier AMP, the first capacitor C1 and the adjustable resistance unit, the startup circuit 20 , the filter circuit 30 and the BG_OK generation circuit 40 .

Wherein, the source of the first MOS transistor MP1 is connected to the power supply voltage VDD, the drain of the first MOS transistor MP1 is connected to the collector and base of the first transistor Q1 and the collector and base of the second transistor Q2 Connected and used to output the reference voltage VBG1. A first end of the first capacitor C1 is connected to the gate of the first MOS transistor MP1, and a second end of the first capacitor C1 is connected to the drain of the first MOS transistor MP1. The emitter of the first transistor Q1 is connected to the first end of the third resistor R3 and the first input end of the amplifier AMP to form node A, and the emitter of the second transistor Q2 is connected to the first end of the first resistor R1 The second terminal of the first resistor R1 is connected to the second input terminal of the amplifier AMP and the first terminal of the second resistor R2 to form a connection node B, and the output terminal of the amplifier AMP is connected to the gate of the first MOS transistor MP1. The second end of the third resistor R3 and the second end of the second resistor R2 are connected to the first end of the adjustable resistance unit, and the second end of the adjustable resistance unit is connected to the ground voltage GND. The first input terminal of the amplifier AMP is a positive input terminal, and the second input terminal of the amplifier AMP is a negative input terminal.

The adjustable resistance unit includes a fourth resistance R4 and several resistance units, the first end of the fourth resistance R4 is connected with the second end of the third resistance R3 and the second end of the second resistance R2, and the fourth resistance R4 and the resistance units are connected to each other. in series. In this embodiment, there are two resistance units 11 , namely a first resistance unit 11 and a second resistance unit 12 . In other embodiments, other numbers of resistance units 11 can be provided as required, such as four, five, seven and so on.

The first resistor unit 11 includes a fifth resistor R5 and a second MOS transistor MN1. The drain of the second MOS transistor MN1 is connected to the first end of the fifth resistor R5 and the second end of the fourth resistor, the source of the second MOS transistor MN1 is connected to the second end of the fifth resistor R5, and the second MOS transistor MN1 is connected to the second end of the fifth resistor R5. The gate of MN1 is used to receive the control signal VTM1.

The second resistor unit 12 includes a sixth resistor R6 and an eighth MOS transistor MN2. The drain of the eighth MOS transistor MN2 is connected to the first end of the sixth resistor R6 and the second end of the fifth resistor R5, the source of the eighth MOS transistor MN2 is connected to the ground voltage GND, and the gate of the eighth MOS transistor MN2 Used to receive the control signal VTM2.

By adjusting the control signals VTM1 and VTM2 , the second MOS transistor MN1 and/or the eighth MOS transistor MN2 can be turned on, so that the adjustable resistance unit exhibits different resistance values. By adjusting the resistance value of the adjustable resistance unit, the precision of the reference voltage VBG1 can be improved.

In this embodiment, if the resistance values of the second resistor R2 and the third resistor R3 are equal, then:

其中，V_BE1、V_BE2为第一三极管Q1、第二三极管Q2的基极和发射极之间的电压，I₁＝ΔV_BE/R₁，ΔV_BE＝

Wherein, V _BE1 and V _BE2 are the voltages between the base and emitter of the first transistor Q1 and the second transistor Q2, I ₁ =ΔV _BE /R ₁ , ΔV _BE =

V _BE1 -V _BE2 ; R _Trim is the resistance value of the adjustable resistance unit.

Based on the characteristics of the amplifier AMP, it can well ensure that the voltages at nodes A and B are equal, and at the same time, it can also well shield the noise generated by the ground terminal from being transmitted to the reference voltage VBG1. Compared with the traditional bandgap reference voltage structure, this The structure greatly improves the ground noise suppression ability of the circuit while ensuring the power supply voltage rejection ratio PSSR; the amplifier AMP can adopt a traditional 5-tube operational amplifier structure or a folded cascode structure.

As shown in FIG. 1 , the start-up circuit 20 is used to switch the bandgap reference circuit from a degenerate state to a normal working state.

In this embodiment, the startup circuit 20 includes an eighth resistor R8, a ninth resistor R9, a third MOS transistor MN3 and a fourth MOS transistor MN4.

Specifically, the first end of the eighth resistor R8 and the first end of the ninth resistor R9 are connected to the power supply voltage VDD, and the second end of the eighth resistor R8 is connected to the gate of the third MOS transistor MN3 and the gate of the fourth MOS transistor MN4. The drain is connected, the second end of the ninth resistor R9 is connected to the drain of the third MOS transistor MN3, the gate of the fourth MOS transistor MN4, the source of the third MOS transistor MN3 are connected to the first triode Q1 and the second three The collector of the transistor Q2 is connected, and the source of the fourth MOS transistor MN4 is connected to the ground voltage GND.

During the power-on process of the power supply voltage VDD, the core circuit 10 may be in a degenerate state. At this time, the reference voltage VBG1 remains in a low-level state. At this time, the fourth MOS transistor MN4 is turned off, and the third MOS transistor MN3 is turned on, so that there is The current is poured into the core circuit 10, so that the core circuit 10 leaves the degenerate state and keeps the reference voltage VBG1 at a normal working voltage. At this time, the fourth MOS transistor MN4 is turned on, the third MOS transistor MN3 is turned off, and the core circuit 10 enters a normal working state .

As shown in FIG. 1 , the filter circuit 30 is used to filter the reference voltage VBG1 to output the final reference voltage VBG, so as to further improve the noise suppression capability of the bandgap reference circuit.

In this embodiment, the filter circuit 30 includes a seventh resistor R7 and a second capacitor C2. The first end of the seventh resistor R7 is connected to the collectors of the first transistor Q1 and the second transistor Q2, the second end of the seventh resistor R7 is connected to the first end of the second capacitor C2, and the second capacitor C2 The second terminal of is connected to the ground voltage GND.

As shown in FIG. 1 , the BG_OK generating circuit 40 is used to output a BG_OK signal when the reference voltage VBG is higher than a preset value.

In this embodiment, the BG_OK generating circuit 40 includes a tenth resistor R10, a fifth MOS transistor MN5, a sixth MOS transistor MN6, a seventh MOS transistor MN7, a first inverter INV1, a second inverter INV2 and a third Inverter INV3.

Specifically, the gate of the fifth MOS transistor MN5 is connected to the gate of the sixth MOS transistor MN6 for receiving the reference voltage, the first end of the tenth resistor R10 is connected to the power supply voltage VDD, and the second end of the tenth resistor R10 is connected to the The input end of the first inverter INV1 is connected to the drain of the fifth MOS transistor MN5, the source of the fifth MOS transistor MN5 is connected to the drain of the sixth MOS transistor MN6 and the drain of the seventh MOS transistor MN7, and the sixth The source of the MOS transistor MN6 and the source of the seventh MOS transistor MN7 are connected to the ground voltage GND, and the output terminal of the first inverter INV1 is connected to the gate of the seventh MOS transistor MN7 and the input terminal of the second inverter INV2 , the output terminal of the second inverter INV2 is connected to the input terminal of the third inverter INV3, and the output terminal of the third inverter INV3 is used to output the BG_OK signal.

When the final reference voltage VBG output by the core circuit 10 is less than the preset value, the BG_OK signal is a low-level signal, and when the reference voltage VBG is higher than the preset value, the BG_OK signal is a high-level signal for turning on subsequent related circuits .

This embodiment also discloses a chip, including: the above-mentioned bandgap reference circuit.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling others skilled in the art to make and use various exemplary embodiments of the invention, as well as various Choose and change. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (10)

1. A bandgap reference circuit, comprising: the circuit comprises a first MOS tube, a first triode, a second triode, a first resistor, a second resistor, a third resistor, an amplifier and an adjustable resistor unit;

the source electrode of the first MOS tube is connected with a power supply voltage, the drain electrode of the first MOS tube is connected with the collector electrode and the base electrode of the first triode and the collector electrode and the base electrode of the second triode and used for outputting a reference voltage, the emitter electrode of the first triode is connected with the first end of the third resistor and the first input end of the amplifier, the emitter electrode of the second triode is connected with the first end of the first resistor, the second end of the first resistor is connected with the second input end of the amplifier and the first end of the second resistor, the output end of the amplifier is connected with the grid electrode of the first MOS tube, the second end of the third resistor is connected with the second end of the second resistor and the first end of the adjustable resistance unit, and the second end of the adjustable resistance unit is connected with a ground voltage.

2. The bandgap reference circuit as recited in claim 1, wherein the adjustable resistance unit comprises a fourth resistor and a plurality of resistor units, and the fourth resistor and the resistor units are connected in series with each other.

3. The bandgap reference circuit as recited in claim 2, wherein the resistance unit comprises a fifth resistor and a second MOS transistor, a drain of the second MOS transistor is connected to a first end of the fifth resistor, a source of the second MOS transistor is connected to a second end of the fifth resistor, and a gate of the second MOS transistor is configured to receive the control signal.

4. The bandgap reference circuit as recited in claim 1, further comprising a start-up circuit for transitioning the bandgap reference circuit from a degenerate state to a normal operating state.

5. The bandgap reference circuit as claimed in claim 4, wherein said start-up circuit comprises an eighth resistor, a ninth resistor, a third MOS transistor and a fourth MOS transistor;

the first end of eighth resistance, the first end of ninth resistance link to each other with mains voltage, the second end of eighth resistance links to each other with the grid of third MOS pipe and the drain electrode of fourth MOS pipe, the second end of ninth resistance links to each other with the drain electrode of third MOS pipe, the grid of fourth MOS pipe, third MOS pipe source electrode link to each other with the collecting electrode of first triode and second triode, the source electrode of fourth MOS pipe links to each other with ground voltage.

6. The bandgap reference circuit as recited in claim 1, wherein the bandgap reference circuit further comprises a filtering circuit for filtering the reference voltage.

7. The bandgap reference circuit of claim 1, further comprising a BG _ OK generation circuit for outputting a BG _ OK signal when the reference voltage is above a preset value.

8. The bandgap reference circuit of claim 7, wherein the BG _ OK generating circuit comprises a tenth resistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, a first inverter, a second inverter, and a third inverter;

the gate of the fifth MOS tube is connected with the gate of the sixth MOS tube and used for receiving reference voltage, the first end of the tenth resistor is connected with power supply voltage, the second end of the tenth resistor is connected with the input end of the first phase inverter and the drain electrode of the fifth MOS tube, the source electrode of the fifth MOS tube is connected with the drain electrode of the sixth MOS tube and the drain electrode of the seventh MOS tube, the source electrode of the sixth MOS tube and the source electrode of the seventh MOS tube are connected with ground voltage, the output end of the first phase inverter is connected with the gate of the seventh MOS tube and the input end of the second phase inverter, the output end of the second phase inverter is connected with the input end of the third phase inverter, and the output end of the third phase inverter is used for outputting BG _ OK signals.

9. The bandgap reference circuit as recited in claim 1, further comprising a first capacitor, wherein a first terminal of the first capacitor is connected to the gate of the first MOS transistor, and a second terminal of the first capacitor is connected to the drain of the first MOS transistor.

10. A chip, comprising: a bandgap reference circuit as claimed in any one of claims 1 to 9.

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