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CN1158693C - Method for forming polysilicon layer by deuterium in semiconductor manufacturing process - Google Patents

Method for forming polysilicon layer by deuterium in semiconductor manufacturing process Download PDF

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Publication number
CN1158693C
CN1158693C CNB011326743A CN01132674A CN1158693C CN 1158693 C CN1158693 C CN 1158693C CN B011326743 A CNB011326743 A CN B011326743A CN 01132674 A CN01132674 A CN 01132674A CN 1158693 C CN1158693 C CN 1158693C
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China
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deuterium
polysilicon layer
layer
polysilicon
gate oxide
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CN1404105A (en
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黄致远
黄燿林
林经祥
范郁琪
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Macronix International Co Ltd
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Macronix International Co Ltd
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Abstract

The invention discloses a method for forming a polysilicon layer by deuterium in a semiconductor manufacturing process. First, a semiconductor substrate is provided, wherein the semiconductor substrate has a dielectric layer thereon. Silane containing chlorine and deuterium is then decomposed to form a polysilicon layer over the dielectric layer.

Description

Method for forming polysilicon layer by deuterium in semiconductor manufacturing process
Technical Field
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a polysilicon layer by deuterium during a semiconductor manufacturing process.
Background
In a semiconductor device, a typical MOS structure is a gate structure formed on a gate oxide film. At this time, conductors forming the gate structure are, for example, polysilicon, polycide, etc. Polysilicon is a thin film and is widely used in semiconductor manufacturing. Polysilicon is typically used in integrated circuits such as gate structures, interconnects and capacitors. However, polysilicon is limited to a strong high resistance force. A polycide film is formed on the doped polysilicon film, the polycide film is composed of a low resistance metal silicide and can be used instead of polysilicon. Reducing the resistance of the gate and interconnect leads to faster integrated circuits and slower power consuming integrated circuits.
Referring to fig. 1A, first, a semiconductor substrate 100 is provided. Then, a gate oxide layer 102 is formed on the semiconductor substrate 100. The gate oxide layer 102 may be a silicon dioxide layer formed by thermal oxidation or chemical vapor deposition, such as pecvd, apcvd and lpcvd. Then, a polysilicon layer 104 is formed on the gate oxide layer 102, the polysilicon layer 104 using Silane (SiH)4) The gas is a reaction gas and is formed by a low pressure chemical vapor deposition method. Thus, at the interface between the gate oxide layer 102 and the gate polysilicon 104, there are always a number of dangling bonds ending with hydrogen in the silicon-hydrogen bonds.
Polysilicon is typically deposited by pyrolysis (e.g., thermal decomposition) of silane at temperatures between 580 and 650 ℃. The main deposition technique is low pressure chemical vapor deposition. The reaction equation for deposition is:
referring to fig. 1B, a molecular structure diagram is shown in which a floating bond occurs between gate oxide layer 102 and polysilicon layer 104. Silicon-hydrogen bonds on the gate oxide and polysilicon layer surfaces will cause poor electrical results.
Referring to fig. 1C, a diagram of the MOS structure after the partial etching and spacer formation in fig. 1A is shown, wherein a semiconductor substrate 100, a gate oxide layer 102 and a polysilicon layer 104 are sequentially formed. Spacers 106 are formed on sidewalls of the polysilicon layer 104, and ions are implanted into the semiconductor substrate 100 using the polysilicon layer 104 and the spacers 106 as masks to form source/drain regions 108. And passing a voltage on the polysilicon layer 104 to complete the cross-sectional view of the MOS transistor. Whereas Silane (SiH) was used because of the problem posed by FIG. 1B4) The gas is a reactive gas that causes instability between the gate oxide layer 102 and the gate oxide layer surface of the gate polysilicon layer 104. Applying a voltage (V)109 to the gate polysilicon layer 104, a large amount of charge accumulates on the surface of the gate oxide layer. Because of the surface instability, the channel region under the gate oxide layer 102 is not easy to generate, causing the data delay phenomenon.
It was found that most of the total number of silicon-hydrogen bonds have weakerbonding force and are not related to each other but are proportional to each other. Therefore, by reducing the total number of silicon-hydrogen bond bonds over the entire area of the gate oxide, a gate oxide with significantly high electrical reliability can be obtained.
For these reasons, a method of forming a polysilicon layer using deuterium during semiconductor fabrication is desired to obtain better stability between the oxide layer and the polysilicon layer.
Disclosure of Invention
In view of the above-mentioned shortcomings of conventional MOS transistor fabrication processes, the present invention provides a method for forming a polysilicon layer using deuterium during semiconductor fabrication process, which can increase the surface stability problem during conventional fabrication process.
The main objective of the present invention is to provide a method for forming a polysilicon layer by using deuterium during the semiconductor manufacturing process, which can increase the stability of the surface of the gate oxide layer.
Another object of the present invention is to provide a method for forming a polysilicon layer using deuterium during semiconductor fabrication, which can achieve better electrical performance in the semiconductor structure.
In accordance with the above objects, a method for forming a polysilicon layer using deuterium during semiconductor fabrication is disclosed. First, a semiconductor substrate is provided, wherein the semiconductor substrate has a dielectric layer thereon. Silane containing chlorine and deuterium is then decomposed to form a polysilicon layer over the dielectric layer.
The objects and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments, when taken in conjunction with the accompanying drawings.
Drawings
FIG. 1A is a cross-sectional view of a prior art MOS structure;
FIG. 1B shows the use of SiH4The source gas is bonded on the surface of the grid oxide layer;
FIG. 1C is a side cross-sectional view of a MOS transistor with a voltage applied to the gate oxide;
FIG. 2A is a cross-sectional view of a preferred embodiment of the present invention, relating to a method for forming a polysilicon layer by using deuterium in a semiconductor manufacturing process;
FIG. 2B is a schematic diagram of using SiD2Cl2Or SiDCl3The source gas and the surface bonding molecular structure diagram of the grid oxide layer;
fig. 2C is a cross-sectional view of a mos transistor with a voltage applied to the gate oxide.
Detailed Description
While the present invention has been described in terms of a preferred embodiment, it will be appreciated by those skilled in the art that numerous variations of the steps, materials and impurities may be substituted for those skilled in the art, and that such substitutions are expressly not intended to depart from the spirit and scope of the present invention.
The present invention will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present invention, the cross-sectional view of the semiconductor structure will be partially enlarged in the semiconductor manufacturing process without being scaled to a general scale for the purpose of illustration, but should not be construed as limiting. In addition, in actual manufacturing, three-dimensional dimensions of length, width and depth should be included.
Referring to fig. 2A, first, a semiconductor substrate 200, such as a silicon substrate, is provided. Then, a gate oxide layer 202 is formed on the semiconductor substrate 200, wherein the thickness of the gate oxide layer 202 is about 100-300 angstroms. The gate oxide layer 202 may be a silicon dioxide layer formed by thermal oxidation or chemical vapor deposition, such as pecvd, apcvd and lpcvd. Then, a gate polysilicon layer 204 is formed on the gate oxide layer 202, wherein the thickness of the gate polysilicon layer 204 is about 2000-3000 angstroms. The gate polysilicon layer 204 is formed by low pressure chemical vapor deposition using silane containing chlorine and deuterium as a reactive gas at about temperature600-800 ℃. In the preferred embodiment, the polysilicon layer uses SiD with better properties2Cl2Or SiDCl3Is a reactive gas. Due to the use of SiD2Cl2Or SiDCl3The gas is a reactive gas that stabilizes between the gate oxide layer 202 and the gate oxide layer surface of the gate polysilicon layer 204.
For example, polysilicon layer 204 is formed by chemical vapor deposition in a deuterium containing state, replacing the conventional hydrogen reactant by a deuterium analog. Growing a polysilicon layer 204 by low pressure chemical vapor deposition and passing through the SiD2Cl2Or SiDCl3Is a reactive gas. The process of growing the polysilicon layer 204 by low pressure chemical vapor deposition is carried out at a system temperature of about 600-800 deg.C and a system pressure of about 100-500 torr using SiD of about 0-500 sccm2Cl2Or 0to 500sccmSiDCl3The source gas of (1). The deposition reaction equation is:
or
Referring to fig. 2B, a molecular architecture diagram is shown in which a floating bond occurs between the gate oxide layer 202 and the polysilicon layer 204. The silicon-deuterium bonds on the surface of the gate oxide layer and the surface of the gate polysilicon layer can obtain better electrical property. In particular, silicon-deuterium bonds are formed more stably than silicon-hydrogen bonds on the surface of the gate oxide layer 202. Thus, when a voltage is applied to the polysilicon layer 204, no charge will accumulate at the interface between the gate oxide layer 202 and the gate polysilicon 204, which can be terminated by deuterium in the silicon-deuterium bond. Therefore, it is very useful to use deuterium atoms in the gate polysilicon 204 to stabilize the surface structure.
Referring to fig. 2C, which is a diagram of the MOS structure after the partial etching and spacer formation in fig. 2A, a semiconductor substrate 200, a gate oxide layer 202 and a polysilicon layer 204 are sequentially formed. Spacers 206 are formed on the sidewalls of the polysilicon layer 204, and ions are implanted into the semiconductor substrate 200 using the polysilicon layer 204 and the spacers 206 as masks to form source/drain regions 208. And applying a voltage (V) to the polysilicon layer 204 to complete the cross-sectional view of the MOS transistor. Due to the problem posed by FIG. 2B, SiD is used2Cl2Or SiDCl3The gas is a reactive gas so as to be stable between the gate oxide layer 202 and the gate oxide layer surface of the gate polysilicon layer 204. By applying a voltage 209 to the top of the gate polysilicon layer 204, a large amount of charge does not accumulate on the surface of the gate oxide layer. Because of the stability of the surfaceAnd thus, a channel region under the gate oxide layer 202 is easily generated.
The method for forming a polysilicon layer by using deuterium in the semiconductor manufacturing process provided by the method of the present invention has the following advantages:
1. a method for forming a polysilicon layer using deuterium during semiconductor fabrication is provided, which can increase the stability of the surface of a gate oxide layer.
2. A method for forming a polysilicon layer using deuterium during semiconductor fabrication is provided to achieve better electrical performance in semiconductor structures.
The above description is only an example of the present invention, and is not intended to limit the scope of the present invention; it is intended that all such equivalent changes and modifications be included within the scope of the appended claims without departing from the spirit of the invention.

Claims (10)

1、一种在半导体制作过程中形成多晶硅的方法,该方法至少包含:1. A method for forming polysilicon in a semiconductor manufacturing process, the method at least comprising: 提供具有介电层的半导体衬底;以及providing a semiconductor substrate having a dielectric layer; and 分解包含氯与氘的硅烷以形成多晶硅层在该介电层上。The silane containing chlorine and deuterium is decomposed to form a polysilicon layer on the dielectric layer. 2、根据权利要求1所述的方法,其中所述的介电层在该介电层与该多晶硅层之间包含硅-氘键。2. The method of claim 1, wherein the dielectric layer includes silicon-deuterium bonds between the dielectric layer and the polysilicon layer. 3、根据权利要求1所述的方法,其中上述的包含氯与氘的硅烷至少包含SiD2Cl23. The method according to claim 1, wherein said silane containing chlorine and deuterium contains at least SiD 2 Cl 2 . 4、根据权利要求1所述的方法,其中上述的包含氯与氘的硅烷至少包含SiDCl34. The method according to claim 1, wherein said silane containing chlorine and deuterium contains at least SiDCl3 . 5、根据权利要求1所述的方法,其中上述的多晶硅层是采用低压化学气相沉积法形成。5. The method according to claim 1, wherein said polysilicon layer is formed by low pressure chemical vapor deposition. 6、一种在半导体制作过程中利用氘以形成多晶硅的方法,该方法至少包含:6. A method of utilizing deuterium to form polysilicon in a semiconductor manufacturing process, the method comprising at least: 提供具有二氧化硅层的半导体衬底;以及providing a semiconductor substrate having a silicon dioxide layer; and 分解包含氯与氘的硅烷气体以形成多晶硅层在该二氧化硅层上。A silane gas containing chlorine and deuterium is decomposed to form a polysilicon layer on the silicon dioxide layer. 7、根据权利要求6所述的方法,其中所述的氧化层在该氧化层与该多晶硅层之间包含硅-氘键。7. The method of claim 6, wherein the oxide layer contains silicon-deuterium bonds between the oxide layer and the polysilicon layer. 8、根据权利要求6所述的方法,其中上述的包含氯与氘的硅烷至少包含SiD2Cl28. The method of claim 6, wherein said silane containing chlorine and deuterium contains at least SiD 2 Cl 2 . 9、根据权利要求6所述的方法,其中上述的包含氯与氘的硅烷至少包含SiDCl39. The method of claim 6, wherein said silane containing chlorine and deuterium contains at least SiDCl3 . 10、根据权利要求6所述的方法,其中上述的多晶硅层是采用低压化学气相沉积法形成。10. The method according to claim 6, wherein said polysilicon layer is formed by low pressure chemical vapor deposition.
CNB011326743A 2001-09-06 2001-09-06 Method for forming polysilicon layer by deuterium in semiconductor manufacturing process Expired - Fee Related CN1158693C (en)

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CN100552955C (en) * 2003-03-28 2009-10-21 旺宏电子股份有限公司 Floating gate memory cell and method of making same
US6881636B2 (en) * 2003-07-03 2005-04-19 Micron Technology, Inc. Methods of forming deuterated silicon nitride-containing materials
CN102376573B (en) * 2010-08-10 2013-08-14 中芯国际集成电路制造(上海)有限公司 NMOS transistor and formation method thereof
CN106884203A (en) * 2015-12-15 2017-06-23 上海新昇半导体科技有限公司 The forming method of monocrystal silicon and wafer

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