CN115843179B - Semiconductor structure and manufacturing method thereof, and memory - Google Patents
Semiconductor structure and manufacturing method thereof, and memory Download PDFInfo
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- CN115843179B CN115843179B CN202111050625.5A CN202111050625A CN115843179B CN 115843179 B CN115843179 B CN 115843179B CN 202111050625 A CN202111050625 A CN 202111050625A CN 115843179 B CN115843179 B CN 115843179B
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
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Abstract
本申请实施例涉及半导体领域，提供一种半导体结构及其制作方法、存储器，半导体结构至少可以包括：自下向上堆叠且设置于不同光刻层中的第一光栅、第二光栅以及第三光栅，不同所述光刻层中用于设置光栅的套刻标记区域重叠，所述第一光栅、所述第二光栅以及所述第三光栅均为周期性结构，所述周期性结构中相邻所述光栅的中心距离为光栅周期，所述第一光栅与所述第二光栅的光栅宽度和/或所述光栅周期不同。本申请实施例有利于提升半导体结构的电学性能。
The embodiments of the present application relate to the semiconductor field, and provide a semiconductor structure and a manufacturing method thereof, and a memory. The semiconductor structure may at least include: a first grating, a second grating, and a third grating stacked from bottom to top and arranged in different photolithography layers, the overlay mark areas for setting the gratings in different photolithography layers overlap, the first grating, the second grating, and the third grating are all periodic structures, the center distance between adjacent gratings in the periodic structure is the grating period, and the grating width and/or the grating period of the first grating and the second grating are different. The embodiments of the present application are conducive to improving the electrical performance of the semiconductor structure.
Description
Technical Field
The embodiment of the application relates to the field of semiconductors, in particular to a semiconductor structure, a manufacturing method thereof and a memory.
Background
Photolithography is a process in which a reticle pattern is transferred to a wafer through a series of steps such as alignment, exposure, etc. In the process of manufacturing a semiconductor device, a plurality of photolithography processes are generally required to be used for realizing alignment, and as various factors on the photolithography processes cannot reach an ideal state, patterns remained on a wafer after exposure and development cannot be completely aligned with existing patterns on the wafer, so that offset, namely an alignment error (overlay), between the patterns remained on the wafer after exposure and development and the existing patterns on the wafer needs to be accurately measured, and the alignment error can be effectively compensated and corrected in a subsequent process, so that the finally obtained semiconductor device has an expected effect.
Disclosure of Invention
The embodiment of the application provides a semiconductor structure, a manufacturing method thereof and a memory, which are at least beneficial to improving the electrical properties of the semiconductor structure and the memory.
According to some embodiments of the present application, an aspect of the present application provides a semiconductor structure, where the semiconductor structure may at least include a first grating, a second grating, and a third grating stacked from bottom to top and disposed in different lithography layers, different alignment mark regions in the lithography layers for disposing the gratings overlap, the first grating, the second grating, and the third grating are all periodic structures, a center distance between adjacent gratings in the periodic structures is a grating period, and grating widths and/or grating periods of the first grating and the second grating are different.
In addition, the first grating and the second grating are in adjacent different ones of the photolithographic layers.
In addition, the first grating, the second grating and the third grating are all composed of gaps, bumps or holes which are arranged periodically.
In addition, the photoetching layer comprises a core area and a peripheral area, the peripheral area is positioned between the core area and the cutting channel, and the overlay mark area is positioned in the peripheral area.
In addition, the semiconductor structure further comprises a first pattern and a second pattern which are positioned in the core area, wherein the first pattern and the first grating are positioned in the same photoetching layer, the second pattern and the second grating are positioned in the other photoetching layer, the first grating and the first pattern are of grating structures with the same grating width and grating period, and the second grating and the second pattern are of grating structures with different grating widths and/or grating periods.
In addition, the first pattern includes a word line.
In addition, the second pattern includes a capacitive contact hole.
In addition, the grating width and the grating period of the second grating are the same as those of the third grating.
In addition, the center position of the second grating is offset from the center position of the first grating in the vertical direction, and the second grating does not overlap with the first grating in the vertical direction.
In addition, the grating period of the second grating is larger than that of the first grating, and the center position of the second grating is used as the center position of part of gratings in the first grating.
In addition, the grating width of the second grating is larger than the grating width of the first grating.
In addition, the grating width of the second grating is less than or equal to twice the grating width of the first grating.
According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a memory, including the semiconductor structure described in any one of the above.
According to some embodiments of the present application, another aspect of the present application provides a method for manufacturing a semiconductor structure, where the method at least includes forming a first grating, a second grating, and a third grating stacked from bottom to top and disposed in different lithography layers, overlapping overlay mark areas in the different lithography layers for disposing the gratings, where the first grating, the second grating, and the third grating are all periodic structures, and a center distance between adjacent gratings in the periodic structures is a grating period, and grating widths or the grating periods of the first grating and the second grating are different.
In addition, the method further comprises the step of forming a second pattern, wherein the second grating and the second pattern are positioned on the same photoetching layer, the second pattern and the second grating are of grating structures with different grating periods, and the grating width of the second grating is larger than that of the second pattern.
The technical scheme provided by the embodiment of the application has at least the following advantages:
In the technical scheme, the grating widths and/or grating periods of the first grating and the second grating are different, so that the characteristics of diffraction signals obtained by illuminating the first grating and the second grating are different, the diffraction signals of the first grating and the diffraction signals of the second grating are distinguished, the whole of the diffraction signals of the first grating and the diffraction signals of the second grating are prevented from being used as the diffraction signals of the second grating, the diffraction signals for calculating the overlay error are ensured to be composed of the diffraction signals of the second grating and the diffraction signals of the third grating, and further the accurate measurement of the overlay error is realized.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise.
Fig. 1 to fig. 4 are schematic structural views of a semiconductor structure according to an embodiment of the present application;
fig. 5 to 9 are schematic structural views illustrating a part of steps in a method for manufacturing a semiconductor structure according to an embodiment of the present application.
Detailed Description
The detection of overlay error is generally divided into post-development detection (After Development Insprection, ADI) and post-etching detection (AFTER ETCHING Inspection, AEI), wherein the post-development detection refers to post-development Critical Dimension (CD) measurement, and is generally used for detecting performance indexes of an exposure machine and a development machine, and after exposure and development are completed, the generated pattern is qualitatively checked by an ADI machine to determine whether the pattern is normal, and because the pattern cannot be measured by transmitted light, ADI is generally measured by means of electron beams or scanning electron microscope, etc., and the post-etching detection refers to post-etching CD measurement, and full Inspection or sampling Inspection is respectively carried out on the product before and after photoresist removal in an etching process.
Overlay errors can generally be measured by image recognition based measurement techniques (Image Based Overlay, IBO), scanning electron microscopy (Scanning Electron microscope, SEM) and novel diffraction measurement techniques (In Die Metrology, IDM). The IDM collects zero-order diffraction light rays of different marking layers and determines overlay errors of the different marking layers according to the asymmetry of the light intensity distribution of the zero-order diffraction light rays.
The embodiment of the application provides a semiconductor structure, wherein a first grating and a second grating are provided with different grating widths and/or grating periods, so that diffraction signals corresponding to the first grating and diffraction signals corresponding to the second grating can be distinguished, when the overlay error of a third grating relative to the second grating is measured, the first grating below the second grating is also provided with corresponding diffraction signals, and the diffraction signals corresponding to the first grating and the diffraction signals corresponding to the second grating are controlled to have different characteristics, so that the diffraction signals for calculating the overlay error are only composed of the diffraction signals of the second grating and the diffraction signals of the third grating, and further accurate measurement of the overlay error is realized.
Embodiments of the present application will be described in detail below with reference to the attached drawings. However, it will be understood by those of ordinary skill in the art that in various embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the present application. The claimed application may be practiced without these specific details and with various changes and modifications based on the following embodiments.
Fig. 1 to fig. 4 are schematic structural diagrams of a semiconductor structure according to an embodiment of the present application.
Referring to fig. 1, the semiconductor structure includes a first grating 111, a second grating 211, and a third grating 311 stacked from bottom to top and disposed in different photolithography layers, overlapping alignment mark regions of the gratings disposed in the different photolithography layers, where the first grating 111, the second grating 211, and the third grating 311 are periodic structures, and a center distance of adjacent gratings in the periodic structures is a grating period, and grating widths and/or grating periods of the first grating 111 and the second grating 211 are different.
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings.
The semiconductor structure comprises a first photoetching layer 10, a second photoetching layer 20 and a third photoetching layer 30 which are stacked from bottom to top, wherein the first photoetching layer 10 is provided with a first overlay mark region 11, the second photoetching layer 20 is provided with a second overlay mark region 21, the third photoetching layer 30 is provided with a third overlay mark region 31, the first grating 111 is positioned in the first overlay mark region 11, the second grating 211 is positioned in the second overlay mark region 21, the third grating 311 is positioned in the third overlay mark region 31, the first grating 111, the second grating 211 and the third grating 311 are all overlay marks, and the projections of the first overlay mark region 11 and the second overlay mark region 21 at least partially coincide in the stacking direction of the photoetching layers.
It will be appreciated that due to the limited chip area, the overlay mark areas of different layers tend to overlap in the film stacking direction, and that when the overlay error of the upper layer is measured using the IDM, the measurement result may be affected by the lower layer. An exemplary scenario is as follows:
When the light irradiates above the third photoetching layer 30, part of light rays penetrate through the third photoetching layer 30 and are reflected, the reflected light is diffracted by the third grating 311 to form a third diffraction signal, part of light rays sequentially penetrate through the third photoetching layer 30 and the second photoetching layer 20 and are reflected, the reflected light is diffracted by the second grating 211 to form a second diffraction signal, and part of light rays sequentially penetrate through the third photoetching layer 30, the second photoetching layer 20 and the first photoetching layer 10 and are reflected, and the reflected light is diffracted by the first grating 111 to form a first diffraction signal. When the first grating 111 and the second grating 211 are periodic structures with the same grating width and grating period, the features of the first diffraction signal and the second diffraction signal are the same, and the technician cannot effectively distinguish the first diffraction signal and the second diffraction signal, and only can use the first diffraction signal and the second diffraction signal as the second diffraction signal, that is, when the overlay error between the third grating 311 and the second grating 211 is measured, the overlay error between the equivalent structures of the first grating 111 and the second grating 112 and the third grating 311 is actually measured.
If the first grating 111 and the second grating 211 are perfectly aligned, the first diffraction signal is identical to the second diffraction signal, the first diffraction signal will not interfere with the recognition of the second diffraction signal by the technician, and if the first grating 111 and the second grating 211 deviate, the actual positions of the first diffraction signal and the second diffraction signal are different, but since the first diffraction signal and the second diffraction signal are identical to each other except for the positions (width and pitch), the technician cannot distinguish the first diffraction signal from the second diffraction signal, and only the whole of the first diffraction signal and the second diffraction signal can be regarded as the "second diffraction signal", and at this time, the measurement result may deviate.
It can be appreciated that as the deviation between the first grating 111 and the second grating 211 gradually expands, the accuracy of the measurement results becomes lower. Ideally, the first grating 111 and the second grating 211 are perfectly aligned, and the measured offset is the same as or similar to the actual offset, for example, the difference is not more than 0.5nm, and as the difference between the first grating 111 and the second grating 211 is enlarged to 2.5nm or even 5nm, the difference between the measured offset and the actual offset may be enlarged to 1nm or even 2nm, and the measured offset is basically ineffective.
It should be noted that, the second diffraction signal will also transmit through the third photolithographic layer 30, and the first diffraction signal will also transmit through the second photolithographic layer 20 and the third photolithographic layer 30, but since the first diffraction signal and the second diffraction signal are not parallel light rays and the grating width is generally much larger than the grating slit, most of the first diffraction signal and the second diffraction signal are transmitted out of the upper film layer and are not diffracted again, so that the positions of the first diffraction signal and the second diffraction signal will not change or change slightly, and the signal intensity (blocked by the film layer and weakened by the signal intensity) will mainly change. In addition, since the measured offset is a relative value (with respect to zero offset), the effects of the second and third lithography layers 20 and 30 are eliminated by the subtraction of the relative values.
In the embodiment of the present application, the third lithography layer 30 is a lithography layer to be tested, the second lithography layer 20 is a reference lithography layer, the first lithography layer 10 is an existing interference lithography layer, the first lithography layer 10 and the second lithography layer 20 are adjacent or not adjacent lithography layers, and the second lithography layer 20 and the third lithography layer 30 are adjacent or not adjacent lithography layers.
In some embodiments, the first photolithographic layer 10 and the second photolithographic layer 20 are adjacent, that is, the first grating 111 and the second grating 211 are adjacent different photolithographic layers, when the first photolithographic layer 10 and the second photolithographic layer 20 are adjacent, the light intensity loss suffered by the transmission of the first diffraction signal to the upper side of the second photolithographic layer 20 is smaller, the influence on the second diffraction signal is larger, and at this time, the signal characteristics of the second diffraction signal need to be adjusted with a larger amplitude to effectively distinguish the first diffraction signal and the second diffraction signal.
In some embodiments, referring to fig. 2, the first grating 111 and the second grating 211 are in separate different lithography layers, at least a fourth lithography layer 40 is further disposed between the first lithography layer 10 and the second lithography layer 20, the fourth lithography layer 40 has a fourth overlay mark region 41 and a fourth grating 411 disposed in the fourth overlay mark region 41, the fourth grating 411 is disposed between the first grating 111 and the second grating 211, the alignment direction of the first grating 111 is parallel to the alignment direction of the second grating 211, and the alignment direction of the fourth grating 411 is perpendicular to the alignment direction of the second grating 211. The fourth grating 411 is advantageous for reducing light transmitted to the first photolithographic layer 10 and suppressing propagation of the first diffraction signal onto the second photolithographic layer 20, so that the first diffraction signal that is finally transmitted out of the third photolithographic layer 30 has a lower light intensity, thereby reducing or even eliminating the influence of the first diffraction signal on the second diffraction signal.
It will be appreciated that other intermediate layers may be disposed between the first photolithographic layer 10 and the second photolithographic layer 20, and the first grating 111 and the second grating 211 may be less distinguished if the light intensity loss of the first diffraction signal in the propagation process is greater and the influence of the first diffraction signal is smaller. That is, the characteristic difference between the first grating 111 and the second grating 211 may be adjusted according to the loss of the first diffraction signal during transmission, and the characteristic difference may include a grating width difference and/or a grating period difference.
In different embodiments, the grating may have different manifestations. The grating may be comprised of periodically arranged gaps, bumps or holes or the grating may comprise periodically arranged gaps, bumps or holes. It will be appreciated that, under the influence of the fabrication process, the middle part of the grating generally follows a more strict periodic distribution, i.e. the spacing of adjacent gratings is equal, the periodicity of the edge parts of the grating is poor, and the distance between adjacent gratings may show a tendency to become larger or smaller gradually, which is a phenomenon that is limited by the state of the art and therefore cannot be taken as evidence of not belonging to the grating.
In addition, it is understood that the same overlay mark region may have multiple sets of gratings, where the multiple sets of gratings have at least two alignment directions for detecting the offset of the lithography layer to be tested in different directions compared to the reference lithography layer, and the alignment directions of the different sets of gratings may be perpendicular or oblique. When the overlay mark includes an array of holes, the overlay mark may be considered to include multiple groups of gratings with different arrangement directions, and a common hole is formed between the two groups of gratings.
In some embodiments, the photolithographic layer includes a core region and a peripheral region, the peripheral region being located between the core region and the scribe line, and the overlay mark region being located within the peripheral region. The peripheral region generally refers to a blank region between the core component and the scribe line, and as the semiconductor structure is miniaturized and the core component is complicated, the area of the blank region may be gradually reduced, and the overlay marks of different film layers may be more likely to overlap in the film stacking direction. It will be appreciated that the first overlay mark region 11, the second overlay mark region 21, and the third overlay mark region 31 all belong to the overlay mark regions and are located in the peripheral region.
In some embodiments, the semiconductor structure further includes a first pattern 112 and a second pattern 212 in the core region, the first pattern 112 being in the same lithographic layer as the first pattern 111, the second pattern 212 being in another lithographic layer as the second pattern 211, the first pattern 111 being a grating structure having the same grating width and grating period as the first pattern 112, the second pattern 211 being a grating structure having a different grating width and/or grating period than the second pattern 212. That is, the embodiment of the present application makes the diffraction signal of the second grating 211 different from the diffraction signal of the first grating 111 by adjusting the grating width and/or the grating period of the second grating 211, so as to accurately obtain the offset of the second lithography layer 20 and the third lithography layer 30 according to the diffraction signal of the second grating 211 and the diffraction signal of the third grating 311.
In order to accurately measure the overlay error of the second lithography layer 20 and the third lithography layer 30, the grating width and the grating period of the second grating 211 may be set to be the same as the grating width and the grating period of the third grating 311, and in this context, if the grating width and/or the grating period of the second grating 211 are adjusted, the grating width and/or the grating period of the third grating 311 need to be adjusted synchronously, so as to ensure that the measurement of the overlay error has higher accuracy. Since the process steps of the peripheral region are the same as those of the core region, and the first grating 111 is at the bottom layer relative to the second grating 211 and the third grating 311, the characteristics of the first grating 111 are kept unchanged to adjust the second grating 211 and the third grating 311, which is beneficial to reducing the influence on the subsequent film process steps and reducing the adjustment cost.
In other embodiments, the second grating 211 and the second pattern 212 are grating structures with the same grating width and grating period, and the first grating 111 and the first pattern 112 are grating structures with different grating widths and/or grating periods, that is, the grating width and/or grating period of the first grating 111 are adjusted, so that the grating width and the grating period of the second grating 211 are kept unchanged. Since the number of the film layers between the first photolithography layer 10 and the second photolithography layer 20 and between the second photolithography layer 20 and the third photolithography layer 30 may be different according to the application scenario, in the actual process, the characteristics of the first grating 111 or the characteristics of the second grating 211 and the third grating 311 may be adjusted according to the actual needs, so as to reduce the influence on the overall film process and reduce the cost.
In some embodiments, referring to fig. 3, the center position aa of the second grating 211 is offset from the center position bb of the first grating 111 in the vertical direction, and the second grating 211 does not overlap with the first grating 111 in the vertical direction. In the case that the center position bb of the first grating 111 is shifted from the center position aa of the second grating 211, by controlling the second grating 211 not to overlap with the first grating 111 in the vertical direction, it is advantageous to avoid overlapping of diffraction signals caused by overlapping of gratings, thereby accurately distinguishing the first diffraction signal from the second diffraction signal. The vertical direction refers to the stacking direction of the first photolithography layer 10 and the second photolithography layer 20, the central position of the gratings refers to the central axis or the central axial surface of each grating in the alignment direction of the gratings, and the plurality of gratings form the first grating 111, the second grating 211, and the third grating 311.
In some embodiments, the second grating 211 does not overlap with the first grating 111 in the vertical direction, which means that there is a gap between the first grating 111 and the second grating 211 in the arrangement direction of the first grating 111, so that it is beneficial to further distinguish the first diffraction signal from the second diffraction signal, and avoid that the first diffraction signal and the second diffraction signal cannot be distinguished due to continuity, and in other embodiments, the second grating 211 does not overlap with the first grating 111 in the vertical direction, which means that the first grating 111 coincides with the second grating 211 in the arrangement direction of the first grating 111.
In some embodiments, the center positions of the gratings in the second pattern 212 are offset from the center positions of the gratings in the first pattern 112 in a vertical direction, and the second pattern 212 at least partially overlaps the first pattern 112 in the vertical direction. It will be appreciated that if the grating features of the second grating 211 are different from those of the second pattern 212, the second pattern 212 and the second grating 211 cannot be formed by the same mask, so that the peripheral region may be covered first to form the second pattern 212 of the core region during the actual manufacturing process, and the second grating 211 of the peripheral region may be formed later after covering the core region. That is, the second pattern 212 and the second grating 211 are formed using different exposure and development processes, respectively.
In some embodiments, referring to fig. 4, the grating period of the second grating 211 is greater than the grating period of the first grating 111, and the center position of the second grating 211 serves as the center position of a portion of the gratings in the first grating 111. In the case where the center position of the second grating 211 is the center position of the first grating 111, controlling the first grating 111 to have a different grating period from the second grating 211 is advantageous in distinguishing the first diffraction signal and the second diffraction signal formed based on the first grating 111 and the second grating 211.
With continued reference to fig. 4, in some embodiments, the grating width of the second grating 211 is greater than the grating width of the first grating 111, and further adjustment of the grating width of the second grating 211 based on changing the grating period of the second grating 211 facilitates further differentiation of the first diffraction signal from the second diffraction signal, and in other embodiments, the grating width of the second grating 211 is less than the grating width of the first grating 111. Taking the second grating 211 as an example, the grating width of the second grating 211 is the width d of each grating in the grating arrangement direction.
In some embodiments, the grating width of the second grating 211 is less than or equal to twice the grating width of the first grating 111, or the grating width of the second grating 211 is less than or equal to twice the grating width of the second pattern 212. The arrangement of the grating width of the second grating 211 and the grating width of the second pattern 212 have the relationship, which is beneficial to forming the second pattern 212 and the second grating 211 by using the same process step, reduces the influence of the adjustment of the second grating 211 on the film preparation process, and reduces the process cost of the semiconductor structure.
In some embodiments, the first pattern 112 includes a word line, which may be a buried word line, for example, and in some embodiments, the second pattern 212 may be a bit line conductive layer or a capacitive contact hole.
In the embodiment of the application, the grating widths and/or grating periods of the first grating and the second grating are different, so that the characteristics of diffraction signals obtained by illuminating the first grating and the second grating are different, the diffraction signals of the first grating and the diffraction signals of the second grating are distinguished, the whole of the diffraction signals of the first grating and the diffraction signals of the second grating are prevented from being used as the diffraction signals of the second grating, the diffraction signals for calculating the overlay error are ensured to be composed of the diffraction signals of the first grating and the diffraction signals of the second grating, and further, the accurate measurement of the overlay error is realized.
Correspondingly, the embodiment of the application also provides a memory, which comprises the semiconductor structure. The offset of the photoetching layer where the second grating is and the photoetching layer where the third grating is can be accurately measured by the semiconductor structure, and then the offset is adjusted and corrected by the subsequent process, so that the memory prepared based on the semiconductor structure has better electrical performance.
Correspondingly, the embodiment of the application also provides a manufacturing method of the semiconductor structure, referring to fig. 1, the manufacturing method of the semiconductor structure comprises the steps of forming a first grating 111, a second grating 211 and a third grating 311 which are stacked from bottom to top and are arranged in different photoetching layers, overlapping alignment mark areas for arranging the gratings in the different photoetching layers, wherein the first grating 111, the second grating 211 and the third grating 311 are all periodic structures, the center distance of adjacent gratings in the periodic structures is a grating period, and the grating widths or the grating periods of the first grating 111 and the second grating 211 are different.
In some embodiments, referring to fig. 4, the second pattern 212 and the second grating 211 are formed by different exposure, development and etching processes, respectively, the second grating 211 and the second pattern 212 are located on the same lithography layer, the second pattern 212 and the second grating 211 are grating structures with different grating periods, and the grating width of the second grating 211 is greater than the grating width of the second pattern 212.
The method comprises the following steps:
Referring to fig. 4 and 5, the first mask 212a and the second mask 211a are formed by exposing and developing, respectively, using different masks, the first mask 212a is used to form the second pattern 212, the second mask 211a is used to form the second grating 211, a deposition process is performed while forming the pattern layer 212b and the grating layer 211b, and when the width of the opening of the second mask 211a is less than or equal to twice the thickness of the pattern layer 212b, the grating layer 211b fills the opening of the second mask 211 a. In an exemplary embodiment, the opening width of the second mask 211a is greater than the thickness of the pattern layer 212b and less than or equal to twice the thickness of the pattern layer 212 b.
Referring to fig. 6, a maskless dry etching process is performed to remove the pattern layer 212b covering the top surface of the first mask 212a and at the bottom of the opening of the first mask 212a, form a first sacrificial layer 212c, and remove the grating layer 211b higher than the top surface of the second mask 211a, form a second sacrificial layer 211c.
Referring to fig. 7, an etching process is performed to remove the first mask 212a and the second mask 211a, leave the first sacrificial layer 212c and the second sacrificial layer 211c, and a deposition process is performed to form a third mask 212d filling the gaps of the first sacrificial layer 212c and a fourth mask 211d filling the gaps of the second sacrificial layer 211 c.
Since the opening width of the second mask 211a is greater than the thickness of the pattern layer 212b and less than or equal to twice the thickness of the pattern layer 212b, and the opening width of the first mask 212a is greater than twice the thickness of the pattern layer 212b, the opening width of the first mask 212a is greater than the opening width of the second mask 211a, and in order to make the opening width of the second mask 211a smaller in the case of the overall total width unchanged, it is necessary to set the width of a single mask stripe in the second mask 211a to be greater than the width of a single mask stripe in the first mask 212a, that is, the opening width of the third mask 212d is smaller than the opening width of the fourth mask 211d, the grating width of the third mask 212d is smaller than the grating width of the fourth mask 211d, and the period of the third mask 212d is smaller than the period of the fourth mask 211d, and the third mask 212d and the fourth mask 211d are used to etch the underlying conductive layer 51 to form the bit line conductive layer.
Referring to fig. 8, the first sacrificial layer 211c and the second sacrificial layer 212c are removed, and the conductive layer 51 is etched using the third mask 212d and the fourth mask 211d to form a first bit line conductive layer 512 located in the functional region and a second bit line conductive layer 511 located in the peripheral region. Since the grating features of the first bit line conductive layer 512 are the same as those of the third mask 212d, the grating features of the second bit line conductive layer 511 are the same as those of the fourth mask 211d, and thus the opening width of the first bit line conductive layer 512 is smaller than that of the second bit line conductive layer 511.
Referring to fig. 9, a first sidewall 513 is formed on the sidewall of the first bit line conductive layer 512, a second sidewall 514 is formed on the sidewall of the second bit line conductive layer 511, a first capacitor contact hole filling the gap between adjacent first bit line conductive layers 512 is formed as the second pattern 212, and a second capacitor contact hole filling the gap between adjacent second bit line conductive layers 511 is formed as the second grating 211.
The first sidewall 513 and the second sidewall 514 may be formed by the same deposition process, and the thickness of the first sidewall 513 and the thickness of the second sidewall 514 are the same. In the case where the opening width of the first bit line conductive layer 512 is smaller than the opening width of the second bit line conductive layer 511 and the thickness of the first sidewall 513 is the same as the thickness of the second sidewall 514, the grating width of the second pattern 212 is smaller than the grating width of the second grating 211.
In addition, the first capacitor contact hole and the second capacitor contact hole can also be formed by adopting the same deposition process, the first capacitor contact hole of the functional area is used for connecting with the drain electrode of the word line so as to play a role in electric connection, and the second capacitor contact hole of the peripheral area can not be connected with the drain electrode of the word line and can be used only as an overlay mark. The buried word line 60 of the functional region may serve as a first pattern, and the buried word line 60 of the peripheral region may serve as a first grating.
In other embodiments, after the first bit line conductive layer and the second bit line conductive layer are formed, the first bit line conductive layer and the second bit line conductive layer are processed in-situ to form first sidewalls and second sidewalls for isolation, such as doped polysilicon of the bit line conductive layer, the doped polysilicon is oxidized or nitrided to form silicon oxide or silicon nitride for electrical isolation, and after the first sidewalls and the second sidewalls are formed, a conductive material may be filled to form the first capacitor contact hole and the second capacitor contact hole. In this case, the width of the first capacitance contact hole is equal to the thickness of the pattern layer, and the width of the second capacitance contact hole is equal to the opening width of the second mask, that is, the width of the second capacitance contact hole is greater than the width of the first capacitance contact hole and less than or equal to twice the width of the first capacitance contact hole.
The width of the first capacitor contact hole may be equal to the width of the embedded word line, in which case the width of the second capacitor contact hole is greater than the width of the embedded word line and less than or equal to twice the width of the embedded word line.
In the embodiment of the application, the grating widths and/or grating periods of the first grating and the second grating are different, so that the characteristics of diffraction signals obtained by illuminating the first grating and the second grating are different, the diffraction signals of the first grating and the diffraction signals of the second grating are distinguished, the whole of the diffraction signals of the first grating and the diffraction signals of the second grating are prevented from being used as the diffraction signals of the second grating, the diffraction signals for calculating the overlay error are ensured to be composed of the diffraction signals of the first grating and the diffraction signals of the second grating, and further, the accurate measurement of the overlay error is realized.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of carrying out the application and that various changes in form and details may be made therein without departing from the spirit and scope of the application. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the application, and the scope of the application is therefore intended to be limited only by the appended claims.
Claims (11)
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| CN202111050625.5A CN115843179B (en) | 2021-09-08 | 2021-09-08 | Semiconductor structure and manufacturing method thereof, and memory |
| PCT/CN2022/093536 WO2023035658A1 (en) | 2021-09-08 | 2022-05-18 | Semiconductor structure and manufacturing method therefor, and memory |
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| CN111324019A (en) * | 2020-02-25 | 2020-06-23 | 上海华力集成电路制造有限公司 | Measurement identifier and measurement method for simultaneously obtaining overlay accuracy between multiple layers |
| CN112230514A (en) * | 2020-10-23 | 2021-01-15 | 泉芯集成电路制造(济南)有限公司 | Overlay error measurement mark structure and process method thereof, and overlay error measurement method |
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| US7193715B2 (en) * | 2002-11-14 | 2007-03-20 | Tokyo Electron Limited | Measurement of overlay using diffraction gratings when overlay exceeds the grating period |
| CN100456142C (en) * | 2006-10-18 | 2009-01-28 | 上海微电子装备有限公司 | Alignment mark and its producing method |
| CN106154765B (en) * | 2015-04-23 | 2018-12-21 | 中芯国际集成电路制造(上海)有限公司 | Alignment measuring device |
| KR102640173B1 (en) * | 2016-06-14 | 2024-02-26 | 삼성전자주식회사 | Diffraction based overlay mark and metrology method |
| CN109828440B (en) * | 2019-03-26 | 2021-04-13 | 上海华力集成电路制造有限公司 | Overlay mark based on diffraction and overlay error measuring method |
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| CN111324019A (en) * | 2020-02-25 | 2020-06-23 | 上海华力集成电路制造有限公司 | Measurement identifier and measurement method for simultaneously obtaining overlay accuracy between multiple layers |
| CN112230514A (en) * | 2020-10-23 | 2021-01-15 | 泉芯集成电路制造(济南)有限公司 | Overlay error measurement mark structure and process method thereof, and overlay error measurement method |
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