CN115833818A - Power supply selection circuit supporting three-way input - Google Patents

Abstract

The invention relates to a power supply selection circuit structure supporting three-way input applied in a multi-power supply chip. For the power selection circuit built into the multi-power chip, the power supply voltage usually needs to be selected from multiple power supplies in the system. The selection principle is generally to select the power supply with the highest voltage as the output, which can be used as the control of the subsequent power supply module. Substrate for logic power supplies and power transistors. The power supply selection circuit proposed by the present invention can support three input power sources, it directly compares and judges the input of the three power sources and controls the corresponding switch tubes, which can reduce the size requirements of the switch tubes, and ensure that the error of the selected highest level value is small, And it can still generate reliable output power after any two power supplies are powered off.

Description

A Power Selection Circuit Supporting Three Inputs

technical field

The invention is a power selection circuit, plays a crucial role in a power management system, and belongs to the field of analog circuit design.

Background technique

The current chip is different according to the power consumption and precision requirements of the subsystem. Generally, there are multiple built-in LDOs (low dropout linear voltage regulators), so there will be multiple internal power supplies, resulting in some circuit power supplies that need to be changed in different modes. Different LDO power supply requirements, the gate control signal of the power transistor of these power supply circuits and the substrate connection need to be guaranteed to be at the highest level, in order to prevent various abnormal short circuits and leakage, so the design can be between multiple power supply voltages Circuits that generate the highest level of power are necessary.

The previous power supply selection circuit mainly focused on the selection of VBAT and VCC, which is usually a selection circuit between two power supplies. If the selection of three input power supplies can be used in cascade, the original two-way power supply selection will be used, but it will cause the selection Switches are used in series, compared with the power supply selection circuit of the present invention with three-way input, under the same switch size and load current situation, the loss of two-way power supply selection cascaded use on the switch tube is twice that of the present invention; For noise and reliability considerations, power supply selection generally has a hysteresis window, and the hysteresis window covers the amplitude of the noise. As a result, the selected highest level may not be the highest level, but is lower than the actual highest level. In the case of noise considerations, the hysteresis voltage is doubled when the two power supplies are cascaded and used, so the selected highest level is twice the voltage value lower than the actual highest level in this patent.

The three-way input power supply selection circuit of the present invention directly compares and judges the three-way power supply input and controls the switch tube, which can reduce the size requirement of the switch tube and ensure that the error of the selected highest level value is small.

Contents of the invention

(1) Purpose of the invention

The traditional power supply selection circuit generally only provides two-way power supply selection structure. For multi-way power supplies, it generally only provides the connection method and selection target of the switch tube, and does not give how to select the high level of the multi-way power supply. For three-way input power supply Although the traditional two-power supply selection circuit can be used, first select between the two power supplies, and then select the result of the selection with the third power supply. Since the final output is a series connection of two-stage switch tubes, the power switching loss Large, if you want to reduce the loss, you need to increase the width-to-length ratio of the power switch and increase the area. At the same time, because the comparison results are superimposed twice, the comparison hysteresis window is doubled, resulting in a large error in the selected highest level. . I have invented a power selection circuit supporting three-way input, which can reduce switch loss and selection error.

(2) Technical solution

Three input power sources A/B/C are input to the power supply voltage comparison circuit to realize the comparison of the sizes of the three input power sources. The power supply voltage comparison circuit has three built-in comparator modules, CMP1, CMP2 and CMP3. Among them, the positive terminal of CMP1 The positive and negative terminals of CMP2 are respectively connected to power supply B and power supply C, and the positive and negative terminals of CMP3 are respectively connected to power supply C and power supply A; the output QAB of CMP1 represents the power supply of A and B Comparison results, QAB=1 means A is higher than B, QAB=0 means A is lower than B, the output QBC of CMP2 represents the comparison result of B and C, QBC=1 means B is higher than C, QBC=0 means B is lower than C , the output QCA of CMP3 represents the comparison result between C and A, QCA=1 represents that C is higher than A, and QCA=0 represents that C is lower than A, and the comparison result is output to the next highest voltage decision circuit. Among them, the built-in comparator module is composed of a hysteresis comparator, a power-down pull-up branch and a shaping inverter, and the power-down pull-up branch is to connect two gate connections between the output of the hysteresis comparator and the power supply voltage The PMOS transistors of the input signal are connected in series, which is used to pull the output of the hysteresis comparator to high level when both inputs of the comparator are powered off, so as to avoid its output high-impedance state and ensure that the shaping stage will not leak and the output state is uncontrollable

The highest voltage judgment circuit obtains the highest voltage value by logically judging the results of the power supply voltage comparison circuit, and makes logical judgments on 8 possibilities of the output result states of QAB, QBC, and QCA. When A is the highest level, QAB=1 , QCA=0, when B is the highest level, QBC=1, QAB=0, when C is the highest level, QCA=1, QBC=0, when A, B, C are the same, QAB, QBC, QCA will be It is 0 or 1 at the same time, so the highest voltage judgment circuit obtains GA0 by performing reverse NAND on QAB and QCA, obtains GB0 by performing reverse NAND on QBC and QAB, and obtains GC0 by performing reverse NAND on QCA and QBC; GA0, GB0 And the signal after GC0 NAND and GA0 get GPA after passing through AND gate, GB0 and '1' get GPB after passing through AND gate, GC0 and '1' get GPC after passing through AND gate, GPA, GPB, GPC are control A, B , The gate control voltage original signal of the PMOS switch tube of the C three-way power supply, the judgment circuit ensures that under any circumstances, only the gate voltage corresponding to the highest level power supply is low level, and the other two gate voltages are high level, and output the result to the next stage selection buffer delay circuit.

The selection buffer delay circuit selects the gate control voltage original signals GPA, GPB, and GPC of the PMOS transistors given by the highest voltage judgment circuit, and delays GPA, GPB, and GPC by cascaded delay units by one Td, two Tds, or even The delayed signals GPA<N:1>, GPB<N:1>, and GPC<N:1> of N Tds are output to the next-stage switch selection transistor.

The switch selection tube is mainly divided into 3 sets of switch tubes connected to power supply A, B and C. Among them, the switch tube connected to power supply A is connected in series with two PMOS tubes whose gates are connected to B and C, and N gates are connected to GPA< The PMOS transistors of N:1> are connected in parallel, and the switching transistor connected to power supply B is connected in series by two PMOS transistors whose gates are connected to C and A, and N gates are connected in parallel to the PMOS transistors of GPB<N:1>, connected to the power supply C The switch tube consists of two PMOS tubes whose gates are connected to A and B in series, and N PMOS tubes whose gates are connected to GPC<N:1> in parallel; the drains of the three sets of switch tubes are connected together to form the selected power supply VO, And all PMOS substrates are connected to VO. The series connection of PMOS transistors on each power supply is to automatically select the highest voltage when the power is turned on, but due to the threshold value of the PMOS transistor, the highest level may have a threshold loss, and the remaining multiple parallel switch transistors By the multi-level delay control provided by the delay circuit, the main switching tube is slowly turned on and the purpose of reducing the switching overshoot is achieved.

Description of drawings

The structure of the power supply selection circuit supporting three-way input of the present invention of Fig. 1

Fig. 2 power supply voltage comparator circuit and highest voltage decision circuit of the present invention

Fig. 3 selects buffer delay circuit and selects switch tube circuit of the present invention

Fig. 4 comparator circuit of the present invention

Detailed ways

The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations thereof such as "includes" or "includes" and the like will be understood to include the stated elements or constituents, and not Other elements or other components are not excluded.

As shown in FIG. 1, it is a power supply selection circuit structure supporting three-way input according to a specific embodiment of the present invention. The structure includes a selection circuit consisting of a power supply voltage comparison circuit, a maximum voltage judgment circuit, a selection buffer delay circuit and a selection switch tube. The power supply voltage comparison circuit realizes the comparison of the size of the three input power supplies A/B/C, and obtains three comparison output results; the three comparison results are input to the highest voltage judgment circuit of the next stage, and the highest voltage judgment circuit passes through the power supply The result of the voltage comparison circuit is logically judged. Based on the principle of selecting the highest voltage value, three switches are output to select the original signal of the gate control voltage of the PMOS transistor. The selection buffer delay circuit delays the original gate control voltage signal of the switch selection PMOS transistor given by the highest voltage decision circuit to obtain a multi-level delay control signal. The switch selection tube selects the multi-level delay control signal provided by the buffer delay circuit to control multiple switch tubes to slowly turn on the main switch tube and reduce switching overshoot.

Fig. 2 is a power supply voltage comparison circuit and a highest voltage decision circuit according to a specific embodiment of the present invention.

The three built-in comparator modules in the power supply voltage comparison circuit compare the size of the three input power sources. Among them, QAB represents the comparison result between A and B, QAB=1 means that A is higher than B, and QAB=0 means that A is higher than B Low, QBC represents the comparison result of B and C, QBC=1 represents B is higher than C, QBC=0 represents B is lower than C, QCA represents the comparison result of C and A, QCA=1 represents C is higher than A, QCA=0 It means that C is lower than A. Therefore, the output results of the three comparators will present the following possibilities:

(1) QAB=0, QBC=0, QCA=0: means A≤B, B≤C, C≤A, indicating that the voltage difference between the three voltages of A/B/C is within the hysteresis of the comparator Within the window, the difference between the three voltages is very small;

(2) QAB=0, QBC=0, QCA=1: means A≤B, B≤C, C≥A, then C is the highest voltage;

(3) QAB=0, QBC=1, QCA=0: means A≤B, B≥C, C≤A, then B is the highest voltage;

(4) QAB=0, QBC=1, QCA=1: means A≤B, B≥C, C≥A, then B is the highest voltage;

(5) QAB=1, QBC=0, QCA=0: means A≥B, B≤C, C≤A, then A is the highest voltage;

(6) QAB=1, QBC=0, QCA=1: means A≥B, B≤C, C≥A, then C is the highest voltage;

(7) QAB=1, QBC=1, QCA=0: means A≥B, B≥C, C≤A, then A is the highest voltage;

(8) QAB=1, QBC=1, QCA=1: means A≥B, B≥C, C≥A, indicating that the voltage difference between the three voltages of A/B/C is within the hysteresis of the comparator Within the window, the difference between the three voltages is very small;

For the cases of (1) and (8), any one of A/B/C can be selected, and it is determined to choose A during implementation.

The highest voltage judgment circuit outputs GPA, GPB, GPC, GB0 after performing some logic processing on QAB, QBC, and QCA. Among them, GPA represents the original control voltage of the gate of the PMOS switch connected to the A power supply, and GPB represents the gate control voltage connected to the B power supply. The gate original control voltage of the PMOS switch tube, GPC represents the gate original control voltage of the PMOS switch tube connected to the C power supply;

Choose A power supply, then GPA=0, GPB=1, GPC=1;

Select B power supply, then GPA=1, GPB=0, GPC=1;

Choose C power supply, then GPA=1, GPB=1, GPC=0;

The truth table and logical control relationship of the two levels of coordination are as follows.

QAB QBC QCA GA0 GB0 GC0 GPA GPB GPC Remark 0 0 0 1 1 1 0 1 1 The comparator is all 0, preferably A 0 0 1 1 1 0 1 1 0 QBC＝0, QCA＝1->C is the highest, choose C 0 1 0 1 0 1 1 0 1 QAB＝0, QBC＝1->B is the highest, choose B 0 1 1 1 0 1 1 0 1 QAB＝0, QBC＝1->B is the highest, choose B 1 0 0 0 1 1 0 1 1 QAB＝1, QCA＝0->A is the highest, choose A 1 0 1 1 1 0 1 1 0 QBC＝0, QCA＝1->C is the highest, choose C 1 1 0 0 1 1 0 1 1 QAB＝1, QCA＝0->A is the highest, choose A 1 1 1 1 1 1 0 1 1 Comparators are all 1s, preferably A

Among them, the added comparator is a special treatment when all 0s and all 1s. This situation shows that the three voltages are very close, and the deviations are all within the hysteresis window of a comparator. A is preferred to ensure that only Strobe all the way.

GPB=GB0&TIE1

GPC=GC0&TIE1

Fig. 3 is a selection buffer delay circuit and a switch selection tube according to a specific embodiment of the present invention.

Select the buffer delay circuit to obtain delay signals GPA<N:1>, GPB<N: 1>, GPC<N:1>.

The final switch selection tube is mainly divided into 3 sets of switch tubes connected to power supply A, B and C. Among them, the switch tube connected to power supply A is connected in series with two PMOS tubes whose gates are connected to B and C, and N gates are connected to GPA The PMOS tubes of <N:1> are connected in parallel, and the switching tube connected to the power supply B is connected in series by two PMOS tubes whose gates are connected to C and A, and connected in parallel with N gates connected to the PMOS tubes of GPB<N:1>, connected to the power supply C The switching tubes of the switch tube are connected in series by two PMOS tubes whose gates are connected to A and B, and connected in parallel with N PMOS tubes whose gates are connected to GPC<N:1>; the drains of the three sets of switching tubes are connected together to form the selected power supply VO , and all PMOS substrates are connected to VO. Among them, the two PMOS series branches are directly strobed when the power supply voltage difference is greater than the threshold of the MOS transistor. When the power supply voltage difference is smaller than the threshold of a MOS transistor, the selection signal provided by the previous stage is required to control the gating.

Among them, the comparator in the power supply voltage comparison circuit can adopt the structure shown in Figure 4 to avoid the hysteresis comparator outputting a high-impedance state when the two input power sources are not powered, resulting in leakage of the post-stage shaping stage and uncontrollable output state.

To sum up, through the above technical solutions and implementation methods, the present invention realizes direct comparison and judgment of the three power supply inputs and controls the switching tubes, which can reduce the size requirements of the switching tubes and ensure that the error of the selected highest level value is small. At the same time, the circuit structure and implementation mode can also be extended to a power supply selection circuit with four inputs or even more inputs.

Claims (5)

1. The power supply selection circuit supporting three-way input is characterized by comprising a power supply voltage comparison circuit, a highest voltage judgment circuit, a selection buffer delay circuit and a selection switch tube, wherein:

the power supply voltage comparison circuit compares the sizes of three input power supplies A, B, C and outputs 3 compared results QAB, QBC and QCA to the next highest voltage judgment circuit as input;

the highest voltage judgment circuit obtains a highest voltage value by carrying out logic judgment on the results QAB, QBC and QCA of the power supply voltage comparison circuit, outputs original signals GPA, GPB and GPC of grid control voltage of the 3-way switch selection PMOS tube and provides the original signals GPA, GPB and GPC to a next-stage selection buffer delay circuit as input;

the selection buffer delay circuit delays the original grid control voltage signals GPA, GPB and GPC of the switch selection PMOS tube given by the highest voltage judgment circuit to obtain multi-stage delay control signals GPA < N:1>, GPB < N:1> and GPC < N:1>, and the multi-stage delay control signals are provided for the next stage of switch selection tube circuit to be used as control input;

the switch selection tube controls the multi-stage delay control signals GPA < N:1>, GPB < N:1> and GPC < N:1> provided by the selection buffer delay circuit to be connected with the grid electrodes of a plurality of parallel switch tubes of the power supply A, B, C, and the purposes of slowly opening any one main switch tube and reducing switching overshoot are achieved.

2. The power supply selection circuit according to claim 1, wherein the power supply voltage comparison circuit has three comparator modules built in, CMP1, CMP2 and CMP3, wherein the positive terminal of CMP1 is connected to input power supply a, the negative terminal of CMP1 is connected to input power supply B, the positive terminal of CMP2 is connected to input power supply B, the negative terminal of CMP2 is connected to input power supply C, the positive terminal of CMP3 is connected to input power supply C, and the negative terminal of CMP3 is connected to input power supply a; output QAB of CMP1 characterizes the comparison result of a and B, QAB =1 represents a higher than B, QAB =0 represents a lower than B, output QBC of CMP2 characterizes the comparison result of B and C, QBC =1 represents B higher than C, QBC =0 represents B lower than C, output QCA of CMP3 characterizes the comparison result of C and a, QCA =1 represents C higher than a, and QCA =0 represents C lower than a.

3. The power selection circuit of claim 1, wherein the highest voltage decision circuit nands the QAB and QCA to obtain GA0, nands the QBC and QAB to obtain GB0, and nands the QCA and QBC to obtain GC0; performing AND gate on the signals subjected to NAND of GA0, GB0 and GC0 and GA0 to obtain GPA, performing AND gate on GB0 and '1' to obtain GPB, and performing AND gate on GC0 and '1' to obtain GPC; GPA represents the original grid control voltage of the PMOS switching tube connected with the power supply A, GPB represents the original grid control voltage of the PMOS switching tube connected with the power supply B, and GPC represents the original grid control voltage of the PMOS switching tube connected with the power supply C.

4. The power selection circuit of claim 1, wherein the selection buffer delay circuit obtains delay signals GPA < N:1>, GPB < N:1>, GPC < N:1> with a Td,2 Td or more to N Td by respectively passing GPA, GPB and GPB through cascaded delay units, and the switch selection tube of the rear stage is mainly divided into 3 sets of switch tubes connecting power supplies A, B and C, wherein the switch tube connecting power supply a is connected in series by 2 PMOS tubes with gates connecting B and C, and the PMOS tubes with gates connecting GPA < N:1> are connected in parallel, the switch tube connecting power supply B is connected in series by 2 PMOS tubes with gates connecting C and a, and the PMOS tubes with gates connecting GPB < N:1> are connected in parallel, and the switch tube connecting power supply C is connected in series by 2 PMOS tubes with gates connecting a and B, and the PMOS tubes with gates connecting GPC < N:1> are connected in parallel; the drains of the 3 sets of switching tubes are connected together to form a selected power supply VO, and all PMOS substrates are connected with the VO.

5. The power supply voltage comparison circuit of claim 2, wherein the built-in comparator module comprises a hysteresis comparator, a power down pull-up branch and a shaping inverter, wherein the power down pull-up branch is formed by connecting 2 PMOS transistors of which the grid electrodes are connected with input signals in series between the output of the hysteresis comparator and the power supply voltage, and is used for pulling the output of the hysteresis comparator to be high level under the condition that two inputs of the comparator are powered down, so as to avoid the output of the hysteresis comparator from being in a high impedance state, and ensure that the shaping stage cannot leak electricity and the output state is uncontrollable.

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