CN115828590B - A method for modeling and simulating processor radiation effects - Google Patents
A method for modeling and simulating processor radiation effectsInfo
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Abstract
一种处理器辐照效应模型建模与仿真系统构建方法，先选择或设计处理器，获取处理器指令集数据与架构数据；再根据处理器指令集数据与架构数据提取处理器内核数据，根据处理器内核数据建立处理器内核模型；然后根据处理器指令集数据与架构数据提取处理器外设数据，根据处理器外设数据建立处理器外设模型；再实现处理器内核模型与外设模型时间同步与数据传输功能，完成处理器常态模型建模与仿真系统构建；然后根据辐照效应引发的故障处理器类型，修改处理器内核模型与处理器外设模型；最后根据辐照效应故障发生位置与概率函数，建立处理器辐照效应模型；本发明反应处理器的行为特性，简化模型复杂度，实现模拟辐照效应带来的处理器器件退化的功能。
A method for constructing a processor radiation effect model and simulation system comprises the following steps: first, selecting or designing a processor, and obtaining processor instruction set data and architecture data; then, extracting processor core data based on the processor instruction set data and architecture data, and establishing a processor core model based on the processor core data; then, extracting processor peripheral data based on the processor instruction set data and architecture data, and establishing a processor peripheral model based on the processor peripheral data; then, implementing time synchronization and data transmission functions between the processor core model and the peripheral model, and completing the construction of a processor normal model model and simulation system; then, modifying the processor core model and the processor peripheral model based on the type of faulty processor caused by the radiation effect; and finally, establishing a processor radiation effect model based on the location and probability function of the radiation effect fault. The present invention reflects the behavioral characteristics of the processor, simplifies the model complexity, and realizes the function of simulating processor device degradation caused by the radiation effect.
Description
Technical Field
The invention belongs to the technical field of modeling of an integrated circuit radiation effect model, and particularly relates to a processor radiation effect modeling and simulation system construction method.
Background
At present, with the rapid development of semiconductor technology, various simulation and device models are widely applied to the fields of aerospace, nuclear industry, particle physics and the like, are positioned in the radiation environments of various electromagnetic and high-energy particles, are influenced by various radiation effects such as total dose radiation, single particle radiation, transient effect and the like, and have serious test on the working reliability and life cycle.
In recent years, with the development of computer simulation technology, the radiation effect simulation of an electronic system provides powerful support for radiation-resistant design and theoretical research of the system, so that the development period is shortened, and the development cost is reduced. Aiming at a processor device, the conventional method ([1]Qureshi Y M,Simon W A,Zapater M,et al.Gem5-X:A Many-core Heterogeneous Simulation Platform for Architectural Exploration and Optimization[J].ACM Transactions on Architecture and Code Optimization,2021(4).) based on RTL function modeling has higher precision, however, the structures of different architecture processors have huge differences and the kernel implementation is complex, the adoption of the RTL function modeling method ([2]PowerProbe:Run-time power modeling through automatic RTL instrumentation[C]//2018Design,Automation&Test in Europe Conference&Exhibition(DATE),2018,pp.743-748.) requires internal details of the processor, the novel processor kernel data relates to intellectual property information and is difficult to obtain, and meanwhile, the method for modeling the processor kernel is difficult and requires long time. Some processing organ parties provide netlist files for researchers to simulate, and basic simulation of general functions of a processor can be completed based on the netlist files, however, the simulation speed is low through the netlist files, the netlist files are not suitable for simulation of complex scenes, and meanwhile, the netlist files are difficult to change and irradiation effect fault injection is difficult to carry out.
In summary, the existing method for modeling the irradiation effect of the processor device model has the problems and defects that (1) in the existing method for modeling the irradiation effect of the device model, the model design difficulty is high, the calculation cost is high, the simulation circuit scale is limited, meanwhile, because the model relates to manufacturer intellectual property information, the required data for modeling is difficult to obtain, (2) the key parts of most open source models are difficult to change, the irradiation effect cannot be added on the basis, the irradiation effect model cannot be built, and (3) the virtual machine technology greatly improves the simulation efficiency, but the detailed modeling of the working details of the processor is difficult.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a modeling and simulation system construction method for a processor irradiation effect model, which not only can reflect the behavior characteristics of a processor in detail, but also can simplify the complexity of the model, greatly improves the simulation speed compared with an RTL model, and can perform data bit overturning and data bit clamping fault injection on an internal register structure, an on-chip storage structure and an external storage structure of the processor model, and can realize the function of simulating the degradation of a processor device caused by irradiation effect by matching with a self-defined fault position and a fault probability algorithm, thereby providing a way and a reference for the irradiation resistance design and research of the device model.
In order to achieve the above purpose, the invention adopts the following technical scheme:
a method for constructing a processor irradiation effect model modeling and simulation system comprises the following steps:
step 1, selecting or designing a processor;
step 2, acquiring instruction set data and architecture data of a processor;
step 3, extracting processor kernel data according to the processor instruction set data and the architecture data;
step 4, establishing a processor kernel model according to the processor kernel data;
Step 5, extracting processor peripheral data according to the processor instruction set data and the architecture data;
step 6, establishing a processor peripheral model according to the processor peripheral data;
step 7, realizing the time synchronization and data transmission functions of the processor kernel model and the peripheral model, and completing the modeling of the normal model of the processor and the construction of a simulation system;
step 8, modifying a processor kernel model and a processor peripheral model according to the processor fault type caused by the irradiation effect;
and 9, establishing a processor radiation effect model according to the radiation effect fault occurrence position and the probability function.
The function of the step 1 and the step 2 is to obtain instruction set data and architecture data of a certain definite processor to prepare for the following modeling work, and the data collection method of the processor comprises the steps of adopting a digital verification simulation method such as UVM and the like or a method for directly programming and testing a real device, and combining a processor architecture official data manual to measure the instruction set data and the processor architecture data of the processor.
The step 3 is used for summarizing and extracting data required by processor kernel modeling, preparing for subsequent processor kernel modeling, analyzing the processor instruction set data and architecture data obtained in the step 2, and extracting various data required by building a processor kernel model, wherein the various data comprise processor instruction set data, processor internal register structure data, processor on-chip memory structure data, processor internal integer and floating point arithmetic unit data, processor interrupt mechanism data and other data related to processor functions.
The function of step 4 is to build a processor core model by which the basic functional simulation around the processor pipeline is embodied, and based on the data obtained in step 3, to build the following data structures or functions:
4.1 Building a physical storage structure of the structure body simulation processor, and mapping various storage structures such as internal registers, on-chip storage and the like of the processor to a host memory;
4.2 Establishing kernel function according to each function of the processor, including register read-write, integer data operation, memory access and other function functions;
4.3 According to the working principle of the processor pipeline, establishing a pipeline simulation function from instruction fetch to execution, and simulating the pipeline work of the processor through a function sequence calling mechanism based on an event queue;
4.4 Based on the processor interrupt control mechanism, establishing an interrupt simulation function simulating the processor interrupt;
The method comprises the following basic functions of instruction fetching, instruction decoding, disassembling and function executing, wherein the instruction fetching is used for acquiring an execution instruction of the cycle according to an execution result of the previous instruction cycle, the instruction decoding is used for calling a corresponding disassembling function and a function executing function according to a value result of the instruction fetching, the disassembling function is used for accessing a target according to an instruction decoding result and the instruction, the disassembling function is used for disassembling an assembly instruction corresponding to the instruction, and the function executing function is used for calling a corresponding function according to a decoding result, so that the function simulation of a processor kernel is realized.
And step 5, the function of the step is to summarize and extract the data required by modeling the processor peripheral equipment so as to prepare for the subsequent modeling of the processor peripheral equipment, and the step 2 is to analyze the data of the instruction set and the architecture data of the processor so as to extract the data required by establishing the processor peripheral equipment model, wherein the data comprise the processor on-chip interconnection bus protocol data, the interrupt manager data, the processor on-chip and off-chip setting data and the processor external function interface mapping data.
The function of step 6 is to build a processor peripheral model, which includes a processor on-chip bus management structure model, a processor interrupt controller model, and a processor functional peripheral, the three models being a series of necessary units to simulate the basic functions of the processor, and the building of the models being accomplished through hardware description language modeling.
The step 7 is used for constructing a joint simulation platform for joint simulation of a processor kernel model and a processor peripheral model, so as to construct a complete processor simulation model and a simulation system under a non-radiation environment, wherein the processor kernel model is modeled by a host function and a host memory based on a high-level language and occupies an independent simulation process, and the processor peripheral model is modeled by a hardware description language and can be operated on various commercial or non-commercial hardware simulation platforms, namely, also occupies an independent simulation process.
Because the processor kernel model and the processor peripheral model established by the high-level language and the hardware description language are respectively simulated under two processes, a simulation process synchronization mechanism based on a process communication mechanism of a host is established, and the simulation process synchronization mechanism has the functions of a time synchronization mechanism, a data transmission mechanism and a data transmission mechanism, wherein the time unit of pushing simulation time under the processor peripheral model is mapped into the execution number of processor instructions under the kernel model, and the memory access data of the processor kernel model and the bus time sequence of the processor peripheral model are mutually mapped (comprising an address line, a control line and a data line).
The function of the step 8 is to add fault models of various data storage modules in the processor core and the peripheral in the irradiation environment, provide support for processor device degradation caused by simulation irradiation effect, and according to data bit overturn, data bit clamping and data transmission delay faults possibly caused by the processor in the actual working environment, add a register and an on-chip memory data modification function in the processor core model to provide a fault injection function, and add a bus delay module, a clamping fault injection module and a bit overturn module in the processor peripheral model.
The step 9 is to build an irradiation effect fault injection module according to the irradiation effect occurrence position and the occurrence probability function, the module supports the simulation of different fault positions and different fault types in the simulation process by adding a random fault injection script or a serial fault injection script, and finally the module is added into a processor simulation model in a non-radiation environment to build a processor irradiation effect model.
The invention has the beneficial effects that as the method of combining simulation by separating modeling of the processor kernel and the peripheral equipment is adopted, the general kernel simulation model can be built for the processor with the specified instruction set, and meanwhile, the peripheral equipment simulation model with fine granularity can be built according to the difference of the specific architecture of the processor. The method simplifies the modeling flow of the processor model, and simultaneously, the built model has higher simulation speed compared with an RTL model, and supports the radiation effect fault injection and simulation of an internal register structure, an on-chip memory structure, a peripheral device and a bus of the processor. The invention provides model support for the function simulation of the electronic system in the irradiation environment.
Drawings
FIG. 1 is a flow chart of an embodiment of the present invention.
FIG. 2 is a schematic diagram of a processor core model according to an embodiment of the invention.
FIG. 3 is a segment of a processor core runtime instruction execution record in accordance with an embodiment of the present invention.
FIG. 4 is a segment of a processor core runtime register data record in accordance with an embodiment of the present invention.
FIG. 5 is a schematic diagram of a processor peripheral model in accordance with an embodiment of the present invention.
Fig. 6 is a waveform illustrating the result of performing an irradiation effect bit flip fault injection on a processor AHB bus portion in accordance with an embodiment of the present invention.
FIG. 7 is a waveform showing the result of irradiation effect continuous bit flip fault injection on a processor interrupt signal line portion in accordance with an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following examples and the accompanying drawings. It should be understood that the embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.
As shown in fig. 1, a method for constructing a processor irradiation effect model modeling and simulation system includes the following steps:
s101, selecting or designing a processor device;
s102, acquiring instruction set data and architecture data of a processor;
s103, extracting processor kernel data according to the processor instruction set data and the architecture data;
s104, establishing a processor kernel model according to the processor kernel data;
s105, extracting processor peripheral data according to the processor instruction set data and the architecture data;
s106, establishing a processor peripheral model according to the processor peripheral data;
S107, realizing the time synchronization and data transmission functions of the processor kernel model and the peripheral model, and completing the modeling and simulation system construction of the normal model of the processor;
s108, modifying a processor kernel model and a processor peripheral model according to the type of the fault processor caused by the irradiation effect;
s109, establishing a processor radiation effect model according to the radiation effect fault occurrence position and the probability function.
In embodiment 1, a Sparcv architecture Leon3 processor is used as a testing and modeling device, and in order to obtain the working data of the original electronic device, a method of directly measuring the real device is adopted to combine a Leon3 architecture official data manual and a sparc instruction set official manual to obtain the necessary modeling data, wherein the necessary modeling data comprises instruction set corresponding codes, instruction classification and various instruction functions, interrupt mechanism and interrupt jump table, register structure, instruction delay slot mechanism and the like. And then analyzing the obtained processor instruction set and architecture data, extracting the instruction coding and instruction functions of the target instruction set, the number of windows of general registers of the processor and a switching mechanism, floating point operation rules and operation flow of the processor, registers and working modes related to interrupt skipping of the processor, and data related to a skip instruction delay slot mechanism of the processor. Based on the obtained data, the following data structures or functions should be established:
(1) Building a physical storage structure of a structural body simulation processor, and mapping various storage structures such as internal registers, on-chip storage and the like of the processor to a host memory;
(2) Establishing kernel function functions according to various instruction functions in an instruction set, including various Sparcv instruction set related function functions such as register read-write, floating point number data operation, external memory access, interrupt return and the like;
(3) According to the working principle of the processor pipeline, a pipeline simulation function from instruction fetch to execution is established, and the pipeline simulation function comprises the following basic functions of instruction fetch function, instruction decoding function, disassembly function and function execution function, so that the function simulation of the processor kernel is realized.
In addition, based on the memory requirement of the processor in actual operation, the virtual on-chip memory is regarded as a part of the processor kernel, a virtual on-chip memory structure model is established, and the kernel function unit is supported to directly access the data of the on-chip memory model through function call. By the method, the built processor kernel model structure is shown in fig. 2, the kernel simulator occupies an independent process to simulate the pipeline work of the processor, can simulate Sparcv the basic operation of an instruction set, records the instruction execution sequence and register data change in the operation process, and part of instruction execution records and register data records are respectively shown in fig. 3 and 4.
And then analyzing the initially obtained processor instruction set and architecture data to determine the inter-chip bus protocol data of the processor, wherein in the embodiment, the processor adopts an AHB and APB communication protocol, the working mode of the processor interrupt controller comprises a priority judging mode and an interrupt reserving and clearing mechanism, the information of the internal and external of the processor chip comprises register address allocation and function allocation of functional peripheral equipment such as serial port peripheral equipment, I2C peripheral equipment and timer peripheral equipment, and the processor maps external functional interfaces. And establishing a processor peripheral model by using a hardware description language according to the obtained data. In the embodiment, the target spark architecture processor adopts an AHB and APB protocol to complete communication between the processor core and the peripheral, the processor is provided with an independent interrupt controller which accords with the spark architecture requirement, and the processor comprises two serial peripheral, a timer peripheral with a specific structure and a 1553B protocol communication peripheral. In this embodiment, the peripheral and interrupt controller model is built using Verilog language, and an AHB-APB bridge model is designed, the modeling method has the advantage of supporting the expansion of open source IP or user IP of various peripheral devices on a processor bus in the subsequent development. The simulation of the processor peripheral model occupies an independent process, and the simulation is completed through ModelSim, and the structural schematic diagram of the simulation is shown in fig. 5.
A simulation process synchronization mechanism based on a process communication mechanism of a host is established between a processor kernel model and a processor peripheral model, and the simulation process synchronization mechanism comprises the steps of adding a time synchronization function and a data transmission function under the processor kernel model, wherein the time synchronization function is responsible for time synchronization with the processor peripheral model, the data transmission function is responsible for transmitting processor access data to an external access process and receiving peripheral return data, adding a special kernel connection module under the processor peripheral model, the module is responsible for receiving the access data from the processor kernel model, unpacking the data and transmitting the access data to the processor peripheral model, and the module is also responsible for packaging and transmitting data returned by the processor peripheral model and interrupt signal data to the processor kernel model, and meanwhile, the module is responsible for simulation time synchronization of the processor kernel model and the peripheral model.
And then, establishing fault models of various data storage modules in the processor core and the peripheral equipment in the irradiation environment, and adding the fault models into corresponding models, so as to provide support for processor device degradation caused by the simulation irradiation effect. According to possible data bit overturn, data bit clamping and data transmission delay faults of a processor under an actual working environment, a register and an on-chip memory data modification function are added in a processor kernel model to provide a fault injection function, and a bus delay module, a clamping fault injection module and a bit overturn module are added in a processor peripheral model.
And finally, combining test data, and establishing an irradiation effect fault injection module according to the irradiation effect occurrence position and the occurrence probability function, wherein the module supports the simulation of different fault positions and different fault types in the simulation process by adding a random fault injection script or a sequential fault injection script, and finally, the module is added into a processor simulation model to obtain the processor irradiation effect model. In this embodiment, irradiation fault injection is performed on the AHB communication part and the interrupt signal transmission part of the peripheral of the processor, where the AHB communication part performs partial bit flip fault injection on the data of the address bus, which is shown in that the lower four bits of the address line are affected to become 0x2, and continuous bit flip faults are added to the interrupt signal transmission part, which is shown in that the waveform of the signal line is continuously flipped within a period of time, and the waveform diagrams of the fault injection result are shown in fig. 6 and 7.
Claims (6)
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| CN106503285A (en) * | 2016-09-14 | 2017-03-15 | 西安电子科技大学 | A kind of circuit irradiation effect modeling method based on VHDL AMS |
| CN108226748A (en) * | 2017-12-05 | 2018-06-29 | 上海精密计量测试研究所 | For the single particle effect test method of SoC systems on chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106503285A (en) * | 2016-09-14 | 2017-03-15 | 西安电子科技大学 | A kind of circuit irradiation effect modeling method based on VHDL AMS |
| CN108226748A (en) * | 2017-12-05 | 2018-06-29 | 上海精密计量测试研究所 | For the single particle effect test method of SoC systems on chip |
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