CN115811829A - Circuit board and manufacturing method thereof - Google Patents

Abstract

A circuit board includes a first conductive layer on the outside, and the first conductive layer includes a plurality of first connection pads. An insulating bump protrudes from each first connection pad, the surface of the bump is covered with a metal layer, and the metal layer is connected to the first connection pad. The present application also provides a manufacturing method of the above-mentioned circuit board.

Description

Circuit board and manufacturing method thereof

technical field

The invention relates to the field of circuit boards, in particular to a circuit board with conductive columns and a manufacturing method thereof.

Background technique

The surface of the circuit board has a plurality of welding pads for welding with various electronic components (such as chips). Under the trend of high density, the welding pads are getting smaller and smaller. In order to improve the welding yield and reliability, a method of using copper pillars instead of welding pads for welding is proposed. The copper pillars protrude from the conductive layer on the surface of the circuit board and are formed by electroplating. However, in industrial production, limited by electroplating equipment (such as traditional gantry type or vertical continuous electroplating equipment) and liquid medicine, the uniformity of electroplating is relatively poor; Uniformity, resulting in uneven distribution of current density generated during electroplating, resulting in a large difference in height of multiple copper pillars formed by electroplating, which cannot meet the requirements of packaging.

Contents of the invention

In view of this, the present invention provides a method for manufacturing a circuit board and a circuit board formed by the method to solve the above-mentioned technical problems.

The first aspect of the present application provides a circuit board, including a first conductive layer on the outside, and the first conductive layer includes a plurality of first connection pads. An insulating bump protrudes from each first connection pad, the surface of the bump is covered with a metal layer, and the metal layer is connected to the first connection pad.

The second aspect of the present application provides a method for manufacturing a circuit board, comprising the following steps:

providing a circuit substrate, including a first metal layer on the outside;

forming an insulating layer on the first metal layer;

removing a portion of the insulating layer to form a plurality of insulating bumps;

forming a metal layer on the surface of the bump, wherein the metal layer is connected to the first metal layer;

A circuit is fabricated on the first metal layer to form a first conductive layer, wherein the first conductive layer includes a plurality of first connection pads, and each first connection pad is connected to a corresponding metal layer.

In the circuit board and its manufacturing method provided by the present application, a plurality of bumps are formed by removing part of the insulating layer, and a metal layer is electroplated on the surface of the bumps to obtain a conductive column. The conductive column formed by electroplating shortens the electroplating layer and time, improves the electroplating efficiency, and improves the consistency of the height of the conductive column. And when the conductive pillars are connected with electronic components, the bumps can provide hard support.

Description of drawings

1 to 10 are schematic cross-sectional views of a manufacturing process of a circuit board according to an embodiment of the present application.

Description of main component symbols

circuit board 100

Double-sided substrate 10

Blind hole 101

first metal layer 11

First insulating layer 12

third metal layer 13

Conductive Structures 102

third conductive layer 130

Second insulating layer 21

Second metal layer 22

Circuit board 30

Insulation 40

Bump 41

metal layer 42

first conductive layer 110

second conductive layer 120

first connection pad 111

Second connection pad 121

First solder mask layer 61

Second solder mask 62

Anti-oxidation layer 70

The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the application are only for the purpose of describing specific embodiments, and are not intended to limit the application.

Some implementations of the present application will be described in detail below in conjunction with the accompanying drawings. In the case of no conflict, the following embodiments and features in the embodiments can be combined or replaced with each other.

Please refer to FIG. 1 to FIG. 10 , the first embodiment of the present application provides a method for manufacturing a circuit board 100, which includes the following steps:

Step S1 , please refer to FIG. 1 , providing a double-sided substrate 10 and forming blind holes 101 on the double-sided substrate 10 .

The double-sided substrate 10 includes a first metal layer 11 , a first insulating layer 12 and a third metal layer 13 which are stacked. The blind hole 101 penetrates through the third metal layer 13 and the first insulating layer 12 , and part of the first metal layer 11 is exposed from the blind hole 101 . The number of blind holes 101 can be set according to actual needs, which is not limited in this application.

The first insulating layer 12 is a dielectric material commonly used in the field, such as polyimide, epoxy resin and the like. Materials of the first metal layer 11 and the third metal layer 13 may include but not limited to copper, gold, silver and the like. In this embodiment, the first metal layer 11 and the third metal layer 13 are copper foil.

Step S2 , please refer to FIG. 2 , forming a conductive structure 102 in the blind hole 101 to electrically connect the first metal layer 11 and the third metal layer 13 .

In this embodiment, the conductive structure 102 is a conductive hole. The conductive hole can be manufactured in the following manner: firstly, a seed layer is formed on the inner wall of the blind hole 101 by using a black hole/black shadow process, and then a copper plating layer is formed on the seed layer by electroplating, to form the conductive hole. The seed layer can also be formed on the inner wall of the blind hole 101 by electroless copper plating. In other manners, the conductive structure 102 may be a conductive column, which may be formed by filling the blind hole 101 with a conductive material.

In step S3 , please refer to FIG. 3 , performing circuit fabrication on the third metal layer to form a third conductive layer 130 . The third conductive layer 130 is electrically connected to the first metal layer 11 through the conductive structure 102 .

Step S4, please refer to FIG. 4 and FIG. 5, providing a second insulating layer 21 and a second metal layer 22, and pressing the second insulating layer 21 and the second metal layer 22 on the third conductive layer in sequence. On layer 130, a circuit substrate 30 is obtained.

The first metal layer 11 and the second metal layer 22 are located outside the circuit substrate 30 and are opposite to each other. The second insulating layer 21 covers the third conductive layer 130 and is connected with the first insulating layer 12 to form a whole. In other embodiments, the third conductive layer 130 may be omitted, or the number of the third conductive layer 130 may be multiple, or the second metal layer 22 and the second insulating layer 21 may be omitted, This application is not limited.

The second insulating layer 21 is a common dielectric material in the field, such as polyimide, epoxy resin and the like. The material of the second metal layer 22 may include but not limited to copper, gold, silver and the like. In this embodiment, the second metal layer 22 is copper foil.

Step S5 , please refer to FIG. 5 , forming an insulating layer 40 on a side of the first metal layer 11 away from the first insulating layer 12 . The insulating layer 40 covers a side of the first metal layer 11 away from the first insulating layer 12 .

The material of the insulating layer 40 can be photosensitive resin, such as photosensitive polyimide, or non-photosensitive resin, such as Ajinomoto Build-up Film (ABF) material.

In step S6 , please refer to FIG. 6 , removing part of the insulating layer 40 to form a plurality of insulating bumps 41 .

The bumps 41 are formed by the remaining insulating layer 40 . The plurality of bumps 41 are disposed on the first metal layer 11 at intervals. The bumps 41 are roughly columnar, and the diameter of the bumps 41 is 100-400 μm. In some embodiments, the diameter of the bump 41 is 200-300 μm. The height a of the bump 41 is 20-200 μm. In some embodiments, the height a of the bump 41 is 30-50 μm. In this embodiment, along the thickness direction of the circuit board (ie along the height direction of the bump 41 ), the cross-sectional shape of the bump 41 is an inverted trapezoid. In other implementation manners, the cross-sectional shape of the bump 41 may also be trapezoidal, rectangular, etc., which is not limited in this application.

In this embodiment, the insulating layer 40 is made of photosensitive resin. Step S6 specifically includes: exposing and developing the insulating layer 40 to remove part of the insulating layer 40 and form a plurality of bumps 41 . That is, part of the insulating layer 40 is removed by exposure and development. In other implementation manners, a part of the insulating layer 40 may also be removed by physical etching such as laser etching, plasma etching, or chemical etching, mechanical cutting, etc., to form the plurality of bumps 41 .

Step S7 , please refer to FIG. 7 , forming a metal layer 42 on the surface of the bump 41 to obtain a conductive pillar 50 .

The metal layer 42 covers the exposed bump 41 on all surfaces of the circuit substrate 30 and is connected to the first metal layer 11 . The bump 41 and the metal layer 42 covered thereon together constitute the conductive column 50 , and the conductive column 50 is electrically connected to the first metal layer 11 .

In this embodiment, the metal layer 42 is formed on the surface of the bump 41 by electroplating. Specifically, firstly, a seed layer is formed on the surface of the bump 41 using a black shadow process, and then the metal layer 42 is formed on the seed layer by electroplating. In other implementation manners, the metal layer 42 may also be formed on the surface of the bump 41 by other means such as printing.

The thickness b of the metal layer 42 is 5-35 μm. In some embodiments, the thickness b of the metal layer 42 is 10-15 μm.

Step S8 , please refer to FIG. 8 , performing circuit fabrication on the first metal layer and the second metal layer to form a first conductive layer 110 and a second conductive layer 120 respectively.

The first conductive layer 110 and the second conductive layer 120 are formed by an image transfer process and an etching process.

The first conductive layer 110 includes a plurality of first connection pads 111 , and each first connection pad 111 is electrically connected to the metal layer 42 of the corresponding conductive column 50 . The second conductive layer 120 includes a plurality of second connection pads 121 .

Step S9 , please refer to FIG. 9 , forming a first solder resist layer 61 on the first conductive layer 110 , and forming a second solder resist layer 62 on the second conductive layer 120 to obtain a circuit board 100 .

The first solder resist layer 61 covers the side of the first conductive layer 110 facing away from the first insulating layer 12, and the first connection pad 111 and the conductive column 50 are exposed on the first solder resist layer. Layer 61 outside. The second solder resist layer 62 covers a side of the second conductive layer 120 away from the second insulating layer 21 , and the second connection pad 121 is exposed outside the second solder resist layer 62 .

In this embodiment, the first solder resist layer 61 and the second solder resist layer 62 are formed by using liquid photosensitive solder resist ink through printing, baking, UV exposure, and development processes.

The circuit board 100 further includes a conductive structure (not shown) penetrating through the second insulating layer 21 and electrically connecting the second conductive layer 120 and the third conductive layer 130 . The conductive structure may be a conductive hole or a conductive column.

In step S10 , please refer to FIG. 10 , surface treatment is performed on the first connection pad 111 , the conductive column 50 and the second connection pad 121 to form a conductive anti-oxidation layer 70 . The anti-oxidation layer 70 covers the surface of the first connection pad 111 facing away from the first insulating layer 12 , the surface of the metal layer 42 facing away from the bump 41 , and the surface of the second connection pad 121 facing away from the first insulating layer 12 . The surface of the second insulating layer 21.

The anti-oxidation layer 70 is made by chemical deposition or electroplating nickel-gold, nickel-palladium-gold, chemical tin, chemical tin-silver, chemical tin-silver-copper, electrolytic tin, electrolytic tin-silver, electrolytic tin-silver-copper or chemical silver.

Please refer to FIG. 10 , the embodiment of the present application also provides a circuit board 100 , including a second conductive layer 120 , a second insulating layer 21 , a third conductive layer 130 , a first insulating layer 12 and a first conductive layer stacked in sequence. 110, a plurality of conductive pillars 50 disposed on the first conductive layer 110, and the first solder resist layer 61 and the second solder resist layer respectively disposed on the first conductive layer 110 and the second conductive layer 120 Layer 62. The second insulating layer 21 is connected to the first insulating layer 12 as a whole. The first conductive layer 110 includes a plurality of first connection pads 111 , and the second conductive layer 120 includes a plurality of second connection pads 121 . The plurality of conductive columns 50 are disposed on the plurality of first connection pads 111 . The conductive pillar 50 includes an insulating bump 41 disposed on the first connection pad 111 and a metal layer 42 covering the surface of the bump 41 . The metal layer 42 is connected to the first connection pad 111 . The first solder resist layer 61 covers the side of the first conductive layer 110 facing away from the first insulating layer 12, and the first connection pad 111 and the conductive column 50 are exposed on the first solder resist layer. Layer 61 outside. The second solder resist layer 62 covers a side of the second conductive layer 120 away from the second insulating layer 21 , and the second connection pad 121 is exposed outside the second solder resist layer 62 .

In the circuit board 100 and its manufacturing method in the embodiment of the present application, a plurality of bumps 41 are formed by removing part of the insulating layer 40, and a metal layer 42 is coated on the surface of the bumps 41 by electroplating. The conductive column 50 , compared with the conventional conductive column formed by electroplating, shortens the plating layer and time, improves the electroplating efficiency, and improves the consistency of the height of the conductive column 50 . And when the conductive pillar 50 is connected with the electronic components, the bump 41 can provide a hard support.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Anyone familiar with this field , without departing from the scope of the technical solution of the present invention, when the technical content disclosed above can be used to make some changes or be modified into equivalent implementations with equivalent changes, but as long as it does not depart from the technical solution of the present invention, the technical content of the present invention In essence, any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solution of the present invention.

Claims (10)

1. A circuit board comprises a first conducting layer located on the outer side, wherein the first conducting layer comprises a plurality of first connecting pads.

2. The circuit board of claim 1, wherein the metal layer is a metal plating layer.

3. The circuit board of claim 1, wherein the bump is made of photosensitive resin.

4. The circuit board of claim 1, wherein the first conductive layer is covered with a first solder mask layer, and the first connecting pad and the metal layer are exposed from the first solder mask layer.

5. The circuit board of claim 1, wherein the surfaces of the metal layer and the first connection pads are covered with a conductive oxidation preventing layer.

6. The manufacturing method of the circuit board is characterized by comprising the following steps:

providing a circuit substrate, which comprises a first metal layer positioned on the outer side;

forming an insulating layer on the first metal layer;

removing part of the insulating layer to form a plurality of insulated bumps;

forming a metal layer on the surface of the bump, wherein the metal layer is connected with the first metal layer;

and carrying out circuit manufacturing on the first metal layer to form a first conductive layer, wherein the first conductive layer comprises a plurality of first connecting pads, and each first connecting pad is connected with the corresponding metal layer.

7. The method of claim 6, wherein the metal layer is formed on the bump by electroplating.

8. The method of claim 6, wherein the insulating layer is made of photosensitive resin, and the insulating layer is partially removed by exposure and development to form a plurality of insulating bumps.

9. The method of claim 6, wherein the insulating layer is partially removed by laser etching or plasma etching to form a plurality of insulating bumps.

10. The method for manufacturing a circuit board according to claim 6, further comprising the steps of: and forming a first anti-welding layer on the surface of the first conducting layer, wherein the first connecting pad and the metal layer are exposed out of the first anti-welding layer.

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