CN115810546A - A method of manufacturing shielded gate trench MOSFET with high-k dielectric - Google Patents

Abstract

The invention discloses a manufacturing method of a shielded gate trench MOSFET with a high-k dielectric, which comprises the following steps: growing an epitaxial layer over a substrate; forming a hard mask structure consisting of a first oxide layer, a silicon nitride dielectric layer and a second oxide layer which are sequentially stacked; forming a groove by photoetching; depositing a side wall oxide layer in the groove; depositing and etching back to form source electrode polycrystalline silicon; etching the side wall oxide layer to a target depth by a wet method; depositing a high-k dielectric layer to fill the groove and etching back to a target depth; depositing to generate an oxide layer to backfill the trench; removing the oxide layer above the silicon nitride, and etching the oxide layer by a wet method to form an isolation oxide layer; forming a grid oxide layer by adopting a thermal oxidation process; and forming gate polysilicon. The invention can enhance the charge coupling effect of the source polysilicon and the drift region by using the high-k dielectric, so that the longitudinal electric field distribution of the drift region is more uniform, the breakdown voltage of the device is further improved, and the better specific on-resistance and gate-to-drain charge are realized.

Description

A method of manufacturing shielded gate trench MOSFET with high-k dielectric

technical field

The invention belongs to the technical field of semiconductor power devices, and in particular relates to a method for manufacturing a shielded grid trench MOSFET with a high-k dielectric.

Background technique

In the field of medium and low voltage power devices, the shielded gate trench MOSFET (SGT MOSFET) utilizes the two-dimensional charge coupling effect to achieve low on-resistance at high doped epitaxial layer concentration, breaking the silicon limit theory of traditional power MOSFETs. At the same time, the shielded gate structure also has a smaller gate-to-drain capacitance, which improves the switching frequency of the device. The SGT MOSFET with excellent performance has gradually become the mainstream device in the market.

Figure 1 is a schematic diagram of the structure of a traditional SGT MOSFET. There is a polysilicon deep inside the trench and connected to the source electrode. The source polysilicon acts like a bulk field plate, depleting the drift region through the thicker trench sidewall oxide. This will introduce a new electric field peak near the bottom of the trench in the drift region, changing the longitudinal electric field from a triangular distribution to a catenary distribution, that is, there is an electric field valley in the middle of the drift region. The non-uniformity of the vertical electric field will become more and more serious as the depth of the trench increases, so that the source polysilicon cannot achieve a perfect charge coupling effect. Therefore, the traditional SGT MOSFET is only suitable for the voltage range within 200V, and its structural characteristics obviously hinder its own development.

Contents of the invention

In order to solve the above problems, the present invention proposes a method for manufacturing SGT MOSFETs with high-k dielectrics, which can improve the problem of uneven longitudinal electric field distribution in the drift region. After depositing the sidewall oxide layer in the deep trench, etch back to the middle of the drift region, then deposit a high-k insulating dielectric and etch back to keep a certain length, then use high-density plasma to deposit the oxide layer, and etch back the oxide layer at the same time Form the sidewall oxide near the top of the source polysilicon and the isolation oxide. The insulating dielectric on the side wall of the trench presents a sandwich structure of an oxide layer, a high-k dielectric layer, and an oxide layer along the longitudinal direction.

The source polysilicon in the middle of the drift region can enhance the charge coupling with the drift region through the high-k dielectric. When the device is in the off state, there will be more positively charged donor ions in the middle of the drift region to terminate the induced negative of the source polysilicon. Charge, thereby pulling up the valley electric field in the middle of the drift region. By reasonably controlling the dielectric constant and length of the high-k dielectric, the valley electric field can be kept consistent with the peak electric field intensity at both ends of the drift region, making the overall longitudinal electric field distribution more uniform, thereby improving the breakdown voltage of the device.

In the case of keeping the breakdown voltage unchanged, it is necessary to increase the doping concentration of the epitaxial layer to match the stronger charge coupling, thereby further reducing the on-resistance. In addition, due to the stronger charge coupling effect produced by the high-k dielectric, it is equivalent to improving the charge shielding effect of the source polysilicon on the gate, which can reduce the parasitic capacitance C _gd generated between the gate and the drain.

The SGT MOSFET manufacturing method provided by the present invention with high-k dielectric comprises the following steps:

Step 1: growing an epitaxial layer on a silicon substrate;

Step 2: sequentially forming a hard mask layer composed of a first oxide layer, a silicon nitride layer and a second oxide layer on the surface of the epitaxial layer;

Step 3: Etching the hard mask layer and epitaxy in sequence by photolithography to form trenches;

Step 4: forming a sidewall oxide layer inside the trench by using a chemical vapor deposition process;

Step 5: Deposit source polysilicon, and dry etch to the target depth;

Step 6: Wet etching the sidewall oxide layer to the target depth;

Step 7: Deposit a high-k insulating dielectric to fill the trench, etch back the high-k dielectric and keep a certain length;

Step 8: Deposit the oxide layer by high-density plasma chemical vapor phase, remove the oxide layer above the silicon nitride layer by chemical mechanical polishing, then remove the silicon nitride layer, and then etch back the oxide layer while forming the sidewall near the top of the source polysilicon oxide layer and isolation oxide layer;

Step 9: Form gate oxide layer by thermal oxidation process, deposit gate polysilicon and etch back below the silicon surface;

Step 10: Forming a P-type base region and an N-type source region respectively by ion implantation and high-temperature annealing;

Step eleven: forming an interlayer dielectric, a contact hole, and a front metal layer, and patterning the front metal layer to lead out a gate and a source;

Subsequent passivation layer deposition is required, and a mask plate is added to etch the passivation layer to form a metal lead area. Finally, the substrate thinning and back gold process are carried out.

The invention can optimize the electric field distribution in the drift region by increasing the deposition and etching process of high-k dielectric, and the process is simple, the process steps are few, and the cost is also low. Moreover, the on-resistance and parasitic capacitance can be further improved to make the performance more excellent and expand its application range.

Description of drawings

Below in conjunction with accompanying drawing and specific implementation method, the present invention will be described in further detail:

FIG. 1 is a schematic structural diagram of an existing traditional shielded gate trench MOSFET;

Fig. 2 is the structural representation of the shielded gate trench MOSFET with high-k dielectric of the present invention;

3-12 is a schematic diagram of the manufacturing process of the shielded gate trench MOSFET with high-k dielectric of the present invention;

Fig. 13 is a comparison diagram of the vertical electric field between the embodiment of the present invention and the conventional shielded gate trench MOSFET.

Detailed ways

The trench sidewall insulating layers corresponding to Figure 1 and Figure 2 all have a uniform thickness, and the electric field distribution of the device can be further optimized by setting the insulating layer in the middle of the trench as a high-k dielectric material with a high dielectric constant, so that the electric field distribution of the device can be further optimized. Improve the breakdown voltage of the device and achieve better specific on-resistance.

As a preferred manner, the device structure is based on withstand voltage specifications, and selectable high-k dielectric materials include silicon nitride, aluminum oxide, silicon oxynitride, and the like.

As shown in Figures 3 to 12, this embodiment improves a method for manufacturing a shielded gate trench MOSFET with a high-k dielectric, and the device can be an N-type device or a P-type device. In this embodiment, N type device as an example. Described manufacturing method comprises the steps:

Step 1, as shown in FIG. 3 , provide a substrate, and grow an epitaxial layer on the upper surface of the substrate.

Step 2, as shown in Figure 4, first thermally grow a thinner first oxide layer on the surface of the epitaxial layer, then deposit a layer of silicon nitride layer, and then deposit a thick second oxide layer, A hard mask layer is formed. The function of the first oxide layer is to relieve the stress of the silicon nitride layer. The silicon nitride layer is a cut-off layer for the subsequent chemical mechanical polishing process.

Step 3, as shown in FIG. 5 , the hard mask layer and the epitaxial layer are sequentially etched by a photolithography process to form trenches, and the bottom of the trenches needs to be rounded.

Step 4, as shown in FIG. 6 , a sidewall oxide layer is formed on the side surface and the bottom surface of the trench by means of deposition. The thickness of the sidewall oxide layer is 2000 angstroms to 10000 angstroms.

Step 5, as shown in FIG. 7 , fill the trench with polysilicon, and etch back to form source polysilicon, with a depth of about 1 μm to 1.5 μm.

Step 6, as shown in FIG. 8 , wet etching is used to etch the sidewall oxide layer inside the trench to a target depth, and at the same time, the thick oxide layer above the epitaxial layer will be removed.

Step 7, as shown in FIG. 9 , fill the trench with high-k dielectric, and etch back to the target depth. The length of the high-k medium is about 0.5 microns to 5 microns.

Step 8, as shown in Figure 10, use high-density plasma chemical vapor deposition to fill the oxide layer inside the trench, use chemical mechanical polishing to remove the oxide layer above the silicon nitride layer, then remove the silicon nitride, and then etch back the oxide layer layer simultaneously forms the sidewall oxide near the top of the source polysilicon and the isolation oxide.

The step coverage of the high-density plasma chemical vapor deposition process is good, the groove can be well filled, and the generation of voids can be prevented. Combined with the chemical mechanical polishing process, the surface of the isolation oxide layer can be kept flat.

Step 9. As shown in FIG. 11 , a gate oxide layer is formed by using a thermal oxidation process, and the gate polysilicon is backfilled and etched below the silicon surface to form a gate of the device.

Step ten, as shown in FIG. 12 , respectively form a P-type base region and an N-type source region by ion implantation and high-temperature annealing. The P-type base region forms a channel region, and the surface of the channel region covered by the gate polysilicon side is used to form a channel. The N-type epitaxial layer at the bottom of the channel region constitutes a drift region.

Step eleven, forming an interlayer dielectric, a contact hole and a front metal layer, and patterning the front metal layer to lead out a gate and a source, and finally the formed structure is shown in FIG. 2 .

In order to form a complete shielded gate power device, passivation layer deposition is required subsequently, and a mask plate is added to etch the passivation layer to form a metal lead area. Finally, the substrate is thinned and the back gold process is carried out, and the drain is drawn out from the back metal.

In addition, in practice, the outer side of the shielded gate power device cell structure also includes a source electrode lead-out area and a gate electrode lead-out area. There is only one piece of source polysilicon in the source electrode lead-out region, which is connected to the source polysilicon in the cell region and connected to the source metal through the contact hole above the trench of the source electrode lead-out region. There are upper and lower pieces of polysilicon in the gate electrode lead-out area, and the upper gate polysilicon is connected to the gate polysilicon in the cell area and connected to the gate metal through the contact hole above the trench in the gate electrode lead-out area.

In the embodiment of the present invention, the metal material filled in the contact hole is the same as the metal material of the front metal layer; or, the metal material filled in the contact hole is different from the metal material of the front metal layer. The metal material of the front metal layer is aluminum, copper aluminum alloy or other metal materials.

In the embodiment of the present invention, the gate oxide layer is a thermal oxide film grown in a dry oxygen method, with a thickness of 100 angstroms to 1000 angstroms. The sidewall oxide layer is formed by a deposition method, or a combination of a thermal oxide film and a deposited oxide film.

As shown in Figure 13, it is the curve of the vertical electric field of the device formed by the method of the embodiment of the present invention and the traditional shielded gate trench MOSFET changing with the position of the drift region, the direction of change is from the top to the bottom of the epitaxial layer, and the abscissa is the electric field Intensity, it can be seen that the longitudinal electric field intensity in the middle of the drift region of the present invention is relatively high, and there is an electric field peak near the bottom of the high-k medium, and the overall longitudinal electric field distribution is more uniform. Since the area surrounded by the vertical electric field in the present invention is larger, it means that the breakdown voltage is larger, so the doping concentration of the epitaxial layer can be selected to further reduce the on-resistance.

The above-mentioned embodiments have described the present invention in detail, but these are not constituting a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (8)

1. A method for manufacturing a shielded gate trench MOSFET with a high-k dielectric, characterized in that it may further comprise the steps: Step 1: growing an epitaxial layer on a silicon substrate; Step 2: sequentially forming a hard mask layer composed of a first oxide layer, a silicon nitride layer and a second oxide layer on the surface of the epitaxial layer; Step 3: Etching the hard mask layer and epitaxy in sequence by photolithography to form trenches; Step 4: forming a sidewall oxide layer inside the trench by using a chemical vapor deposition process; Step 5: Deposit source polysilicon, and dry etch to the target depth; Step 6: Wet etching the sidewall oxide layer to the target depth; Step 7: Deposit a high-k insulating dielectric to fill the trench, etch back the high-k dielectric and keep a certain length; Step 8: Deposit the oxide layer by high-density plasma chemical vapor phase, remove the oxide layer above the silicon nitride layer by chemical mechanical polishing, then remove the silicon nitride layer, and then etch back the oxide layer while forming the sidewall near the top of the source polysilicon oxide layer and isolation oxide layer; Step 9: Form gate oxide layer by thermal oxidation process, deposit gate polysilicon and etch back below the silicon surface; Step 10: Forming a P-type base region and an N-type source region respectively by ion implantation and high-temperature annealing; Step eleven: forming an interlayer dielectric, a contact hole, and a front metal layer, and patterning the front metal layer to lead out a gate and a source; Subsequent passivation layer deposition is required, and a mask plate is added to etch the passivation layer to form a metal lead area; finally, the substrate thinning and back gold process are performed. 2. The manufacturing method of the shielded gate trench MOSFET with high-k dielectric according to claim 1, characterized in that: the two sides of the trench described in step 3 are etched at a certain angle, the sidewall surfaces are flat, and the bottom of the trench is Carry out arc processing. 3. The manufacturing method of the shielded gate trench MOSFET with high-k dielectric according to claim 1, characterized in that: the high-k dielectric in step 7 is located on both sides of the sidewall of the middle trench, and the high-k dielectric The thickness is consistent with the thickness of the sidewall oxide layer. 4. The manufacturing method of the shielded gate trench MOSFET with high-k dielectric according to claim 3, characterized in that: the thickness of the high-k dielectric is between 0.2 micron and 1 micron, and the length is between 0.5 micron and 5 micron between microns. 5. The method for manufacturing a shielded gate trench MOSFET with a high-k dielectric according to claim 1 or 3, characterized in that: the trench sidewall insulating layer is composed of silicon oxide and silicon nitride, and between the polysilicon The isolation dielectric layer is composed of silicon oxide formed by deposition, and the gate dielectric layer is composed of silicon oxide grown by dry oxygen. 6 . The method for manufacturing a shielded gate trench MOSFET with a high-k dielectric according to claim 5 , wherein the thickness of the isolation oxide layer is between 1000 angstroms and 5000 angstroms. 7. The method for manufacturing a shielded gate trench MOSFET with a high-k dielectric according to claim 1, wherein the gate polysilicon is connected to the gate through a contact hole, and the source region is connected to the gate through a contact hole and the source connection. 8 . The method for manufacturing a shielded gate trench MOSFET with a high-k dielectric according to claim 7 , wherein the source polysilicon is connected to the source through a contact hole.

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