CN115801165B - Time synchronization method, system, equipment and medium of vehicle-mounted controller - Google Patents
Time synchronization method, system, equipment and medium of vehicle-mounted controller Download PDFInfo
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Abstract
The application relates to a time synchronization method, device, equipment and medium of a vehicle-mounted controller. The method comprises the following steps: acquiring a first pulse signal and a first time signal, wherein the time sequences of the first pulse signal and the first time signal correspond to each other; generating a second pulse signal of the first controller, and sampling the first pulse signal to obtain a first rising edge; resetting the second pulse signal according to the first rising edge so as to synchronize the second time signal of the first controller according to the first time signal. By adopting the method, the time synchronization of the vehicle-mounted controller can be realized.
Description
Technical Field
The application relates to the technical field of automatic driving time synchronization, in particular to a time synchronization method, a system, equipment and a medium of a vehicle-mounted controller.
Background
With the rapid development of automobile technology, development of automatic driving automobiles is becoming hot. Behavior decisions are one of the important components of autopilot, which rely on time synchronization between individual onboard controllers or sensors.
For example, after high-precision time synchronization is obtained in an automatic driving vehicle, sensors such as radar probes on the vehicle can send obstacle information around the vehicle to a behavior decision module, so that decisions can be made in time, and safety accidents are avoided. For example, after the automatic driving vehicles on the road acquire high-precision time synchronization, specific positions of other vehicles can be accurately perceived among the vehicles, so that collision is avoided, and the safety of road traffic is improved.
Thus, time synchronization plays a crucial role in the behavioral decision of autopilot.
Disclosure of Invention
Based on the above, a time synchronization method, a system, equipment and a medium of the vehicle-mounted controller are provided to realize the time synchronization of the vehicle-mounted controller.
In a first aspect, a time synchronization method of an on-vehicle controller is provided, the method including:
Acquiring a first pulse signal and a first time signal, wherein the time sequences of the first pulse signal and the first time signal correspond to each other;
Generating a second pulse signal of the first controller, and sampling the first pulse signal to obtain a first rising edge;
Resetting the second pulse signal according to the first rising edge so as to synchronize the second time signal of the first controller according to the first time signal.
With reference to the first aspect, in a first implementation manner of the first aspect, the step of resetting the second pulse signal according to the first rising edge includes:
Acquiring the number of the first rising edges, first pulse widths corresponding to the first rising edges and first interval duration between two adjacent first rising edges;
resetting the second pulse signal of the first controller according to the number of the first rising edges, the first pulse width and the first interval duration, so that the second rising edges of the second pulse signal and the first rising edges of the first pulse signal are aligned.
In a second aspect, a time synchronization method of an on-vehicle controller is provided, where the time synchronization method of the controller as described in the first aspect or in combination with the first implementation manner of the first aspect is further provided, and the method further includes:
Encoding the second pulse signal to obtain a first data frame, wherein the first data frame comprises a first byte, and the first byte corresponds to the time sequence of a second rising edge of the second pulse signal;
Generating a third pulse signal of at least one second controller, recovering the first data frame into a second pulse signal, and sampling the second pulse signal to obtain a second rising edge;
And resetting each third pulse signal according to the second rising edge when the first byte is received, so as to synchronize the third time signals of each second controller according to the second time signals of the first controller.
With reference to the second aspect, in a first implementation manner of the second aspect, before the step of resetting each of the third pulse signals according to the first byte, the method further includes:
obtaining a signal to be checked according to the first data frame and the second time signal, and sending the first data frame, the second time signal and the signal to be checked according to a time sequence;
performing cyclic redundancy check on the received first data frame and the second time signal to obtain a check signal, and comparing the check signal with a received signal to be checked;
And executing the step of resetting each third pulse signal according to the second rising edge under the condition that the verification signal is consistent with the signal to be verified.
With reference to the second aspect, in a second implementation manner of the second aspect, the step of resetting each of the third pulse signals according to the second rising edge includes:
when a first byte is received, acquiring the number of the second rising edges, second pulse widths corresponding to the second rising edges and second interval duration between two adjacent second rising edges;
Resetting the third pulse signals of the second controllers according to the number of the second rising edges, the second pulse widths and the second interval durations so that the third rising edges of the third pulse signals are aligned with the second rising edges of the second pulse signals respectively.
In a third aspect, a time synchronization apparatus of an in-vehicle controller is provided, including a first controller including:
the receiving chip is used for acquiring a first pulse signal and a first time signal, wherein the time sequences of the first pulse signal and the first time signal correspond to each other;
the first processing chip comprises a first counter and a first clock, wherein the first counter is used for generating a second pulse signal of the first controller, and the first clock is used for sampling the first pulse signal to obtain a first rising edge;
the first processing chip is used for resetting the first counter according to the first rising edge so as to reset the second pulse signal, and synchronizing the second time signal of the first controller according to the first time signal.
In a fourth aspect, there is provided a time synchronization device of an in-vehicle controller, to which the time synchronization device of the controller according to the third aspect is applied, further including at least one second controller, each of the second controllers including:
The second processing chip comprises a second counter and a second clock, wherein the second counter is used for generating a third pulse signal of the second controller, and the second clock is used for sampling the second pulse signal to obtain a second rising edge;
The second processing chip is further configured to clear the second counter according to the second rising edge when the first byte is received, so as to reset the third pulse signal, and synchronize a third time signal of the second controller according to a second time signal of the first controller;
the first controller is further configured to encode a second pulse signal to obtain a first data frame, where the first data frame includes a first byte, and the first byte corresponds to a timing sequence of a second rising edge of the second pulse signal.
With reference to the fourth aspect, in a first possible implementation manner of the fourth aspect,
The first controller is further configured to obtain a signal to be checked according to the first data frame and the second time signal, and send the first data frame, the second time signal and the signal to be checked according to a time sequence;
the second processing chip is also used for performing cyclic redundancy check on the received first data frame and the second time signal to obtain a check signal, and comparing the check signal with a received signal to be checked;
The second processing chip is further configured to execute a step of resetting the third pulse signal according to the second rising edge when the verification signal is consistent with the signal to be verified.
In a fifth aspect, a computer device is provided, comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the time synchronization method of the in-vehicle controller as described in any one of the first aspect, the implementation manner combined with the first aspect, the second aspect and the implementation manner combined with the second aspect when the computer program is executed.
In a sixth aspect, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the time synchronization method of an in-vehicle controller as described in any of the first aspect, the embodiments in combination with the first aspect, the second aspect, and the embodiments in combination with the second aspect.
The time synchronization method, the device, the equipment and the medium of the vehicle-mounted controller are characterized in that a first pulse signal and a first time signal are obtained, wherein the time sequences of the first pulse signal and the first time signal are supposed to correspond; generating a second pulse signal of the first controller, and sampling the first pulse signal to obtain a first rising edge; resetting the second pulse signal according to the first rising edge so as to synchronize the second time signal of the first controller according to the first time signal. Therefore, the time synchronization of the vehicle-mounted controller can be realized by adopting the method.
Drawings
FIG. 1 is a flowchart of a time synchronization method of an in-vehicle controller according to an embodiment;
FIG. 2 is a flowchart of a time synchronization method of an in-vehicle controller according to another embodiment;
FIG. 3 is a flowchart of a time synchronization method of an in-vehicle controller according to another embodiment;
FIG. 4 is a block diagram of a time synchronization device of an in-vehicle controller according to another embodiment;
FIG. 5 is a block diagram of a time synchronization device of an in-vehicle controller according to another embodiment;
FIG. 6 is a diagram of a signal transmission format in one embodiment;
fig. 7 is an internal structural diagram of a computer device in one embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
Because embodiments of the present application relate to terminology, the following description of the relevant terms and concepts that embodiments of the application may relate to will be presented for ease of understanding.
1. Coordination world time (Universal Time Coordinated, UTC)
Universal time, also known as universal time, universal time or international coordination time. Coordinated universal time is a time metering mode which is as close to universal time as possible in time on the basis of atomic time seconds. Wherein atomic time refers to a time based on a definition of precise seconds.
2. Cyclic redundancy check (Cyclic Redundancy Check, CRC)
The cyclic redundancy check is a hash function for generating a short fixed bit check code according to data such as network data packets or computer files, and is mainly used for detecting or checking whether errors occur after data transmission or storage. The check code is calculated before transmission or storage and appended to the data for transmission, and then the receiving side checks the received data and compares the obtained check result with the check code transmitted by the transmitting side, thereby determining whether the data is changed.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The structures, proportions, sizes, etc. shown in the drawings attached hereto are for illustration purposes only and are not intended to limit the scope of the application, which is defined by the claims, but rather by the claims.
References in this specification to orientations or positional relationships as "upper", "lower", "left", "right", "intermediate", "longitudinal", "transverse", "horizontal", "inner", "outer", "radial", "circumferential", etc., are based on the orientation or positional relationships shown in the drawings, are also for convenience of description only, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore are not to be construed as limiting the application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
At present, the requirements of the automatic driving automobile on behavior decision are higher and higher, and time synchronization has a non-negligible influence on the behavior decision. After the automatic driving vehicle acquires high-precision time synchronization, behavior decisions can be made according to surrounding barrier information acquired by the environment sensing module, so that safety accidents such as collision are avoided.
Therefore, the application provides a time synchronization method of a vehicle-mounted controller, which comprises the steps of obtaining a first pulse signal and a first time signal, wherein the time sequences of the first pulse signal and the first time signal correspond to each other; sampling the first pulse signal to obtain a first rising edge; resetting the second pulse signal of the first controller according to the first rising edge, so that the second time signal of the first controller is synchronized according to the first time signal. The method can realize time synchronization of the vehicle-mounted controller.
Next, the present application will be described with reference to a flowchart shown in fig. 1, where a time synchronization method of an in-vehicle controller according to the present application is described by taking an execution subject of the method as an example of a time synchronization device of the in-vehicle controller, and in a first embodiment, the time synchronization method includes the following steps:
s101: and acquiring a first pulse signal and a first time signal, wherein the first pulse signal and the first time signal correspond to each other in time sequence.
The first pulse signal may specifically be a second pulse signal, and the first time signal may be a coordinated universal time from a global navigation satellite system (Global Navigation SATELLITE SYSTEM, GNSS). The correspondence of the timing of the first pulse signal and the first time signal means that the first rising edge of the first pulse signal corresponds to the accurate time information indicated by the first time signal.
S102: and generating a second pulse signal of the first controller, and sampling the first pulse signal to obtain a first rising edge.
Illustratively, the first controller of the time synchronization device may maintain a first counter for generating the second pulse signal of the first controller; the time synchronization device may further include a first clock, where the first clock is configured to sample the first pulse signal to obtain a first rising edge. The first counter may be a 32-bit counter, and the first clock may be a high-speed clock with a frequency of 50 MHz.
S103: resetting the second pulse signal according to the first rising edge so as to synchronize the second time signal of the first controller according to the first time signal.
Resetting the second pulse signal by resetting the first counter according to the first rising edge, and synchronizing the second time signal of the first controller according to the first time signal. Specifically, resetting the second pulse signal refers to obtaining the number of the first rising edges, a first pulse width corresponding to each first rising edge, and a first interval length between two adjacent first rising edges; resetting the second pulse signal of the first controller according to the number of the first rising edges, the first pulse width and the first interval duration, so that the second rising edges of the second pulse signal and the first rising edges of the first pulse signal are aligned. Since the first rising edge corresponds to the exact time information indicated by the first time signal, synchronization of the time information indicated by the second time signal of the first controller is achieved when said first rising edge and said second rising edge are aligned.
In the time synchronization method of the vehicle-mounted controller, the time synchronization device obtains the corresponding first rising edge by sampling the first pulse signal, and resets the second pulse signal of the first controller according to the first rising edge, namely, the second rising edge of the second pulse signal is aligned with the first rising edge; because the first rising edge corresponds to the accurate time information indicated by the first time signal, when the first rising edge and the second rising edge are aligned, the synchronization of the time information indicated by the second time signal of the first controller is realized, and higher cost is not required by adopting the method.
As shown in fig. 2, in a second embodiment, the time synchronization method of the vehicle-mounted controller includes the steps of:
S201: acquiring a first pulse signal and a first time signal, wherein the time sequences of the first pulse signal and the first time signal correspond to each other;
S202: generating a second pulse signal of the first controller, and sampling the first pulse signal to obtain a first rising edge;
S203: resetting the second pulse signal according to the first rising edge so as to synchronize the second time signal of the first controller according to the first time signal.
The steps S201 to S203 are described in detail in the first embodiment, and the related description is referred to the first embodiment, and will not be repeated here.
S204: and encoding the second pulse signal to obtain a first data frame, wherein the first data frame comprises a first byte, and the first byte corresponds to the time sequence of the second rising edge.
In this embodiment, the first controller of the time synchronization device of the vehicle-mounted controller performs the steps of the first embodiment, and completes synchronization of the time information indicated by the second time signal thereof; and then, encoding the synchronized second pulse signal to obtain a first data frame, and transmitting the first data frame and the second time signal according to a time sequence. The first data frame comprises a first byte, and the first byte corresponds to the time sequence of the second rising edge of the second pulse signal. And the timing of the first byte and the second rising edge of the second pulse signal corresponds to the alignment of the first byte with the second rising edge of the second pulse signal.
S205: and generating a third pulse signal of at least one second controller, recovering the first data frame into a second pulse signal, and sampling the second pulse signal to obtain a second rising edge.
The time synchronization device of the vehicle-mounted controller further comprises at least one second controller, and each second controller is in data transmission with the first controller. After each second controller receives the first data frame and the second time signal, the first data frame is restored to the second pulse signal, and a second counter is maintained, and the second counter is used for generating a third pulse signal of the second controller. Each second controller further comprises a second clock, and the second clock is used for sampling the second pulse signals to obtain second rising edges. Illustratively, the second counter may be a 32-bit counter and the second clock may be a high-speed clock having a frequency of 50 MHz.
S206: and resetting each third pulse signal according to the second rising edge when the first byte is received, so as to synchronize the third time signals of each second controller according to the second time signals of the first controller.
Resetting the second counter according to the second rising edge to reset each third pulse signal, and synchronizing the third time signals of each second controller according to the second time signals of the first controller. Specifically, resetting each third pulse signal refers to, when receiving the first byte, obtaining the number of the second rising edges, the second pulse width corresponding to each second rising edge, and the second interval duration between two adjacent second rising edges; resetting the third pulse signals of the second controllers according to the number of the second rising edges, the second pulse widths and the second interval durations so that the third rising edges of the third pulse signals are aligned with the second rising edges of the second pulse signals respectively. Since the first controller performs time synchronization according to the above embodiment, the second rising edge corresponds to the time information indicated by the second pulse signal, and the first byte and the second rising edge are aligned, when the first byte is received, the third rising edge of the second controller is aligned with the second rising edge of the first controller, that is, synchronization of the time information indicated by the third time signal of the second controller is achieved.
In the time synchronization method of the vehicle-mounted controller, the second time signal of the first controller is synchronized according to the first time signal by aligning the second rising edge of the first controller with the first rising edge, wherein the first rising edge corresponds to the time sequence of the first time signal; since each second controller is connected to the first controller, the third time signals of the second controllers are synchronized according to the second time signals by aligning the third rising edge of each second controller with the second rising edge of the first controller, wherein the second rising edge corresponds to the time sequence of the second time signals. Since the first controller is provided with the receiving chip for receiving the first time signal from the GNSS, in this embodiment, the first controller performs time synchronization on each of the second controllers, and the second controller does not need to be provided with the receiving chip, so that the cost can be reduced.
As shown in fig. 3, in a third embodiment, the time synchronization method of the in-vehicle controller includes the steps of:
S301: acquiring a first pulse signal and a first time signal, wherein the time sequences of the first pulse signal and the first time signal correspond to each other;
S302: generating a second pulse signal of the first controller, and sampling the first pulse signal to obtain a first rising edge;
S303: resetting the second pulse signal according to the first rising edge so as to synchronize a second time signal of the first controller according to the first time signal;
s304: encoding the second pulse signal to obtain a first data frame, wherein the first data frame comprises a first byte, and the first byte corresponds to the time sequence of the second rising edge;
S305: and obtaining a signal to be checked according to the first data frame and the second time signal, and sending the first data frame, the second time signal and the signal to be checked according to a time sequence.
Calculating a cyclic redundancy check value for the first data frame and the second time signal, thereby obtaining a signal to be checked; the step of transmitting the first data frame, the second time signal and the signal to be checked according to the time sequence means that the first data frame is transmitted first, then the second time signal is transmitted, and finally the signal to be checked is transmitted.
S306: and generating a third pulse signal of at least one second controller, recovering the first data frame into a second pulse signal, and sampling the second pulse signal to obtain a second rising edge.
S307: performing cyclic redundancy check on the received first data frame and the second time signal to obtain a check signal, and comparing the check signal with a received signal to be checked;
S308: and when the check signal is consistent with the signal to be checked, resetting each third pulse signal according to the second rising edge when the first byte is received, so as to synchronize the third time signals of each second controller according to the second time signals of the first controller.
The steps of S301-S304, S306 and S308 are described in detail in the first embodiment and the second embodiment, and the related description is referred to the first embodiment and the second embodiment, and will not be repeated here.
In this embodiment, if the verification is passed, it indicates that the second time signal received by the second controller is consistent with the second time signal received by the first controller, and the third pulse signals may be reset according to the second rising edge, and the third time signals of the second controller may be synchronized by the second time signal of the first controller. If the verification is not passed, continuing to use the time indicated by the third time signal inside the second controller. It can be seen that in this embodiment, by adding the cyclic redundancy check, the accuracy and reliability of time synchronization between the first controller and the second controller can be ensured.
It should be understood that, although the steps in the flowcharts of fig. 1-3 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 1-3 may include multiple sub-steps or phases that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or phases are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the sub-steps or phases of other steps or other steps.
As shown in fig. 4, in a fourth embodiment, there is provided a time synchronization apparatus of an in-vehicle controller including a first controller including:
the receiving chip is used for acquiring a first pulse signal and a first time signal, wherein the time sequences of the first pulse signal and the first time signal correspond to each other;
the first processing chip comprises a first counter and a first clock, wherein the first counter is used for generating a second pulse signal of the first controller, and the first clock is used for sampling the first pulse signal to obtain a first rising edge;
the first processing chip is used for resetting the first counter according to the first rising edge so as to reset the second pulse signal, and synchronizing the second time signal of the first controller according to the first time signal.
Illustratively, the first counter may be a 32-bit counter and the first clock may be a high-speed clock having a frequency of 50 MHz.
Specifically, the step of resetting the second pulse signal by the first processing chip according to the first rising edge includes:
Acquiring the number of the first rising edges, first pulse widths corresponding to the first rising edges and first interval duration between two adjacent first rising edges;
resetting the second pulse signal of the first controller according to the number of the first rising edges, the first pulse width and the first interval duration, so that the second rising edges of the second pulse signal and the first rising edges of the first pulse signal are aligned.
As shown in fig. 5, in a fifth embodiment, the time synchronization apparatus for a vehicle-mounted controller according to the fourth embodiment is applied, further comprising at least one second controller, each of the second controllers comprising:
The second processing chip comprises a second counter and a second clock, wherein the second counter is used for generating a third pulse signal of the second controller, and the second clock is used for sampling the second pulse signal to obtain a second rising edge;
The second processing chip is further configured to clear the second counter according to the second rising edge when the first byte is received, so as to reset the third pulse signal, and synchronize a third time signal of the second controller according to a second time signal of the first controller;
the first controller is further configured to encode a second pulse signal to obtain a first data frame, where the first data frame includes a first byte, and the first byte corresponds to a timing sequence of a second rising edge of the second pulse signal.
In this embodiment, the first controller and each second controller respectively perform data transmission, after time synchronization is completed, each first controller encodes the synchronized second pulse signal to obtain a first data frame, and then sends the first data frame and the second time signal according to a time sequence. The first data frame comprises a first byte, and the first byte corresponds to the time sequence of the second rising edge of the second pulse signal. And the timing of the first byte and the second rising edge of the second pulse signal corresponds to the alignment of the first byte with the second rising edge of the second pulse signal.
After each second controller receives the first data frame and the second time signal, the first data frame is restored to the second pulse signal, and a second counter is maintained, and the second counter is used for generating a third pulse signal of the second controller. Each second controller further comprises a second clock, and the second clock is used for sampling the second pulse signals to obtain second rising edges. Illustratively, the second counter may be a 32-bit counter and the second clock may be a high-speed clock having a frequency of 50 MHz.
And resetting the second counter according to the second rising edge so as to reset each third pulse signal, so that the third rising edge of each third pulse signal is aligned with the second rising edge of the second pulse signal respectively. Since the first controller performs time synchronization according to the above embodiment, the second rising edge corresponds to the time information indicated by the second pulse signal, and the first byte and the second rising edge are aligned, when the first byte is received, the third rising edge of the second controller is aligned with the second rising edge of the first controller, that is, synchronization of the time information indicated by the third time signal of the second controller is achieved.
Specifically, the step of resetting each third pulse signal by the second processing chip according to the second rising edge includes:
when a first byte is received, acquiring the number of the second rising edges, second pulse widths corresponding to the second rising edges and second interval duration between two adjacent second rising edges;
Resetting the third pulse signals of the second controllers according to the number of the second rising edges, the second pulse widths and the second interval durations so that the third rising edges of the third pulse signals are aligned with the second rising edges of the second pulse signals respectively.
In a sixth embodiment, the first controller is further configured to obtain a signal to be checked according to the first data frame and the second time signal, and send the first data frame, the second time signal, and the signal to be checked according to a time sequence;
the second processing chip is also used for performing cyclic redundancy check on the received first data frame and the second time signal to obtain a check signal, and comparing the check signal with a received signal to be checked;
The second processing chip is further configured to execute a step of resetting the third pulse signal according to the second rising edge when the verification signal is consistent with the signal to be verified.
In the above embodiment of the time synchronization apparatus of the in-vehicle controller, the first processing chip and the second processing chip may employ a low-cost Field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA); the first controller and each second controller can communicate by adopting a Low Voltage differential signal (Low Voltage DIFFERENTIAL SIGNALING, LVDS) bus, the influence caused by common mode interference is improved to a certain extent, the transmission rate can be set to 10MHz, the transmission distance of 10 meters is met, the accuracy can reach the sub microsecond level, and the accuracy and the reliability of time synchronization are ensured.
Fig. 6 is an exemplary diagram of signal transmission formats involved in a time synchronization method of an on-vehicle controller according to the present application, and next, with reference to fig. 6, an exemplary description is given of a step of time synchronization between a first controller and a second controller by taking a time synchronization device of the on-vehicle controller as an execution subject, taking a first pulse signal, a second pulse signal, and a third pulse signal as second pulses, and taking a first time signal, a second time signal, and a third time signal as UTC as examples. Specific: the first processing chip of the first controller, namely the FPGA, encodes the second pulse signal to obtain a first data frame, wherein the first data frame comprises a first byte and 7 second bytes, the first byte is represented by D5, and the second byte is represented by 55; The length of UTC is 4 bytes, the FPGA of the first controller calculates a CRC32 value based on the first data frame of 8 bytes and UTC of 4 bytes, and the length of the CRC value is 4 bytes; then the first controller sequentially sends 55 bytes of 7, D5 bytes of 1, UTC of 4 bytes and CRC32 of 4 bytes one by one through an LVDS bus; and ensures that D5 is properly aligned with the rising edge of the second pulse after it is sent. The second processing chip of the second controller, namely the FPGA, generates a third second pulse inside the second controller by maintaining a 32-bit second counter; When the FPGA of the second controller receives the D5 through the LVDS bus, the second counter with 32 bits inside is cleared, so that the third second pulse inside the second controller is aligned with the rising edge of the second pulse inside the first controller, and a new second pulse is recovered; the FPGA of the second controller can obtain UTC by continuously sampling the bytes after the D5, and the UTC is used for indicating accurate time information when the rising edge of the second pulse appears because the output time of the D5 represents accurate whole second time, so that the accurate time of the third rising edge can be obtained according to the UTC obtained by sampling, and the time synchronization between the first controller and the second controller can be completed at the moment. in addition, the FPGA of the second controller performs CRC calculation on 55, D5 and UTC of 4 bytes of 8 bytes, and then compares the calculated check value with the received CRC32 value, if the check value is consistent with the received CRC32 value, the received second pulse signal is refreshed to the inside for use, otherwise, the inside time is continuously used, and the accuracy and the reliability of time synchronization between the first controller and the second controller can be ensured. Therefore, the method realizes the time synchronization among the controllers in a simple and reliable mode, the precision can reach the sub microsecond level, the time synchronization requirement of the vehicle-mounted controller can be met, and the accuracy and the reliability of the time synchronization can be ensured; And only a receiving chip for receiving UTC from GNSS is required to be installed on the first controller, and the receiving chip is not required to be installed on each second controller, so that the time synchronization cost of the vehicle-mounted controllers is reduced. For specific limitations of the time synchronization device of the vehicle-mounted controller, reference may be made to the above limitation of the time synchronization method of the vehicle-mounted controller, and no further description is given here. The above-mentioned individual chips in the time synchronization device of the vehicle-mounted controller may be implemented in whole or in part by software, hardware, and combinations thereof. The chips can be embedded in hardware or independent of a processor in the computer equipment, and can also be stored in a memory in the computer equipment in a software mode, so that the processor can call and execute the operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a terminal, and the internal structure of which may be as shown in fig. 7. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program, when executed by a processor, implements a time synchronization method for an on-board controller. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be keys, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.
It will be appreciated by those skilled in the art that the structure shown in FIG. 7 is merely a block diagram of some of the structures associated with the present inventive arrangements and is not limiting of the computer device to which the present inventive arrangements may be applied, and that a particular computer device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.
In one embodiment, a computer device is provided comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps of when executing the computer program:
Acquiring a first pulse signal and a first time signal, wherein the time sequences of the first pulse signal and the first time signal correspond to each other;
Generating a second pulse signal of the first controller, and sampling the first pulse signal to obtain a first rising edge;
resetting the second pulse signal according to the first rising edge to synchronize the second time signal of the first controller according to the first time signal
In one embodiment, the processor when executing the computer program further performs the steps of:
the step of resetting the second pulse signal according to the first rising edge includes:
Acquiring the number of the first rising edges, first pulse widths corresponding to the first rising edges and first interval duration between two adjacent first rising edges;
resetting the second pulse signal of the first controller according to the number of the first rising edges, the first pulse width and the first interval duration, so that the second rising edges of the second pulse signal and the first rising edges of the first pulse signal are aligned.
In one embodiment, the processor when executing the computer program further performs the steps of:
The time synchronization method applied to the controller according to any one of the first to third embodiments, further comprising:
Encoding the second pulse signal to obtain a first data frame, wherein the first data frame comprises a first byte, and the first byte corresponds to the time sequence of a second rising edge of the second pulse signal;
Generating a third pulse signal of at least one second controller, recovering the first data frame into a second pulse signal, and sampling the second pulse signal to obtain a second rising edge;
And resetting each third pulse signal according to the second rising edge when the first byte is received, so as to synchronize the third time signals of each second controller according to the second time signals of the first controller.
In one embodiment, the processor when executing the computer program further performs the steps of:
Before the step of resetting each third pulse signal according to the first byte, the method further includes:
obtaining a signal to be checked according to the first data frame and the second time signal, and sending the first data frame, the second time signal and the signal to be checked according to a time sequence;
performing cyclic redundancy check on the received first data frame and the second time signal to obtain a check signal, and comparing the check signal with a received signal to be checked;
And executing the step of resetting each third pulse signal according to the second rising edge under the condition that the verification signal is consistent with the signal to be verified.
In one embodiment, the processor when executing the computer program further performs the steps of:
the step of resetting each third pulse signal according to the second rising edge includes:
when a first byte is received, acquiring the number of the second rising edges, second pulse widths corresponding to the second rising edges and second interval duration between two adjacent second rising edges;
Resetting the third pulse signals of the second controllers according to the number of the second rising edges, the second pulse widths and the second interval durations so that the third rising edges of the third pulse signals are aligned with the second rising edges of the second pulse signals respectively.
In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, performs the steps of:
Acquiring a first pulse signal and a first time signal, wherein the time sequences of the first pulse signal and the first time signal correspond to each other;
Generating a second pulse signal of the first controller, and sampling the first pulse signal to obtain a first rising edge;
resetting the second pulse signal according to the first rising edge to synchronize the second time signal of the first controller according to the first time signal
In one embodiment, the computer program when executed by the processor further performs the steps of:
the step of resetting the second pulse signal according to the first rising edge includes:
Acquiring the number of the first rising edges, first pulse widths corresponding to the first rising edges and first interval duration between two adjacent first rising edges;
resetting the second pulse signal of the first controller according to the number of the first rising edges, the first pulse width and the first interval duration, so that the second rising edges of the second pulse signal and the first rising edges of the first pulse signal are aligned.
In one embodiment, the computer program when executed by the processor further performs the steps of:
The time synchronization method applied to the controller according to any one of the first to third embodiments, further comprising:
Encoding the second pulse signal to obtain a first data frame, wherein the first data frame comprises a first byte, and the first byte corresponds to the time sequence of a second rising edge of the second pulse signal;
Generating a third pulse signal of at least one second controller, recovering the first data frame into a second pulse signal, and sampling the second pulse signal to obtain a second rising edge;
And resetting each third pulse signal according to the second rising edge when the first byte is received, so as to synchronize the third time signals of each second controller according to the second time signals of the first controller.
In one embodiment, the computer program when executed by the processor further performs the steps of:
Before the step of resetting each third pulse signal according to the first byte, the method further includes:
obtaining a signal to be checked according to the first data frame and the second time signal, and sending the first data frame, the second time signal and the signal to be checked according to a time sequence;
performing cyclic redundancy check on the received first data frame and the second time signal to obtain a check signal, and comparing the check signal with a received signal to be checked;
And executing the step of resetting each third pulse signal according to the second rising edge under the condition that the verification signal is consistent with the signal to be verified.
In one embodiment, the computer program when executed by the processor further performs the steps of:
the step of resetting each third pulse signal according to the second rising edge includes:
when a first byte is received, acquiring the number of the second rising edges, second pulse widths corresponding to the second rising edges and second interval duration between two adjacent second rising edges;
Resetting the third pulse signals of the second controllers according to the number of the second rising edges, the second pulse widths and the second interval durations so that the third rising edges of the third pulse signals are aligned with the second rising edges of the second pulse signals respectively.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (SYNCHLINK) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (8)
1. A time synchronization method of an in-vehicle controller, comprising:
Acquiring a first pulse signal and a first time signal, wherein the time sequences of the first pulse signal and the first time signal correspond to each other;
Generating a second pulse signal of the first controller, and sampling the first pulse signal to obtain a first rising edge;
Resetting the second pulse signal according to the first rising edge so as to synchronize a second time signal of the first controller according to the first time signal;
Encoding the second pulse signal to obtain a first data frame, wherein the first data frame comprises a first byte, and the first byte corresponds to the time sequence of a second rising edge of the second pulse signal;
Generating a third pulse signal of at least one second controller, recovering the first data frame into a second pulse signal, and sampling the second pulse signal to obtain a second rising edge;
And resetting each third pulse signal according to the second rising edge when the first byte is received, so as to synchronize the third time signals of each second controller according to the second time signals of the first controller.
2. The time synchronization method of the in-vehicle controller according to claim 1, wherein the step of resetting the second pulse signal according to the first rising edge includes:
Acquiring the number of the first rising edges, first pulse widths corresponding to the first rising edges and first interval duration between two adjacent first rising edges;
resetting the second pulse signal of the first controller according to the number of the first rising edges, the first pulse width and the first interval duration, so that the second rising edges of the second pulse signal and the first rising edges of the first pulse signal are aligned.
3. The method according to claim 1, wherein before the step of resetting each of the third pulse signals according to the first byte, further comprising:
obtaining a signal to be checked according to the first data frame and the second time signal, and sending the first data frame, the second time signal and the signal to be checked according to a time sequence;
performing cyclic redundancy check on the received first data frame and the second time signal to obtain a check signal, and comparing the check signal with a received signal to be checked;
And executing the step of resetting each third pulse signal according to the second rising edge under the condition that the verification signal is consistent with the signal to be verified.
4. The time synchronization method of the in-vehicle controller according to claim 1, wherein the step of resetting each of the third pulse signals according to the second rising edge includes:
when a first byte is received, acquiring the number of the second rising edges, second pulse widths corresponding to the second rising edges and second interval duration between two adjacent second rising edges;
Resetting the third pulse signals of the second controllers according to the number of the second rising edges, the second pulse widths and the second interval durations so that the third rising edges of the third pulse signals are aligned with the second rising edges of the second pulse signals respectively.
5. A time synchronization device of an in-vehicle controller, comprising a first controller and at least one second controller, the first controller comprising:
the receiving chip is used for acquiring a first pulse signal and a first time signal, wherein the time sequences of the first pulse signal and the first time signal correspond to each other;
the first processing chip comprises a first counter and a first clock, wherein the first counter is used for generating a second pulse signal of the first controller, and the first clock is used for sampling the first pulse signal to obtain a first rising edge;
The first processing chip is used for resetting the first counter according to the first rising edge so as to reset the second pulse signal and synchronizing a second time signal of the first controller according to the first time signal;
The first controller is further configured to encode a second pulse signal to obtain a first data frame, where the first data frame includes a first byte, and the first byte corresponds to a timing sequence of a second rising edge of the second pulse signal;
Each of the second controllers includes:
The second processing chip comprises a second counter and a second clock, wherein the second counter is used for generating a third pulse signal of the second controller, and the second clock is used for sampling the second pulse signal to obtain a second rising edge;
the second processing chip is further configured to clear the second counter according to the second rising edge when the first byte is received, reset the third pulse signal, and synchronize a third time signal of the second controller according to a second time signal of the first controller.
6. The time synchronization device of an in-vehicle controller according to claim 5, wherein,
The first controller is further configured to obtain a signal to be checked according to the first data frame and the second time signal, and send the first data frame, the second time signal and the signal to be checked according to a time sequence;
the second processing chip is also used for performing cyclic redundancy check on the received first data frame and the second time signal to obtain a check signal, and comparing the check signal with a received signal to be checked;
The second processing chip is further configured to execute a step of resetting the third pulse signal according to the second rising edge when the verification signal is consistent with the signal to be verified.
7. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the time synchronization method of the in-vehicle controller of any one of claims 1 to 4 when the computer program is executed by the processor.
8. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the time synchronization method of the in-vehicle controller of any one of claims 1 to 4.
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| CN101119192B (en) * | 2007-09-11 | 2010-09-29 | 杭州华三通信技术有限公司 | Clock synchronization method and system |
| JP2010279235A (en) * | 2009-06-01 | 2010-12-09 | Mitsubishi Electric Corp | Current differential relay |
| CN102142954B (en) * | 2010-11-30 | 2014-11-05 | 中兴通讯股份有限公司 | Time synchronization method and equipment in rack |
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| CN104333426B (en) * | 2014-09-25 | 2017-04-12 | 国家电网公司 | Pulse per second synchronization method based on merging unit SV message sampling sequence number learning |
| CN107655475B (en) * | 2017-11-03 | 2024-03-26 | 河南思维轨道交通技术研究院有限公司 | Synchronous pulse signal acquisition method, navigation data synchronous processing method and system |
| CN108802734B (en) * | 2018-06-20 | 2020-10-02 | 清华大学 | A method and device for controlling the timing synchronization of a radar system |
| CN111585682B (en) * | 2020-05-09 | 2022-10-04 | 森思泰克河北科技有限公司 | Sensor time synchronization method and device and terminal equipment |
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| CN114608566A (en) * | 2020-12-08 | 2022-06-10 | 图森有限公司 | Hardware-based time synchronization of heterogeneous sensors in autonomous vehicles |
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