CN115793955A - Storage device, data processing method thereof, and computer-readable storage medium - Google Patents
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Abstract
The application relates to the technical field of storage devices, and discloses a storage device, a data processing method thereof and a computer readable storage medium. The method comprises the following steps: when the first target data is written, acquiring a plurality of continuous first logical addresses corresponding to the first target data and a plurality of first physical addresses mapped by the plurality of first logical addresses respectively; compressing the mapping relation between a plurality of first logical addresses and a plurality of first physical addresses to form a first log record; writing the first log record into a mapping relation log; the mapping relation log is used for updating the recorded mapping relation to the memory according to a preset time period. By the method, the storage space occupied by the mapping relation logs in the storage device can be reduced, and the available storage space of the storage device is further improved.
Description
Technical Field
The present application relates to the field of storage device technologies, and in particular, to a storage device, a data processing method thereof, and a computer-readable storage medium.
Background
In a storage device, it is generally necessary to store a mapping relationship between each logical address and each physical address, so that when data is read, the physical address is acquired according to the mapping relationship, and the data is read from a data storage area according to the physical address.
At present, each logical address and each physical address are recorded according to a one-to-one correspondence relationship, and on the premise of storing a large amount of data, the storage space occupied correspondingly is huge.
Disclosure of Invention
The storage device, the data processing method thereof and the computer readable storage medium are provided, which can reduce the storage space occupied by the mapping relation log in the storage device, thereby improving the available storage space of the storage device.
In order to solve the above problem, a technical solution adopted by the present application is to provide a data processing method of a storage device, the method including: when the first target data is written, acquiring a plurality of continuous first logical addresses corresponding to the first target data and a plurality of first physical addresses mapped by the first logical addresses respectively; compressing the mapping relation between a plurality of first logical addresses and a plurality of first physical addresses to form a first log record; writing the first log record into a mapping relation log; the mapping relation log is used for updating the recorded mapping relation to the memory according to a preset time period.
Wherein, compressing the mapping relation between a plurality of first logical addresses and a plurality of first physical addresses to form a first log record comprises: determining a first number of the plurality of first logical addresses; acquiring a first logical address generated by a first one of a plurality of first logical addresses and a corresponding first physical address; a first log record is formed based on the first generated first logical address and the corresponding first physical address and first number.
Wherein, the method also comprises: when reading operation is carried out on second target data, a plurality of second logic addresses corresponding to the second target data are obtained; determining whether the second logical address is within the first log record; if so, determining a second physical address corresponding to the second logical address by using the first log record and the second logical address.
Wherein determining whether the second logical address is within the first log record comprises: calculating a logical address range recorded in the first log record by using the first number and the first generated logical address; it is determined whether the second logical address is within the logical address range.
The determining a second physical address corresponding to the second logical address by using the first log record and the second logical address includes: determining a target location of the second logical address within the logical address range; determining a difference between the target location and a location of the first logical address in the first log record; the difference and the first physical address in the first log record are used to obtain the second physical address.
Wherein, the method also comprises: when the third target data is subjected to erasing operation, obtaining a plurality of continuous third logical addresses corresponding to the third target data and a plurality of third physical addresses mapped by the third logical addresses; compressing the mapping relation between the plurality of third logical addresses and the third physical addresses to form a second log record; and writing the second log record into the mapping relation log.
Compressing the mapping relationship between the plurality of third logical addresses and the third physical addresses to form a second log record, comprising: determining a second number of a plurality of third logical addresses; acquiring a first generated third logical address in the plurality of third logical addresses; a second log record is formed based on the first generated third logical address, and the third physical address and the second quantity.
Wherein, the method also comprises: when reading the fourth target data, acquiring a third logical address corresponding to the fourth target data; determining whether the third logical address is within the second log record; if yes, a third physical address is obtained.
In order to solve the above problem, another technical solution adopted by the present application is to provide a storage device, which includes a processor and a memory coupled to the processor; wherein the memory is used for storing computer programs, and the processor is used for executing the computer programs so as to realize the method provided by the technical scheme.
In order to solve the above problem, another technical solution adopted by the present application is to provide a computer-readable storage medium for storing a computer program, which when executed by a processor is used for implementing the method provided by the above technical solution.
The beneficial effect of this application is: different from the prior art, the present application provides a data processing method for a storage device, which enables each log record to record more mapping relationships between logical addresses and physical addresses by compressing the mapping relationships between a plurality of first logical addresses and a plurality of first physical addresses to form a first log record, thereby reducing the storage space occupied by the mapping relationship log in the storage device and further increasing the available storage space of the storage device.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic flowchart of an embodiment of a data processing method of a storage device provided in the present application;
FIG. 2 is a schematic flow chart diagram illustrating a data processing method of a storage device according to another embodiment of the present disclosure;
FIG. 3 is a schematic flow chart diagram illustrating a data processing method of a storage device according to another embodiment of the present disclosure;
FIG. 4 is a schematic flow chart diagram illustrating one embodiment of step 32 provided herein;
FIG. 5 is a schematic flow chart diagram illustrating an embodiment of step 33 provided herein;
FIG. 6 is a flow chart illustrating a data processing method of a storage device according to another embodiment of the present disclosure;
FIG. 7 is a schematic flow chart diagram illustrating one embodiment of step 62 provided herein;
FIG. 8 is a schematic flowchart illustrating a data processing method of a storage device according to another embodiment of the present disclosure;
FIG. 9 is a schematic structural diagram of an embodiment of a memory device provided herein;
FIG. 10 is a schematic structural diagram of an embodiment of a computer-readable storage medium provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
The terms "first", "second", etc. in this application are used to distinguish different objects, and are not used to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic flowchart illustrating an embodiment of a data processing method of a storage device provided in the present application, where the method includes:
step 11: when the first target data is written, a plurality of continuous first logic addresses corresponding to the first target data and a plurality of first physical addresses mapped by the first logic addresses are obtained.
In some embodiments, the storage device is connected to an external control device, and can interact with the external control device to complete reading and writing of data.
The data writing can be performed sequentially or randomly. When writing sequentially, continuous logical addresses are generated correspondingly, and correspondingly, continuous physical addresses are generated correspondingly in the storage space of the storage device.
Therefore, the case of sequentially writing data is mainly described in the present embodiment.
Step 12: the mapping relation between the first logical addresses and the first physical addresses is compressed to form a first log record.
The applicant has found that long-term research shows that the storage device records a logical address and a corresponding physical address to generate a log record. Then as more data is written, the more log records, the more storage space the corresponding storage device occupies. Based on this, in order to save the storage space of the storage device, the application compresses the mapping relationship between the plurality of first logical addresses and the plurality of first physical addresses to form one log record.
Step 13: writing the first log record into a mapping relation log; the mapping relation log is used for updating the recorded mapping relation to the memory according to a preset time period.
It is understood that a plurality of log records, such as log records generated by randomly writing data, may be recorded in the mapping relationship log.
In an application scenario, after the first target data is written, if the data is written again, and at this time, the data corresponds to a plurality of continuous logical addresses and a plurality of physical addresses mapped by the plurality of logical addresses respectively. And if the logical address generated by the first of the plurality of logical addresses is detected to be continuous with the last first logical address in the first target data, fusing the log record generated by the corresponding logical address and the physical address at the moment with the log record of the first target data to generate a log record, thereby reducing the occupation of the storage space.
If the previous journal record is a, a plurality of consecutive logical addresses and corresponding physical addresses are generated when data is written this time. And calculating the last recorded logical address according to the log record A, comparing the last logical address with the first logical address generated at this time, and if the two logical addresses are continuous, directly fusing the logical address and the physical address generated at this time with the log record A to obtain a new log record B.
It is understood that when any one generates a logical address, the logical address can be associated with any log record to determine whether it can be continued with the logical address therein, and if so, the mapping relationship between the logical address and the physical address is written into the log record.
It will be appreciated that the physical addresses are written sequentially or randomly by the storage device apparatus, and that the physical addresses may be contiguous.
In this embodiment, by compressing the mapping relationship between the plurality of first logical addresses and the plurality of first physical addresses to form one first log record, each first log record can record more mapping relationships between the logical addresses and the physical addresses, so as to reduce the storage space occupied by the mapping relationship log in the storage device, thereby increasing the available storage space of the storage device.
Referring to fig. 2, fig. 2 is a schematic flowchart of another embodiment of a data processing method of a storage device provided in the present application, the method including:
step 21: when the first target data is written, a plurality of continuous first logic addresses corresponding to the first target data and a plurality of first physical addresses mapped by the first logic addresses are obtained.
Step 22: a first number of the plurality of first logical addresses is determined.
Step 23: a first logical address generated by a first one of the plurality of first logical addresses and a corresponding first physical address are obtained.
And step 24: a first log record is formed based on the first generated first logical address and the corresponding first physical address and first number.
The steps 22-24 are illustrated:
when the first target data is written, seven first logical addresses La, lb, lc, ld, le, lf, and Lg are obtained. The corresponding physical addresses are Pa, pb, pc, pd, pe, pf and Pg, in which case it is determined that the first number is 7, the first logical address La is first generated, and the corresponding first physical address Pa.
The first log record at this time can be represented as (La, pa, 7).
In summary, if L represents the first of the consecutive logical addresses, P represents the corresponding physical address, and N represents the number of logical addresses, the first log record can be represented as (L, P, N).
Step 25: writing the first log record into a mapping relation log; the mapping relation log is used for updating the recorded mapping relation to the memory according to a preset time period.
In this embodiment, by compressing the mapping relationship between the plurality of first logical addresses and the plurality of first physical addresses to form one first log record, each log record can record more mapping relationships between the logical addresses and the physical addresses, so as to reduce the storage space occupied by the mapping relationship log in the storage device, thereby increasing the available storage space of the storage device.
After logging is performed according to any of the above embodiments, how to read data according to the log record is described with the following embodiments, specifically, referring to fig. 3, fig. 3 is a schematic flow chart of another embodiment of a data processing method of a storage device provided by the present application, where the method includes:
step 31: and when the second target data is read, acquiring a plurality of second logic addresses corresponding to the second target data.
It is understood that the read operation of the second target data may be a random read or a sequential read.
It can be understood that randomly written data is journaled in a manner that one logical address corresponds to one journal record.
Step 32: it is determined whether the second logical address is within the first log record.
If the second logical address is not in the first log record, it means that the second logical address is in the log record generated by randomly writing data, and the physical address can be directly obtained from the log record, so that the data can be obtained from the physical address.
If the second logical address is in the first log record, step 33 is performed.
In some embodiments, referring to fig. 4, step 32 may be the following step:
step 321: a range of logical addresses recorded by the first log record is calculated using the first number and the first logical address generated first.
Step 322: it is determined whether the second logical address is within the logical address range.
The following illustrates steps 321-322:
for example, the first log record is (La, pa, 7), and the logical address range of the first log record is calculated as La to Lg using the first number 7 and the first generated logical address La. If the second logical address is Lc and is within the logical address range, step 33 is executed. If the second logical address is Lh and is not within the logical address range, the second logical address is continuously compared with other log records to determine the corresponding physical address.
It will be appreciated that each second logical address is compared with the log records in a traversal order to determine the corresponding physical address.
Step 33: and determining a second physical address corresponding to the second logical address by using the first log record and the second logical address.
And determining a second physical address corresponding to the second logical address by using the first number, the first physical address and the first logical address recorded in the first log record.
In some embodiments, referring to fig. 5, step 33 may be the following step:
step 331: a target location for the second logical address within the logical address range is determined.
Step 332: a difference between the target location and the location of the first logical address in the first log record is determined.
Step 333: the difference and the first physical address in the first log record are used to obtain the second physical address.
The following steps 331-333 are illustrated:
for example, the first log record is (La, pa, 7), and the logical address range described in the first log record is La to Lg. If the second logical address is Lc, the target position in the logical address range is the third one. The difference with the position of the first logical address La is 2. Similarly, the physical address range described in the first log record is Pa to Pg. By using the difference 2 and the first physical address Pa in the first log record, it can be determined that the second logical address Lc is the third physical address in the physical range, and the first physical address Lc is the first physical address Pc.
In this embodiment, the first log record is parsed to obtain a second physical address corresponding to the second target data, so as to read the physical address from the compressed first log record, thereby forming an entire flow of data writing and reading. On the premise of reducing the storage space occupied by the mapping relation log in the storage device, the reading of data is not influenced, and the performance of the storage device is improved.
Based on the fact that the mapping relationship between the logical address and the physical address also exists when data erasure is performed, and accordingly, recording is also required, the present application proposes a technical solution of fig. 6 for description, and specifically refer to fig. 6, where fig. 6 is a schematic flow diagram of another embodiment of a data processing method of a storage device provided by the present application, and the method includes:
step 61: when the third target data is erased, a plurality of continuous third logical addresses corresponding to the third target data and a plurality of third physical addresses mapped by the third logical addresses are obtained.
When data is operated, the mapping relationship between the logical address and the physical address of the data already exists before, which is essentially to change the mapping relationship between the logical address and the physical address so that the logical address points to a fixed value, which means that the data is erased, and the data at the corresponding physical address is also erased.
Step 62: and compressing the mapping relation of the plurality of third logical addresses and the third physical addresses to form a second log record.
The applicant has found that, through long-term research, the storage device records each erased logical address and a corresponding special physical address to generate a log record. Then as more data is erased, more log records, and more storage space is occupied in the storage device. Based on this, in order to save the storage space of the storage device, the application compresses the mapping relationship between a plurality of third logical addresses and a third physical address to form a log record.
In some embodiments, referring to fig. 7, step 62 may be the following step:
step 621: a second number of the plurality of third logical addresses is determined.
Step 622: a first generated third logical address of the plurality of third logical addresses is obtained.
Step 623: a second log record is formed based on the first generated third logical address, and the third physical address and the second quantity.
Steps 621-623 are illustrated:
when the third target data is subjected to the erasing operation, seven third logical addresses La, lb, lc, ld, le, lf, and Lg are obtained. At this time, the third physical addresses corresponding to these third logical addresses are-0, and at this time, it is determined that the second number is 7, and the third logical address La is generated first. Then the second log record may be represented at this time as (La, -0, 7).
In summary, if L denotes the first of consecutive third logical addresses, -0 denotes the corresponding third physical address, and N denotes the number of logical addresses, the second log record may be denoted as (L, -0, N).
And step 63: and writing the second log record into the mapping relation log.
In this embodiment, by compressing the mapping relationship between the plurality of third logical addresses and the third physical addresses to form one second log record, each second log record can record more mapping relationships between the logical addresses and the physical addresses of the erasure data, so as to reduce the storage space occupied by the mapping relationship log in the storage device, thereby increasing the available storage space of the storage device.
Referring to fig. 8, fig. 8 is a schematic flowchart illustrating a data processing method of a memory device according to another embodiment of the present disclosure, where the method includes:
step 81: and when the fourth target data is read, acquiring a fourth logical address corresponding to the fourth target data.
It is understood that the read operation of the fourth target data may be a random read or a sequential read.
Step 82: it is determined whether the fourth logical address is within the second log record.
If the fourth logical address is not in the second log record, it indicates that the physical address corresponding to the fourth logical address exists, that is, the fourth target data is not erased. The physical address can be obtained from other log records and the data obtained from that physical address.
If the fourth logical address is in the second log record, go to step 83.
Specifically, whether the fourth logical address is in the second log record may be determined in the following manner:
a range of logical addresses recorded by the second log record is calculated using the second number and the first generated third logical address. It is determined whether the fourth logical address is within the logical address range, and if yes, go to step 83.
Step 83: and acquiring the third physical address.
Since the physical addresses of all the erased data point to the same address, the third physical address in the second log record can be directly returned as data.
Referring to fig. 9, fig. 9 is a schematic structural diagram of an embodiment of a memory device provided in the present application. The storage device 90 includes a processor 91 and a memory 92 coupled to the processor 91; wherein the memory 92 is used for storing a computer program, and the processor 91 is used for executing the computer program to implement the following method:
when the first target data is written, acquiring a plurality of continuous first logical addresses corresponding to the first target data and a plurality of first physical addresses mapped by the plurality of first logical addresses respectively; compressing the mapping relation between a plurality of first logical addresses and a plurality of first physical addresses to form a first log record; writing the first log record into a mapping relation log; the mapping relation log is used for updating the recorded mapping relation to the memory according to a preset time period.
It is to be understood that the processor 91 is also configured to execute a computer program to implement the method of any of the above embodiments, which is not described herein again.
Referring to fig. 10, fig. 10 is a schematic structural diagram of an embodiment of a computer-readable storage medium provided in the present application. The computer-readable storage medium 100 is for storing a computer program 101, the computer program 101, when being executed by a processor, is for implementing the method of:
when the first target data is written, acquiring a plurality of continuous first logical addresses corresponding to the first target data and a plurality of first physical addresses mapped by the first logical addresses respectively; compressing the mapping relation between a plurality of first logical addresses and a plurality of first physical addresses to form a first log record; writing the first log record into a mapping relation log; the mapping relation log is used for updating the recorded mapping relation to the memory according to a preset time period.
It is understood that the computer program 101, when executed by a processor, is for implementing the method of any of the above embodiments, and is not described herein in detail.
The technical scheme provided by the application can be applied to a Storage device based on a Flash memory, such as an SSD (Solid State Disk or Solid State Drive), a UFS (Universal Flash Storage), an eMMC, etc., where the FTL (Flash Translation Layer) adopts a page mapping manner, and compared with the conventional block mapping manner, the Storage device adopting the page mapping manner has better random write performance, but has a disadvantage that a mapping table (for storing physical addresses of logical blocks in the Flash memory) is very large, generally 1/1024 of the Storage device capacity, such as 1TB, where the size of the mapping table is 1GB. Conventional SSDs are generally configured with a DRAM (Dynamic Random Access Memory) with a corresponding size to store a mapping table during operation, so that the firmware update and lookup speed are fast.
In some consumer SSDs and mobile storage devices, such as UFS and eMMC, due to cost and power consumption, there is usually no DRAM configured, and a firmware architecture of DRAM-less is adopted in software design, specifically, most mapping tables are stored in flash Memory, and when the storage device is running, mapping table data is loaded into a mapping table cache, typically an SRAM (Static Random-Access Memory) with a size of tens to hundreds of KB, as required. For example, to read a logical address, a mapping table cache is searched first, if hit, a physical address corresponding to the logical address is directly obtained, and then the flash memory is read according to the physical address to obtain final user data. However, since the mapping table cache is very small, the mapping table cache will not hit the cache at a very high probability, and the mapping table data needs to be loaded in the flash memory temporarily, and then the user data is read according to the physical address. Compared with the DRAM memory device, the DRAM-less memory device requires more accesses to the flash memory, and thus has much poorer read/write performance, especially in terms of random read/write performance.
In the DRAM-less storage device, the updating of the mapping table is also a problem. Writing of user data, erasing (such as Trim), and garbage collection inside the storage device all result in updating the mapping. For the storage device of DRAM-less, because the mapping table is in the flash memory, it is largely impossible to load the corresponding mapping relation in the flash memory every time a mapping relation is generated, then update and write back to the flash memory, otherwise, the write performance, especially the random write performance, will be very bad.
In order to solve the problem of updating the mapping table, the storage device of DRAM-less usually adopts a log mode, i.e. the generated mapping relationships (logical addresses and physical addresses) are recorded in the mapping relationship log of SRAM first, and then the mapping relationships are updated in a centralized manner after being gathered to a certain number.
When the mapping table is updated, the corresponding mapping block (the basic unit for loading and updating the mapping table data, generally 2KB or 4 KB) is loaded into the flash memory according to the mapping relation log, the old mapping relation is replaced by the new mapping relation, and the new mapping relation is finally written back to the flash memory after the updating is finished.
The mode of delaying batch updating avoids frequent loading and updating of the flash memory, and improves the performance and the service life of the storage device. According to the scheme, the log records are compressed, each log record can store more mapping relations between the logical address blocks and the physical addresses, and therefore the size of a log buffer area of the mapping relations is reduced. This is significant for DRAM-less memory devices, which have only a limited size of SRAM to store the map log, and reducing the size of the map log reduces the use of SRAM.
In summary, when the technical scheme provided by the application is applied to a DRAM-less storage device, the size of the mapping relation log is greatly reduced by compressing the mapping relation, so that the use of the SRAM on the storage device is greatly reduced, and the performance of the storage device can be improved.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each of the units may exist alone physically, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated units in the other embodiments described above may be stored in a computer-readable storage medium if they are implemented in the form of software functional units and sold or used as separate products. Based on such understanding, the technical solutions of the present application, which are essential or contributing to the prior art, or all or part of the technical solutions may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the methods according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, and various media capable of storing program codes.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A method of data processing of a storage device, the method comprising:
when a first target data is subjected to a write operation, acquiring a plurality of continuous first logical addresses corresponding to the first target data and a plurality of first physical addresses mapped by the plurality of first logical addresses respectively;
compressing the mapping relation between the plurality of first logical addresses and the plurality of first physical addresses to form a first log record;
writing the first log record into a mapping relation log; and the mapping relation log is used for updating the recorded mapping relation to the memory according to a preset time period.
2. The method of claim 1,
compressing the mapping relationship between the plurality of first logical addresses and the plurality of first physical addresses to form a first log record, including:
determining a first number of the plurality of first logical addresses;
acquiring a first logical address generated by a first one of the plurality of first logical addresses and a corresponding first physical address;
forming one of said first log records based on a first generated logical address and a corresponding first physical address and said first number.
3. The method of claim 2,
the method further comprises the following steps:
when reading second target data, acquiring a plurality of second logic addresses corresponding to the second target data;
determining whether the second logical address is within the first log record;
and if so, determining a second physical address corresponding to the second logical address by using the first log record and the second logical address.
4. The method of claim 3,
the determining whether the second logical address is within the first log record includes:
calculating a logical address range recorded by the first log record by using the first number and the first generated first logical address;
and judging whether the second logical address is in the logical address range.
5. The method of claim 4,
the determining a second physical address corresponding to the second logical address by using the first log record and the second logical address includes:
determining a target location of the second logical address within the logical address range;
determining a difference between the target location and the location of the first logical address in the first log record;
the second physical address is obtained using the difference and the first physical address in the first log record.
6. The method of claim 1,
the method further comprises the following steps:
when a third target data is subjected to an erasing operation, obtaining a plurality of continuous third logical addresses corresponding to the third target data and a third physical address mapped by the plurality of third logical addresses;
compressing the mapping relation between the plurality of third logical addresses and the third physical addresses to form a second log record;
and writing the second log record into a mapping relation log.
7. The method of claim 6,
compressing the mapping relationship between the plurality of third logical addresses and the third physical address to form a second log record, including:
determining a second number of the plurality of third logical addresses;
obtaining a third logical address generated by a first one of the plurality of third logical addresses;
forming the second log record based on the first generated third logical address, and the third physical address and the second quantity.
8. The method of claim 7,
the method further comprises the following steps:
when reading fourth target data, acquiring a third logical address corresponding to the fourth target data;
determining whether the third logical address is within the second log record;
and if so, acquiring the third physical address.
9. A memory device, comprising a processor and a memory coupled to the processor;
wherein the memory is adapted to store a computer program and the processor is adapted to execute the computer program to implement the method according to any of claims 1-8.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium is used for storing a computer program which, when being executed by a processor, is used for carrying out the method according to any one of the claims 1-8.
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