CN115766526B - Method and device for testing physical layer chip of switch and electronic equipment - Google Patents

Abstract

The invention provides a method and a device for testing a physical layer chip of a switch and electronic equipment, wherein the method comprises the following steps: through the MDC interface of the management data clock and the MDIO interface of the management data input and output, each PHY port of the PHY chip of the physical layer is configured to be in a loop-back state; and (3) through performing a line speed flow test on each PHY port, acquiring a port test result of each PHY port, wherein the port test result is used for indicating whether the PHY port passes the test. According to the invention, through the MDC interface and the MDIO interface, each PHY port of the PHY chip can be configured to be in a loop-back state, so that the line speed flow test can be performed on each PHY port, test case data transmitted to each PHY port of the PHY chip in the test process can be analyzed through loop-back of the PHY chip, the port test result of each PHY port can be obtained, an external jig is not required in the test process, and the test efficiency can be improved.

Description

Switch physical layer chip testing method, device and electronic equipment

Technical Field

The present invention relates to the field of computer technology, and in particular to a test method, device and electronic equipment for a physical layer chip of a switch.

Background technique

The physical layer (Physical Layer, PHY) of the switch processes the data of the media access control layer (Media Access Control, MAC), converts parallel data into serial data, encodes it according to the rules of the physical layer, and then converts it into an analog signal to send the data out. It can also implement some Carrier Sense Multiple Access/Collision Detection (CSMA/CD) functions with collision detection, and is an important part of the switch. With the development of network technology, the use of PHY chips in switches is getting larger and larger.

The PHY port testing technology in the related art mostly uses external fixtures (such as optical modules, eload and other fixtures) to connect the transmit (tx) port and receive (rx) port of each lane through a DC blocking capacitor, and then perform a flow test, which has low test efficiency.

Summary of the invention

In view of the problems existing in the prior art, the embodiments of the present invention provide a method, a device and an electronic device for testing a physical layer chip of a switch.

In a first aspect, the present invention provides a test method for a switch physical layer chip, comprising: configuring each PHY port of a physical layer PHY chip to a loopback state by managing a data clock MDC interface and a data input and output MDIO interface;

By performing a line-speed flow test on each PHY port, a port test result of each PHY port is obtained, and the port test result is used to indicate whether the PHY port passes the test.

Optionally, according to a test method for a switch physical layer chip provided by the present invention, the step of performing a line rate flow test on each PHY port to obtain a port test result of each PHY port includes:

Get the connection status of each PHY port;

If it is determined that the connection status of each PHY port is a connection establishment status, the test case data is sent to each PHY port through the sending TX port of the media access control layer MAC;

Receive loopback data from each PHY port through the MAC's RX port;

Based on the test case data, the loopback data of each PHY port and the connection status monitoring data of each PHY port, a port test result of each PHY port is obtained.

Optionally, according to a test method for a switch physical layer chip provided by the present invention, obtaining a port test result of each PHY port based on the test case data, the loopback data of each PHY port, and the connection status monitoring data of each PHY port includes:

Based on the test case data and the loopback data of each PHY port, determine the difference information of the number of sent and received packets of each PHY port and the error packet information of each PHY port;

Based on the connection status monitoring data of each PHY port, the difference information of the number of sent and received packets, and the error packet information, it is determined whether each PHY port passes the test, and the port test result of each PHY port is obtained.

Optionally, according to a test method for a switch physical layer chip provided by the present invention, after performing a line rate flow test on each PHY port to obtain a port test result of each PHY port, the method further includes:

When the port test result of the target PHY port indicates that the target PHY port has failed the test, determining a target fault keyword based on the connection status monitoring data, the difference information of the number of sent and received packets, and the error packet information of the target PHY port;

Based on the target fault keyword and the fault table, a target fault diagnosis instruction is acquired, wherein the fault table is used to characterize a mapping relationship between the fault keyword and the fault diagnosis instruction, and the fault diagnosis instruction is used to assist in diagnosing the PHY port;

Obtaining fault diagnosis information of the target PHY port by executing the target fault diagnosis instruction;

The target PHY port is any PHY port of the PHY chip.

Optionally, according to a test method for a switch physical layer chip provided by the present invention, after acquiring the fault diagnosis information of the target PHY port, the method further includes:

Determine the fault reporting information of the target PHY port based on the connection status monitoring data of the target PHY port, the difference information of the number of sent and received packets, the error packet information and the fault diagnosis information;

Send the fault reporting information of the target PHY port to the server.

Optionally, a test method for a switch physical layer chip provided by the present invention further includes:

Polling multiple registers of the PHY chip through the MDC interface and the MDIO interface to obtain storage values of the multiple registers, wherein the multiple registers include an interrupt register, a control register, and a status register;

Based on the reference value of each register and the storage value of each register, the operation status information of the PHY chip is determined, and the operation status information is used to indicate whether the PHY chip fails.

Optionally, according to a test method for a switch physical layer chip provided by the present invention, after determining the operating status information of the PHY chip, the method further includes:

In a case where the operating status information indicates that a fault occurs in the PHY chip, the storage value of each register is configured as a reference value of each register.

In a second aspect, the present invention further provides a test device for a switch physical layer chip, comprising:

The first configuration module is used to configure each PHY port of the physical layer PHY chip to a loopback state through a management data clock MDC interface and a management data input and output MDIO interface;

The test module is used to obtain the port test result of each PHY port by performing a line speed flow test on each PHY port, and the port test result is used to indicate whether the PHY port passes the test.

In a third aspect, the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, a test method for a physical layer chip of a switch as described above is implemented.

In a fourth aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the test method for the physical layer chip of a switch as described in any one of the above is implemented.

The switch physical layer chip testing method, device and electronic device provided by the present invention can configure each PHY port of the PHY chip to be in a loopback state through an MDC interface and an MDIO interface, and then perform a line speed flow test on each PHY port. During the test, the test case data sent to each PHY port of the PHY chip can be looped back through the PHY chip, and then the loopback data of each PHY port can be analyzed, and the port test results of each PHY port can be obtained. The port test results can indicate whether the PHY port passes the test. No external fixture is required during the test, and the test efficiency can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a schematic flow chart of a method for testing a physical layer chip of a switch provided by the present invention;

FIG2 is a schematic diagram of the hardware connection structure of the line speed flow test provided by the present invention;

3 is a schematic diagram of the structure of a test device for a switch physical layer chip provided by the present invention;

FIG. 4 is a schematic diagram of the structure of an electronic device provided by the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

FIG1 is a flow chart of a test method for a physical layer chip of a switch provided by the present invention. As shown in FIG1 , the execution subject of the test method for a physical layer chip of a switch may be an electronic device. The method comprises:

Step 101, configuring each PHY port of the physical layer PHY chip to a loopback state through a management data clock MDC interface and a management data input and output MDIO interface;

Specifically, in order to improve the test efficiency, each PHY port of the PHY chip can be configured to be in a loopback state through the Management Data Clock (MDC) interface and the Management Data Input Output (MDIO) interface, and then the test case data sent to each PHY port of the PHY chip can be looped back through the PHY chip.

It can be understood that through the MDC interface and the MDIO interface, each port of the PHY chip can be configured as a Lineinternal loopback, so that the traffic can be sent out from the MAC port tx, then looped back through the PHY chip and returned to the MAC port rx, thereby achieving testing without relying on external fixtures.

Step 102, by performing a line rate flow test on each PHY port, a port test result of each PHY port is obtained, wherein the port test result is used to indicate whether the PHY port passes the test.

Specifically, after configuring each PHY port of the PHY chip to be in a loopback state, a line-speed traffic test can be performed on each PHY port. During the test, test case data can be sent to each PHY port of the PHY chip. The test case data is used to test each PHY port. Through the PHY chip loopback, the loopback data of each PHY port can be analyzed to obtain the port test results of each PHY port. The port test results can indicate whether the PHY port passes the test.

For example, a PHY chip may include three PHY ports, namely port A, port B and port C. Port A, port B and port C may be configured to be in a loopback state through the MDC interface and the MDIO interface. During the test, test case data may be sent to port A, port B and port C. Through the PHY chip loopback, the loopback data of port A, port B and port C may be analyzed, and the port test results of each PHY port may be obtained.

The switch physical layer chip testing method provided by the present invention can configure each PHY port of the PHY chip to be in a loopback state through an MDC interface and an MDIO interface, and then a line speed flow test can be performed on each PHY port. During the test, the test case data sent to each PHY port of the PHY chip can be looped back through the PHY chip, and then the loopback data of each PHY port can be analyzed, and the port test result of each PHY port can be obtained. The port test result can indicate whether the PHY port passes the test. No external fixture is required in the test process, and the test efficiency can be improved.

Optionally, the present invention provides a method for testing a physical layer chip of a switch, wherein the method performs a line rate flow test on each PHY port to obtain a port test result of each PHY port, comprising:

Get the connection status of each PHY port;

If it is determined that the connection status of each PHY port is a connection establishment status, the test case data is sent to each PHY port through the sending TX port of the media access control layer MAC;

Receive loopback data from each PHY port through the MAC's RX port;

Based on the test case data, the loopback data of each PHY port and the connection status monitoring data of each PHY port, a port test result of each PHY port is obtained.

Specifically, after configuring each PHY port of the PHY chip to be in a loopback state, the connection (Link) status of each PHY port can be obtained to determine whether the connection status of each PHY port is in a connection establishment state (Link up). If it is determined that the connection status of each PHY port is in a connection establishment state, test case data can be sent to each PHY port through the MAC's sending TX port. The test case data is used to test each PHY port. Then, the loopback data of each PHY port can be received through the MAC's receiving RX port. Then, based on the test case data, the loopback data of each PHY port and the connection status monitoring data of each PHY port, the test situation of the PHY port can be analyzed to obtain the port test results of each PHY port.

For example, a PHY chip may include two PHY ports, namely port A and port B. Port A and port B may be configured to be in a loopback state through an MDC interface and an MDIO interface, and then it may be determined whether port A and port B are both in Link up. If it is determined that port A and port B are both in Link up, test case data may be sent to port A and port B through a MAC sending TX port, and then the loopback data of port A and port B may be received through a MAC receiving RX port. Based on the test case data, the loopback data of port A and port B, and the connection status monitoring data of port A and port B, the test conditions of port A and port B may be analyzed, and the port test results of each PHY port may be obtained.

Optionally, Fig. 2 is a schematic diagram of the hardware connection structure of the line speed flow test provided by the present invention. As shown in Fig. 2, the PHY chip can be connected to the CPU through the KR bus of the central processing unit (CPU), and the PHY chip can include a physical medium attachment (PMA) sublayer, a physical medium dependent (PMD) sublayer, a physical coding sublayer (PCS), a serializer (Serializer) and a deserializer (De-Serializer). As shown in Fig. 2, each PHY port of the PHY chip can be configured to be in a loopback state, and then the Lanconf tool can be combined to perform a line speed packet sending and receiving test on each PHY port, and the number of packets sent and received and the number of error packets of each port can be counted in real time.

Therefore, after configuring each PHY port of the PHY chip to be in a loopback state, the test case data is sent to each PHY port through the TX port of the MAC, and the loopback data of each PHY port is received through the RX port of the MAC. This can realize automated testing of each PHY port, and the test process does not require the use of external fixtures, which can improve test efficiency.

Optionally, the present invention provides a test method for a physical layer chip of a switch, wherein the port test result of each PHY port is obtained based on the test case data, the loopback data of each PHY port, and the connection status monitoring data of each PHY port, including:

Based on the test case data and the loopback data of each PHY port, determine the difference information of the number of sent and received packets of each PHY port and the error packet information of each PHY port;

Based on the connection status monitoring data of each PHY port, the difference information of the number of sent and received packets, and the error packet information, it is determined whether each PHY port passes the test, and the port test result of each PHY port is obtained.

Specifically, by comparing the number of packets in the test case data and the number of packets in the loopback data, the difference information in the number of sent and received packets can be determined, and by verifying the loopback data (for example, cyclic redundancy check (CRC)), the error packet information can be obtained, and then based on the connection status monitoring data of each PHY port, the difference information in the number of sent and received packets, and the error packet information, it can be determined whether each PHY port has passed the test, and then the port test results of each PHY port can be obtained.

Optionally, for a certain PHY port, if the connection status monitoring data indicates that the connection status of the PHY port changes to a disconnected state (Link down) during the test, it can be determined that the PHY port has failed the test.

Optionally, for a certain PHY port, if the information about the difference in the number of sent and received packets indicates that the number of packets of the test case data is different from the number of packets of the loopback data, it can be determined that the PHY port has failed the test.

Optionally, for a certain PHY port, if the error packet information indicates that one or more data packets in the loopback data fail to pass the check, it can be determined that the PHY port fails the test.

Optionally, for a certain PHY port, if the following three conditions are met at the same time, it can be determined that the PHY port has failed the test:

The first condition is that the connection status monitoring data indicates that the connection status of the PHY port is in the connection establishment state during the test;

The second condition is that the difference information of the number of sent and received packets indicates that the number of packets of the test case data is the same as the number of packets of the loopback data;

The third condition is that the error packet information indicates that during the process of verifying the loopback data, all data packets in the loopback data have passed the verification.

Therefore, by judging whether each PHY port has passed the test based on the connection status monitoring data, the difference information of the number of sent and received packets, and the error packet information of each PHY port, it is possible to realize automated testing of each PHY port, and the test process does not require the use of external fixtures, which can improve test efficiency.

Optionally, the present invention provides a test method for a physical layer chip of a switch, which, after performing a line-speed flow test on each PHY port to obtain a port test result of each PHY port, further comprises:

When the port test result of the target PHY port indicates that the target PHY port has failed the test, determining a target fault keyword based on the connection status monitoring data, the difference information of the number of sent and received packets, and the error packet information of the target PHY port;

Based on the target fault keyword and the fault table, a target fault diagnosis instruction is acquired, wherein the fault table is used to characterize a mapping relationship between the fault keyword and the fault diagnosis instruction, and the fault diagnosis instruction is used to assist in diagnosing the PHY port;

Obtaining fault diagnosis information of the target PHY port by executing the target fault diagnosis instruction;

The target PHY port is any PHY port of the PHY chip.

Specifically, in order to obtain the cause of the failure of the PHY port, the port test results of each PHY port can be analyzed. If the port test result of the target PHY port of the PHY chip indicates that the target PHY port has failed the test, fault keywords can be extracted based on the connection status monitoring data, the difference information in the number of sent and received packets, and the error packet information to obtain the target fault keyword used to characterize the fault condition of the target PHY port. Then, based on the target fault keyword, a query can be made in the fault table to obtain a target fault diagnosis instruction that matches the target fault keyword. Then, the target fault diagnosis instruction can be executed to diagnose the target PHY port, and the fault diagnosis information of the target PHY port can be obtained.

It is understandable that the fault table can characterize the mapping relationship between fault keywords and fault diagnosis instructions. Based on the target fault keyword, by querying in the fault table, the target fault diagnosis instruction matching the target fault keyword can be obtained. By analyzing historical test data, keywords can be extracted for various fault scenarios of the PHY port to obtain fault keywords, and the fault keywords can characterize a class of fault scenarios of the PHY port. For various fault scenarios of the PHY port, various fault diagnosis instructions can be pre-configured, and a fault diagnosis instruction can perform fault diagnosis for a class of fault scenarios to assist in diagnosing the PHY port.

For example, the connection status monitoring data indicates that during the test, the connection status of the target PHY port changes from Link up to Link down. The target fault keyword may include "abnormal connection status". Based on this keyword, a query can be made in the fault table to obtain a target fault diagnosis instruction that matches the keyword ("abnormal connection status").

For example, for the target PHY port, if the difference information on the number of sent and received packets indicates that the number of packets in the test case data is different from the number of packets in the loopback data, the target fault keyword may include "inconsistent number of sent and received packets", and then based on this keyword, the fault table may be queried to obtain a target fault diagnosis instruction that matches the keyword ("inconsistent number of sent and received packets").

For example, for the target PHY port, if the error packet information indicates that one or more data packets in the loopback data failed to pass the check, the target fault keyword may include "CRC error occurred", and then based on this keyword, the fault table can be queried to obtain the target fault diagnosis instruction that matches the keyword ("CRC error occurred").

For example, the target fault keyword may include "CRC error occurs", and the target fault diagnosis instruction matching the keyword may be a fault diagnosis for a CRC error scenario. The target fault diagnosis instruction may obtain an eye diagram, a bathtub curve, CTLE parameters, and a decision feedback equalizer (DFE) parameter for the target PHY port, and then based on a preset range value, determine whether the eye diagram, bathtub curve, continuous-time linear equalizer (CTLE) parameter, and DFE parameter are within a preset range, and obtain fault diagnosis information of the target PHY port.

Therefore, when the PHY port fails the test, the target fault diagnosis instruction can be obtained by querying the fault table. The fault diagnosis information can be obtained by running the target fault diagnosis instruction, which can realize automatic diagnosis of the PHY port fault. The test process does not require the use of external fixtures, which can improve the test efficiency.

Optionally, the present invention provides a test method for a switch physical layer chip, which, after acquiring the fault diagnosis information of the target PHY port, further comprises:

Determine the fault reporting information of the target PHY port based on the connection status monitoring data of the target PHY port, the difference information of the number of sent and received packets, the error packet information and the fault diagnosis information;

Send the fault reporting information of the target PHY port to the server.

Specifically, after obtaining the fault diagnosis information of the target PHY port, the information of the target PHY port can be collected, and the connection status monitoring data, the difference information of the number of sent and received packets, the error packet information and the fault diagnosis information can be packaged into the fault reporting information, and then the fault reporting information of the target PHY port can be sent to the server.

Therefore, by sending the fault reporting information of the PHY port to the server, the server can collect and comprehensively analyze the fault information of each PHY chip.

Optionally, the present invention provides a method for testing a physical layer chip of a switch, further comprising:

Polling multiple registers of the PHY chip through the MDC interface and the MDIO interface to obtain storage values of the multiple registers, wherein the multiple registers include an interrupt register, a control register, and a status register;

Based on the reference value of each register and the storage value of each register, the operation status information of the PHY chip is determined, and the operation status information is used to indicate whether the PHY chip fails.

Specifically, in order to monitor the operating status of the PHY chip in real time, multiple registers of the PHY chip can be polled through the MDC interface and the MDIO interface to obtain the storage values of the multiple registers, and then the reference value of each register can be compared with the storage value of each register to determine the operating status information of the PHY chip.

It is understandable that in the related art, the detection of the operating status of the PHY chip is generally performed by sending a code stream during the link idle phase, which has low real-time performance. The present invention polls multiple registers of the PHY chip through the MDC interface and the MDIO interface to achieve real-time monitoring of the operating status of the PHY chip.

For example, a storage value of an interrupt register (eg, a serdes interrupt register) and a reference value of the interrupt register may be compared. If it is determined that the storage value of the interrupt register and the reference value of the interrupt register are different, it may be determined that a PHY chip fails.

For example, the storage value of the control register and the reference value of the control register may be compared. If it is determined that the storage value of the control register and the reference value of the control register are different, it may be determined that the PHY chip fails.

For example, the storage value of the status register and the reference value of the status register may be compared. If it is determined that the storage value of the status register and the reference value of the status register are different, it may be determined that the PHY chip fails.

Therefore, by polling multiple registers of the PHY chip through the MDC interface and the MDIO interface, the operating status of the PHY chip can be monitored in real time, and the test process does not require the use of external fixtures, which can improve the test efficiency.

Optionally, the present invention provides a method for testing a physical layer chip of a switch, which, after determining the operating status information of the PHY chip, further comprises:

In a case where the operating status information indicates that a fault occurs in the PHY chip, the storage value of each register is configured as a reference value of each register.

Specifically, after determining the operating status information of the PHY chip, it can be determined whether the PHY chip fails. If it is determined that the PHY chip fails, the PHY chip can be reset by configuring the storage value of each register as the reference value of each register to restore the PHY chip to a normal operating state.

Optionally, a PHY chip debug tool can be run in the background of the switch to enable a thread to poll the PHY chip Serdes interrupt register, control register or status register through the MDC interface and the MDIO interface. If an abnormality occurs, it automatically intervenes and rewrites the register value for reconfiguration.

Therefore, in the event of a failure in the PHY chip, automatic intervention can be achieved by configuring the storage value of each register as the reference value of each register, which has high real-time performance and reduces the impact of the failure on the service.

The switch physical layer chip testing method provided by the present invention can configure each PHY port of the PHY chip to be in a loopback state through an MDC interface and an MDIO interface, and then a line speed flow test can be performed on each PHY port. During the test, the test case data sent to each PHY port of the PHY chip can be looped back through the PHY chip, and then the loopback data of each PHY port can be analyzed, and the port test result of each PHY port can be obtained. The port test result can indicate whether the PHY port passes the test. No external fixture is required in the test process, and the test efficiency can be improved.

The following is an optional example of the present invention, but is not intended to limit the present invention.

CPU 10GBASE-KR uses a PHY chip to make a QSFP port, configures the port as 4x10G, and records it as port1, port2, port3, and port4. Performing automated testing at high temperature (about 45 degrees Celsius) may include the following steps 401 to 403:

Step 401, configure all four ports of the PHY chip as internal loopback.

Step 402: After detecting that the port can be normally linked up after the loopback is configured, the Lanconf tool is called to perform a transmit and receive test, and the port count is counted in real time.

Optionally, during the test, the real-time detection program running in the background finds through polling that the value of the LIVELNKSTAT1_00x20028 register is abnormal, with a value of 0xFF0F, compares it with the normal value, and writes it back to 0xFF87.

Step 403, according to the statistical information of step 402, it is determined that a CRC error occurs in port 1 during the test process. The test program uses the log keyword "traffic crc occurred" to look up the fault table to find the fault diagnosis instruction "TRAFFIC_CRC". According to the fault diagnosis instruction, the MDC interface and the MDIO interface dump registers (dumping registers means exporting and transferring register data into files or static forms) to obtain the eye diagram of Port 1, determine that the eye height is small, analyze the bathtub curve to find that the deterministic jitter is large, and then analyze the port CTLE or DFE and other training parameters to determine that the difference is large compared with the normal port, and then determine that the CTLE initial value is unreasonable, and return the result and collected information to the server.

The present invention configures an internal loopback for the PHY chip and combines the Lanconf tool to realize automatic testing of the PHY port without relying on other tooling and fixtures, and the test program can automatically collect information and automatically analyze the cause of test failure by checking the fault table. Compared with the traditional test method, it can reduce tooling costs and manpower, and avoid environmental damage due to lack of timely analysis. By polling the PHY chip register in real time through the background program, the operating status of the PHY chip can be detected in real time, and it can automatically intervene without users noticing and affecting normal business.

The switch physical layer chip testing device provided by the present invention is described below. The switch physical layer chip testing device described below and the switch physical layer chip testing method described above can refer to each other.

FIG3 is a schematic diagram of the structure of a test device for a switch physical layer chip provided by the present invention. As shown in FIG3 , the device includes: a first configuration module 301 and a test module 302, wherein:

The first configuration module 301 is used to configure each PHY port of the physical layer PHY chip to a loopback state through a management data clock MDC interface and a management data input and output MDIO interface;

The testing module 302 is used to obtain a port test result of each PHY port by performing a line rate flow test on each PHY port, wherein the port test result is used to indicate whether the PHY port passes the test.

The switch physical layer chip test device provided by the present invention can configure each PHY port of the PHY chip to be in a loopback state through an MDC interface and an MDIO interface, and then can perform a line speed flow test on each PHY port. During the test, the test case data sent to each PHY port of the PHY chip can be looped back through the PHY chip, and then the loopback data of each PHY port can be analyzed, and the port test result of each PHY port can be obtained. The port test result can indicate whether the PHY port passes the test. The test process does not need to use an external fixture, which can improve the test efficiency.

Optionally, the test module is specifically used for:

Get the connection status of each PHY port;

If it is determined that the connection status of each PHY port is a connection establishment status, the test case data is sent to each PHY port through the sending TX port of the media access control layer MAC;

Receive loopback data from each PHY port through the MAC's RX port;

Based on the test case data, the loopback data of each PHY port and the connection status monitoring data of each PHY port, a port test result of each PHY port is obtained.

Optionally, the test module is specifically used for:

Based on the test case data and the loopback data of each PHY port, determine the difference information of the number of sent and received packets of each PHY port and the error packet information of each PHY port;

Based on the connection status monitoring data of each PHY port, the difference information of the number of sent and received packets, and the error packet information, it is determined whether each PHY port passes the test, and the port test result of each PHY port is obtained.

Optionally, the device further includes a fault diagnosis module, and after performing a line rate flow test on each PHY port to obtain a port test result of each PHY port, the fault diagnosis module is used to:

When the port test result of the target PHY port indicates that the target PHY port has failed the test, determining a target fault keyword based on the connection status monitoring data, the difference information of the number of sent and received packets, and the error packet information of the target PHY port;

Based on the target fault keyword and the fault table, a target fault diagnosis instruction is acquired, wherein the fault table is used to characterize a mapping relationship between the fault keyword and the fault diagnosis instruction, and the fault diagnosis instruction is used to assist in diagnosing the PHY port;

Obtaining fault diagnosis information of the target PHY port by executing the target fault diagnosis instruction;

The target PHY port is any PHY port of the PHY chip.

Optionally, the device further includes a sending module, and after acquiring the fault diagnosis information of the target PHY port, the sending module is used to:

Determine the fault reporting information of the target PHY port based on the connection status monitoring data of the target PHY port, the difference information of the number of sent and received packets, the error packet information and the fault diagnosis information;

Send the fault reporting information of the target PHY port to the server.

Optionally, the device further comprises an operation status monitoring module, wherein the operation status monitoring module is used to:

Polling multiple registers of the PHY chip through the MDC interface and the MDIO interface to obtain storage values of the multiple registers, wherein the multiple registers include an interrupt register, a control register, and a status register;

Based on the reference value of each register and the storage value of each register, the operation status information of the PHY chip is determined, and the operation status information is used to indicate whether the PHY chip fails.

Optionally, the device further includes a second configuration module, and after determining the operating status information of the PHY chip, the second configuration module is used to:

In a case where the operating status information indicates that a fault occurs in the PHY chip, the storage value of each register is configured as a reference value of each register.

The switch physical layer chip test device provided by the present invention can configure each PHY port of the PHY chip to be in a loopback state through an MDC interface and an MDIO interface, and then can perform a line speed flow test on each PHY port. During the test, the test case data sent to each PHY port of the PHY chip can be looped back through the PHY chip, and then the loopback data of each PHY port can be analyzed, and the port test result of each PHY port can be obtained. The port test result can indicate whether the PHY port passes the test. The test process does not need to use an external fixture, which can improve the test efficiency.

FIG4 is a schematic diagram of the structure of an electronic device provided by the present invention. As shown in FIG4 , the electronic device may include: a processor 410, a communications interface 420, a memory 430, and a communication bus 440, wherein the processor 410, the communications interface 420, and the memory 430 communicate with each other through the communication bus 440. The processor 410 may call the logic instructions in the memory 430 to execute the test method of the physical layer chip of the switch, for example, the method includes:

By managing the data clock MDC interface and the data input and output MDIO interface, each PHY port of the physical layer PHY chip is configured to be in a loopback state;

By performing a line-speed flow test on each PHY port, a port test result of each PHY port is obtained, and the port test result is used to indicate whether the PHY port passes the test.

In addition, the logic instructions in the above-mentioned memory 430 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

On the other hand, the present invention further provides a computer program product, the computer program product includes a computer program, the computer program can be stored on a non-transitory computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the switch physical layer chip test method provided by the above methods, for example, the method includes:

By managing the data clock MDC interface and the data input and output MDIO interface, each PHY port of the physical layer PHY chip is configured to be in a loopback state;

By performing a line-speed flow test on each PHY port, a port test result of each PHY port is obtained, and the port test result is used to indicate whether the PHY port passes the test.

In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the method for testing the physical layer chip of the switch provided by the above methods is implemented, for example, the method includes:

By managing the data clock MDC interface and the data input and output MDIO interface, each PHY port of the physical layer PHY chip is configured to be in a loopback state;

By performing a line-speed flow test on each PHY port, a port test result of each PHY port is obtained, and the port test result is used to indicate whether the PHY port passes the test.

The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM/RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (9)

1. A method for testing a physical layer chip of a switch, comprising:

Through the MDC interface of the management data clock and the MDIO interface of the management data input and output, each PHY port of the PHY chip of the physical layer is configured to be in a loop-back state;

Acquiring port test results of each PHY port by performing a line speed flow test on each PHY port, wherein the port test results are used for indicating whether the PHY port passes the test or not;

The obtaining the port test result of each PHY port by performing the line speed traffic test on each PHY port includes: acquiring the connection state of each PHY port; if the connection state of each PHY port is determined to be the connection establishment state, transmitting test case data to each PHY port through a transmission TX port of a Media Access Control (MAC); receiving loop-back data of each PHY port through a receiving RX port of the MAC; and acquiring a port test result of each PHY port based on the test case data, the loopback data of each PHY port and the connection state monitoring data of each PHY port.

2. The method for testing the physical layer chip of the switch according to claim 1, wherein the obtaining the port test result of each PHY port based on the test case data, the loopback data of each PHY port, and the connection state monitoring data of each PHY port includes:

Determining the difference information of the number of the receiving and transmitting packets of each PHY port and the error packet information of each PHY port based on the test case data and the loopback data of each PHY port;

And judging whether each PHY port passes the test or not based on the connection state monitoring data of each PHY port, the difference information of the number of the receiving and transmitting packets and the error packet information, and obtaining the port test result of each PHY port.

3. The method for testing a physical layer chip of a switch according to any one of claims 1 to 2, further comprising, after the obtaining a port test result of each PHY port by performing a line speed traffic test on each PHY port:

determining a target fault keyword based on connection state monitoring data, receiving and transmitting packet quantity difference information and error packet information of a target PHY port under the condition that a port test result of the target PHY port indicates that the target PHY port fails the test;

Acquiring a target fault diagnosis instruction based on the target fault keyword and a fault table, wherein the fault table is used for representing a mapping relation between the fault keyword and the fault diagnosis instruction, and the fault diagnosis instruction is used for assisting in diagnosing the PHY port;

Acquiring fault diagnosis information of the target PHY port by executing the target fault diagnosis instruction;

the target PHY port is any one PHY port of the PHY chip.

4. The method for testing a physical layer chip of a switch according to claim 3, further comprising, after the obtaining the failure diagnosis information of the target PHY port:

Determining fault reporting information of the target PHY port based on connection state monitoring data of the target PHY port, receiving and transmitting packet quantity difference information, error packet information and fault diagnosis information;

and sending fault report information of the target PHY port to a server.

5. The method for testing a physical layer chip of a switch according to any one of claims 1-2, further comprising:

polling a plurality of registers of the PHY chip through an MDC interface and an MDIO interface to acquire storage values of the registers, wherein the registers comprise an interrupt register, a control register and a status register;

and determining the operation state information of the PHY chip based on the reference value of each register and the storage value of each register, wherein the operation state information is used for representing whether the PHY chip has faults or not.

6. The method for testing a physical layer chip of a switch according to claim 5, further comprising, after said determining the operation state information of the PHY chip:

and under the condition that the running state information represents that the PHY chip fails, configuring the storage value of each register as the reference value of each register.

7. A test device for a physical layer chip of a switch, comprising:

the first configuration module is used for configuring each PHY port of the PHY chip of the physical layer into a loop-back state through the MDC interface of the management data clock and the MDIO interface of the management data input and output;

The testing module is used for obtaining the port testing result of each PHY port by carrying out the line speed flow test on each PHY port, and the port testing result is used for indicating whether the PHY port passes the test or not; the obtaining the port test result of each PHY port by performing the line speed traffic test on each PHY port includes: acquiring the connection state of each PHY port; if the connection state of each PHY port is determined to be the connection establishment state, transmitting test case data to each PHY port through a transmission TX port of a Media Access Control (MAC); receiving loop-back data of each PHY port through a receiving RX port of the MAC; and acquiring a port test result of each PHY port based on the test case data, the loopback data of each PHY port and the connection state monitoring data of each PHY port.

8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of testing the physical layer chip of the switch of any one of claims 1 to 6 when the program is executed by the processor.

9. A non-transitory computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when executed by a processor, implements a method of testing a physical layer chip of a switch according to any one of claims 1 to 6.