CN115631728B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN115631728B CN115631728B CN202211351269.5A CN202211351269A CN115631728B CN 115631728 B CN115631728 B CN 115631728B CN 202211351269 A CN202211351269 A CN 202211351269A CN 115631728 B CN115631728 B CN 115631728B
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- 238000010586 diagram Methods 0.000 description 27
- 230000000694 effects Effects 0.000 description 12
- 230000002093 peripheral effect Effects 0.000 description 9
- 230000002349 favourable effect Effects 0.000 description 8
- 230000008859 change Effects 0.000 description 4
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- 230000000087 stabilizing effect Effects 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 3
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the application provides a display panel and a display device, wherein the display panel comprises a first type pixel circuit, a first electrode of a first transistor is electrically connected with a second electrode of a driving transistor in the first type pixel circuit, a first electrode of a second transistor is electrically connected with a grid electrode of the driving transistor, a first node is arranged between the second electrode of the first transistor and the second electrode of the second transistor, a first end of a first sub-gating module is electrically connected with the grid electrode of the driving transistor, a second end of the first sub-gating module is electrically connected with a first end of a second sub-gating module, a second end of the second sub-gating module is electrically connected with the first node, and an opening period of the first sub-gating module is positioned before an opening period of the second sub-gating module. The application can avoid the first node from influencing the grid potential of the driving transistor through the first sub-gating module and the second sub-gating module, is beneficial to reducing the potential difference between the first node and the grid of the driving transistor and improves the problem of electric leakage of the first node to the grid of the driving transistor.
Description
[ Field of technology ]
The present application relates to the field of display technologies, and in particular, to a display panel and a display device.
[ Background Art ]
An organic light-emitting diode (OLED) display panel has advantages of low power consumption, self-luminescence, wide viewing angle, wide temperature characteristics, fast response speed, and the like, and has wide application in the market. Among them, the pixel circuit for controlling the light emission of the light emitting device is a core technical content of the OLED display panel, and has important research significance.
A driving transistor is generally included in the pixel circuit, and the driving transistor is capable of generating a driving current for driving the light emitting device according to a voltage of a gate thereof. However, in the prior art, the gate voltage of the driving transistor has a problem of leakage, which results in unstable gate voltage of the driving transistor, and affects the light emitting brightness of the light emitting device, thereby affecting the display effect.
[ MEANS FOR SOLVING PROBLEMS ]
In view of the above, the embodiments of the present application provide a display panel and a display device to solve the above-mentioned problems.
In a first aspect, an embodiment of the present application provides a display panel, where the display panel includes a plurality of pixel circuits and a plurality of light emitting modules, the pixel circuits include a driving transistor, a first transistor and a second transistor, the driving transistor is used for providing a light emitting driving current for the light emitting module, a first electrode of the first transistor is electrically connected with a second electrode of the driving transistor, a first node is included between the second electrode of the first transistor and the second electrode of the second transistor, the plurality of pixel circuits include a first type pixel circuit, the first type pixel circuit includes a first gate module, the first gate module includes a first sub-gate module and a second sub-gate module, a first end of the first sub-gate module is electrically connected with the gate electrode of the driving transistor, a second end of the second sub-gate module is electrically connected with the second node, the first gate module is used for adjusting a potential of the first node, and the first sub-gate module is located before a second sub-gate-on period.
In one implementation of the first aspect, the first sub-gate module includes a third transistor having a first pole electrically connected to the gate of the driving transistor and a second pole electrically connected to the second node, and the second sub-gate module includes a fourth transistor having a first pole electrically connected to the first node and a second pole electrically connected to the second node.
In one implementation manner of the first aspect, the first type of pixel circuit includes a first capacitor, one polar plate of the first capacitor is electrically connected with the second node, and the other polar plate is electrically connected with the fixed potential signal line.
In one implementation manner of the first aspect, the fixed potential signal line is electrically connected to a first power supply voltage signal line, and the first power supply voltage signal line is electrically connected to the light emitting module.
In one implementation manner of the first aspect, the first-type pixel circuit further includes a data voltage writing module, an input end of the data voltage writing module is electrically connected with the data signal line, an output end of the data voltage writing module is electrically connected with the first pole of the driving transistor, the working process of the first-type pixel circuit includes a data writing stage, the data voltage writing module, the first transistor and the second transistor are turned on in the data writing stage, and the first gating module is turned on after the data writing stage.
In one implementation manner of the first aspect, the operation of the first type of pixel circuit further includes a light emitting phase performed after the data writing phase, and the first strobe module is turned on in the light emitting phase.
In an implementation manner of the first aspect, the operation of the first type of pixel circuit further includes a conditioning phase and a light emitting phase sequentially performed after the data writing phase, and the first gating module is turned on during the conditioning phase.
In one implementation manner of the first aspect, the data voltage writing module includes a fifth transistor, a first pole of the fifth transistor is electrically connected to the data signal line, a second pole of the fifth transistor is electrically connected to the first pole of the driving transistor, a gate of the fifth transistor is electrically connected to the first scan line, a gate of the first transistor and a gate of the second transistor are electrically connected to the first scan line, and signals transmitted by the first scan line control the switching states of the first transistor, the second transistor and the fifth transistor to be the same.
In one implementation manner of the first aspect, a gate of the third transistor is electrically connected to the second scan line, and a gate of the fourth transistor is electrically connected to the third scan line.
In one implementation manner of the first aspect, the first type pixel circuit further includes a power supply voltage writing module and a light emitting control module, wherein an input end of the power supply voltage writing module is electrically connected with the second power supply voltage signal line, an output end of the power supply voltage writing module is electrically connected with a first electrode of the driving transistor, a control end of the power supply voltage writing module is electrically connected with the light emitting control signal line, an input end of the light emitting control module is electrically connected with a second electrode of the driving transistor, an output end of the light emitting control module is electrically connected with the first electrode of the light emitting module, a control end of the light emitting control module is electrically connected with the light emitting control signal line, and a third scanning line is electrically connected with the light emitting control signal line, and signals transmitted by the light emitting control signal line control the switch states of the power supply voltage writing module, the light emitting control module and the fourth transistor are identical.
In one implementation manner of the first aspect, the display panel includes a plurality of rows of first-type pixel circuits, the second scan line electrically connected to the i-th row of first-type pixel circuits is electrically connected to the first scan line electrically connected to the i+1-th row of first-type pixel circuits, and the third scan line electrically connected to the i-th row of first-type pixel circuits is electrically connected to the first scan line electrically connected to the i+2-th row of first-type pixel circuits, where i is greater than or equal to 1.
In one implementation manner of the first aspect, a duration of opening the first sub-gate module is not less than a duration of opening the data voltage writing module, and a duration of opening the second sub-gate module is not less than a duration of opening the data voltage writing module.
In an implementation manner of the first aspect, a duration that the first sub-gating module is turned on is not less than a duration that the second sub-gating module is turned on.
In one implementation manner of the first aspect, the plurality of pixel circuits includes a second type of pixel circuit, the second type of pixel circuit includes a second gating module, a first end of the second gating module is electrically connected with the first node, and a second end of the second gating module is electrically connected with a second node in the first type of pixel circuit, wherein a switching state of the second gating module is the same as a switching state of a second sub-gating module in the first type of pixel circuit.
In a second aspect, an embodiment of the present application provides a display device including the display panel provided in the first aspect.
In the embodiment of the application, the first gating module is arranged between the first node and the grid electrode of the driving transistor, and the potential of the first node is regulated by utilizing the potential of the grid electrode of the driving transistor, so that the potential difference between the first node and the grid electrode of the driving transistor can be reduced, thereby being beneficial to improving the problem of electric leakage of the first node to the grid electrode of the driving transistor, stabilizing the potential of the grid electrode of the driving transistor, further being beneficial to avoiding larger change of brightness of a display frame picture and improving the display effect of the display panel.
In addition, in the first gating module, the period for setting the first sub-gating module to be started is located before the period for setting the second sub-gating module to be started, the grid potential of the driving transistor can be written into the second node through the first sub-gating module, then the potential of the first node is written into the first node through the second sub-gating module to be adjusted, the potential of the first node can be prevented from influencing the grid potential of the driving transistor through the first gating module, and therefore stability and accuracy of the grid potential of the driving transistor are further guaranteed, and the display effect of the display panel is further improved.
[ Description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a first type of pixel circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a first type of pixel circuit shown in FIG. 2;
FIG. 4 is a timing diagram of the first type of pixel circuit shown in FIG. 3;
FIG. 5 is a schematic diagram of a first type of pixel circuit according to an embodiment of the present application;
FIG. 6 is a timing diagram of a first type of pixel circuit shown in FIG. 3;
FIG. 7 is a timing diagram of a first type of pixel circuit shown in FIG. 3;
FIG. 8 is a timing diagram of a first type of pixel circuit shown in FIG. 3;
FIG. 9 is a timing diagram of a first type of pixel circuit shown in FIG. 3;
FIG. 10 is a schematic diagram of a first type of pixel circuit according to an embodiment of the present application;
FIG. 11 is a schematic diagram illustrating a connection between adjacent three rows of the first type pixel circuits in FIG. 1;
FIG. 12 is a schematic view of a display panel according to another embodiment of the present application;
fig. 13 is a schematic diagram illustrating connection between a second type pixel circuit and a first type pixel circuit according to an embodiment of the present application;
fig. 14 is a schematic diagram of a display device according to an embodiment of the application.
[ Detailed description ] of the invention
For a better understanding of the technical solution of the present application, the following detailed description of the embodiments of the present application refers to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely an association relationship describing the associated object, and means that there may be three relationships, e.g., a and/or B, and that there may be three cases where a exists alone, while a and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
In the description of the present specification, it is to be understood that the terms "substantially," "approximately," "about," "approximately," "substantially," and the like as used in the claims and embodiments of the application are intended to be inclusive of a reasonable process operation or tolerance and not an exact value.
It should be understood that although the terms first, second, etc. may be used in embodiments of the present application to describe transistors, nodes, directions, etc., these transistors, nodes, directions, etc. should not be limited to these terms. These terms are only used to distinguish transistors, nodes, directions, etc. from one another. For example, a first node may also be referred to as a second node, and similarly, a second node may also be referred to as a first node, without departing from the scope of embodiments of the present application.
The applicant has provided a solution to the problems existing in the prior art by intensive studies.
Fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application, fig. 2 is a schematic diagram of a first type pixel circuit according to an embodiment of the present application, and fig. 3 is a schematic diagram of the first type pixel circuit shown in fig. 2.
The embodiment of the application provides a display panel 01, as shown in fig. 1, the display panel 01 includes a plurality of pixel circuits 11 and a light emitting module 12, and the pixel circuits 11 are electrically connected with the light emitting module 12 and are used for driving the light emitting module 12 to emit light. In the display panel 01, the pixel circuits 11 may be arrayed along a first direction X, which may be a row direction of the display panel 01, and a second direction Y, which may be a column direction of the display panel 01.
As shown in fig. 2, the pixel circuit 11 includes a driving transistor Td for providing a light emitting driving current to the light emitting module 12, a first transistor T1 and a second transistor T2, a first electrode of the first transistor T1 is electrically connected to a second electrode of the driving transistor Td, a first electrode of the second transistor T2 is electrically connected to a gate electrode of the driving transistor Td, and a first node N1 is included between the second electrode of the first transistor T1 and the second electrode of the second transistor T2. The first transistor T1 and the second transistor T2 are used to compensate the threshold voltage of the driving transistor Td to the gate of the driving transistor Td.
Specifically, as shown in fig. 2 and 3, the second pole of the first transistor T1 is electrically connected to the second pole of the second transistor T2 at the first node N1. The grid electrode of the first transistor T1 and the grid electrode of the second transistor T2 are electrically connected with the first scanning line S1, and the signal transmitted by the first scanning line S1 controls the switching states of the first transistor T1 and the second transistor T2 to be the same.
When the first scan line S1 transmits an active signal to control the first transistor T1 and the second transistor T2 to be turned on, the threshold voltage of the driving transistor Td may be compensated to the gate electrode of the driving transistor Td through the turned-on first transistor T1 and second transistor T2.
Referring to fig. 1 and 2, the plurality of pixel circuits 11 includes a first type of pixel circuit 111, the first type of pixel circuit 111 includes the driving transistor Td, the first transistor T1 and the second transistor T2 included in the pixel circuit 11, and the first type of pixel circuit 111 further includes the first gate module 20, i.e. the pixel circuit 11 including the first gate module 20 may be the first type of pixel circuit 111.
The first gating module 20 includes a first sub-gating module 21 and a second sub-gating module 22, a first end of the first sub-gating module 21 is electrically connected to the gate of the driving transistor Td, a second end of the first sub-gating module is electrically connected to the second node N2, a first end of the second sub-gating module 22 is electrically connected to the second node N2, and a second end of the second sub-gating module 22 is electrically connected to the first node N1, and the first gating module 20 is used for adjusting the potential of the first node N1.
Specifically, when the first gate module 20 is turned on, the first node N1 is turned on with the gate of the driving transistor Td, and the first gate module 20 can adjust the potential of the first node N1 by using the gate potential of the driving transistor Td, so as to reduce the potential difference between the first node N1 and the gate of the driving transistor Td. The first terminal of the first sub-gate module 21 and the gate of the driving transistor Td may be electrically connected at a third node N3, and the third node N3 may have the same potential as the gate of the driving transistor Td.
Wherein, in the first gating module 20, the period in which the first sub-gating module 21 is turned on is located before the period in which the second sub-gating module 22 is turned on.
That is, the periods in which the first sub-gate module 21 and the second sub-gate module 22 are turned on do not overlap, and the first sub-gate module 21 is turned on before and the second sub-gate module 22 is turned on after.
It should be noted that, in the embodiment of the present application, the periods when the first sub-gate module 21 and the second sub-gate module 22 are turned on do not overlap, which includes the case that the time when the first sub-gate module 21 is turned off is the same as the time when the second sub-gate module 22 is turned on.
It will be appreciated that due to the operating characteristics of the transistor, the transistor will experience a leakage current when a potential difference occurs between the first and second poles of the transistor, although the transistor is in an off state, and that the greater the potential difference between the first and second poles of the transistor, the more pronounced the leakage current of the transistor. The first and second poles of the transistor may be the source and drain of the transistor.
In the prior art, after the first transistor T1 and the second transistor T2 grab the threshold voltage of the driving transistor Td to the gate of the driving transistor Td, the potential of the first node N1 is generally greater than the gate potential of the driving transistor Td due to the coupling effect of the transmission signal of the first scan line S1, i.e. the second electrode potential of the second transistor T2 is greater than the first electrode potential thereof. Although the first transistor T1 and the second transistor T2 are both turned off at this time, the first node N1 still leaks current to the gate of the driving transistor Td, which results in unstable gate potential of the driving transistor Td when generating the light emitting driving current, and thus results in unstable light emitting driving current generated according to the gate potential thereof, which affects the brightness of the light emitting module 12. Especially, when the display panel 01 is displayed at a low frequency, flickering of the screen is very remarkable.
In the embodiment of the application, the first gating module 20 is arranged between the first node N1 and the gate of the driving transistor Td, and the potential of the first node N1 is adjusted by using the gate potential of the driving transistor Td, so that the potential difference between the first node N1 and the gate of the driving transistor Td can be reduced, thereby being beneficial to improving the problem of leakage of the first node N1 to the gate of the driving transistor Td, stabilizing the gate potential of the driving transistor Td, further being beneficial to avoiding larger change of brightness of a display frame picture, and improving the display effect of the display panel 01.
In addition, in the first gating module 20, the period when the first sub-gating module 21 is turned on is set before the period when the second sub-gating module 22 is turned on, the gate potential of the driving transistor Td may be written into the second node N2 through the first sub-gating module 21, and then written into the first node N1 through the second sub-gating module 22 to adjust the potential of the first node N1, so that the potential of the first node N1 may be prevented from affecting the gate potential of the driving transistor Td through the first gating module 20, thereby being beneficial to further ensuring stability and accuracy of the gate potential of the driving transistor Td and further improving the display effect of the display panel 01.
Fig. 4 is a timing diagram of the first type of pixel circuit shown in fig. 3.
In one embodiment of the present application, as shown in fig. 3, the first sub-gate module 21 includes a third transistor T3, a first pole of the third transistor T3 is electrically connected to the gate of the driving transistor Td, and a second pole is electrically connected to the second node N2. The second sub-gate module 22 includes a fourth transistor T4, a first pole of the fourth transistor T4 is electrically connected to the first node N1, and a second pole is electrically connected to the second node N2.
That is, each of the first and second sub-gate modules 21 and 22 may include only one transistor to simplify the structure of the first type pixel circuit 111.
Further, referring to fig. 3 and 4, the gate of the third transistor T3 is electrically connected to the second scan line S2, and the gate of the fourth transistor T4 is electrically connected to the third scan line S3. The period during which the second scan line S2 transmits the active signal (e.g., low level) to control the third transistor T3 to be turned on is before the period during which the third scan line S3 transmits the active signal (e.g., low level) to control the fourth transistor T4 to be turned on.
Fig. 5 is a schematic diagram of still another first type of pixel circuit according to an embodiment of the present application.
The present inventors considered that after the gate potential of the driving transistor Td is written into the second node N2, the potential of the second node N2 may be generally smaller than the gate potential of the driving transistor Td as time passes, and in the process of turning on the second node N2 and the first node N1 to adjust the potential of the first node N1, a situation may still occur in which there is a large potential difference between the first node N1 and the gate potential of the driving transistor Td, and the first node N1 may still leak to the gate of the driving transistor Td, affecting the stability of the gate potential of the driving transistor Td. Accordingly, the present inventors have provided a scheme that can further reduce the potential difference between the first node N1 and the gate potential of the driving transistor Td without affecting the gate potential of the driving transistor Td through the first gate module 20.
In one embodiment of the present application, as shown in fig. 5, the first type pixel circuit 111 includes a first capacitor C1, one plate of the first capacitor C1 is electrically connected to the second node N2, and the other plate is electrically connected to the fixed potential signal line CL 1.
Alternatively, as shown in fig. 5, the fixed potential signal line CL1 is electrically connected to the first power supply voltage signal line PVEE, and the first power supply voltage signal line PVEE is electrically connected to the light emitting module 12. Of course, in some other embodiments, the fixed potential signal line CL1 may also be electrically connected to the second power supply voltage signal line PVDD.
In the embodiment of the application, the first capacitor C1 can effectively stabilize the potential of the second node N2, which is favorable for completely storing the gate potential of the driving transistor Td in the second node N2, i.e., is favorable for realizing that the potential of the second node N2 and the gate potential of the driving transistor Td tend to be the same, so that after the second node N2 is conducted with the first node N1, the potential between the first node N1 and the gate of the driving transistor Td is favorable for further reducing, thereby ensuring that the gate potential of the driving transistor Td remains stable, and further being favorable for improving the display effect of the display panel 01.
With continued reference to fig. 2 and 3, in one embodiment of the present application, the first type pixel circuit 111 further includes a data voltage writing module 30, an input terminal of the data voltage writing module 30 is electrically connected to the data signal line DL1, an output terminal of the data voltage writing module 30 is electrically connected to the first electrode of the driving transistor Td, and the data voltage writing module 30 is configured to transmit the data voltage Vdata transmitted by the data signal line DL1 to the first electrode of the driving transistor Td.
The first type of pixel circuit 111 includes a data writing stage E1, and in the data writing stage E1, the data voltage writing module 30 and the first transistor T1 and the second transistor T2 are turned on.
The first gating module 20 is turned on after the data writing phase E1.
Specifically, as shown in fig. 3, the control terminal of the data voltage writing module 30 is electrically connected to the first scan line S1, and the signal transmitted by the first scan line S1 controls the switching states of the data voltage writing module 30, the first transistor T1, and the second transistor T2 to be the same.
Further, the data voltage writing module 30 includes a fifth transistor T5, a first electrode of the fifth transistor T5 is electrically connected to the data signal line DL1, a second electrode of the fifth transistor T5 is electrically connected to the first electrode of the driving transistor Td, and a gate electrode of the fifth transistor T5 is electrically connected to the first scan line S1. The gates of the first transistor T1 and the second transistor T2 are electrically connected to the first scan line S1, and the signals transmitted by the first scan line S1 control the switching states of the first transistor T1, the second transistor T2 and the fifth transistor T5 to be the same.
In the data writing stage E1, the fifth transistor T5, the first transistor T1 and the second transistor T2 are turned on, the data voltage Vdata is transmitted to the gate of the driving transistor Td, and the threshold voltage of the driving transistor Td is compensated to the gate of the driving transistor Td.
As shown in fig. 2, the first type pixel circuit 111 further includes a first reset module 40, an input terminal of the first reset module 40 is electrically connected to the first reset signal line SL1, an output terminal of the first reset module 40 is electrically connected to the gate of the driving transistor Td, and the first reset module 40 is configured to transmit the first reset voltage Vref1 transmitted by the first reset signal line SL1 to the gate of the driving transistor Td.
Alternatively, as shown in fig. 3, the first reset module 40 includes a sixth transistor T6 and a seventh transistor T7, wherein a first pole of the sixth transistor T6 is electrically connected to the first reset signal line SL1, a second pole of the sixth transistor T7 is electrically connected to a first pole of the seventh transistor T7, a second pole of the seventh transistor T7 is electrically connected to a gate of the driving transistor Td, a gate of the sixth transistor T6 and a gate of the seventh transistor T7 are electrically connected to the fourth scan line S4, and a signal transmitted by the fourth scan line S4 controls the switching states of the sixth transistor T6 and the seventh transistor T7 to be the same.
As shown in connection with fig. 4, the operation of the first type pixel circuit 111 further includes a reset phase E0 performed before the data writing phase E1. In the reset stage E0, the fourth scan line S4 transmits an active signal to control the sixth transistor T6 and the seventh transistor T7 to be turned on, and at this time, the first reset voltage Vref1 transmitted by the first reset signal line SL1 is transmitted to the gate of the driving transistor Td through the turned-on sixth transistor T6 and the turned-on seventh transistor T7 to reset the gate of the driving transistor Td.
It is understood that the gate potential of the driving transistor Td at the time of generating the light emission driving current is a potential after the data writing stage E1.
In the embodiment of the present application, the first gating module 20 is turned on after the data writing stage E1, so that the potential of the first node N1 can be regulated by the gate potential of the driving transistor Td when generating the light-emitting driving current, thereby reducing the potential difference between the first node N1 and the gate potential of the driving transistor Td when the display panel 01 emits light, further being beneficial to stabilizing the gate potential of the driving transistor Td, avoiding the occurrence of a larger change in the brightness of the display frame, and improving the display effect of the display panel 01.
In addition, the first gating module 20 is turned on after the data writing stage E1 in the embodiment of the present application, which can avoid the first gating module 20 from affecting the reset stage E0 and the data writing stage E1 of the first type pixel circuit 111, and is beneficial to ensuring the normal operation of the first type pixel circuit 111.
In one embodiment of the present application, please continue with fig. 4, the operation of the first type pixel circuit 111 further includes a light emitting stage E2 performed after the data writing stage E1.
The first gating module 20 is turned on in the light emitting phase E2.
It is understood that in the light emitting stage E2, the first transistor T1, the second transistor T2, the sixth transistor T6 and the seventh transistor T7 are all turned off. At this time, the driving transistor Td generates a light emission driving current for driving the light emitting module 12 according to the gate potential thereof.
In the embodiment of the application, when the first gating module 20 is turned on in the light emitting stage E2, the potential of the first node N1 in the light emitting stage E2 can be adjusted, so that the problem of leakage of the first node N1 to the gate electrode of the driving transistor Td in the light emitting stage E2 is solved, and the display effect of the display panel 01 is further improved.
Fig. 6 is a timing diagram of the first type of pixel circuit shown in fig. 3, and fig. 7 is a timing diagram of the first type of pixel circuit shown in fig. 3.
As shown in fig. 6, in one embodiment of the present application, the operation of the first type pixel circuit 111 further includes a conditioning phase E3 and a light emitting phase E2 sequentially performed after the data writing phase E1.
The first gating module 20 is turned on during the conditioning phase E3.
The timing shown in fig. 6 is different from the timing shown in fig. 4 mainly in that an adjustment stage E3 is provided between the data writing stage E1 and the light emitting stage E2, and the second scan line S2 and the third scan line S3 sequentially transmit an effective signal in the adjustment stage E3 to control the first transistor T1 and the second transistor T2 to be turned on.
The embodiment of the application can neutralize the potential of the first node N1 before the light-emitting stage E2, thereby being beneficial to keeping the grid potential of the driving transistor Td stable at the initial moment of the light-emitting stage E2 and further being beneficial to ensuring the brightness stability of the display frame picture.
It should be noted that, as shown in fig. 7, in some other embodiments, the second scan line S2 may be further configured to transmit an active signal to control the first transistor T1 to be turned on during the adjustment phase E3, and the third scan line S3 may be configured to transmit an active signal to control the second transistor T2 to be turned on during the light-emitting phase E2. Namely, the gate potential of the driving transistor Td is written into the second node N2 in the adjusting stage E3, and then the second node N2 is turned on with the first node N1 in the light emitting stage E2, so that the potential of the first node N1 is neutralized, the adjustment of the first node N1 is realized, and the problem of leakage of the first node N1 to the gate of the driving transistor Td is reduced.
Fig. 8 is a timing diagram of a first type of pixel circuit shown in fig. 3.
In one embodiment of the present application, the duration that the first sub-gating module 21 is turned on is not less than the duration that the second sub-gating module 22 is turned on. That is, the period in which the second scan line S2 transmits the effective signal (e.g., low level) is not less than the period in which the third scan line S3 transmits the effective signal (e.g., low level).
Alternatively, as shown in fig. 6, the duration t1 of the first sub-gating module 21 being turned on is equal to the duration t2 of the second sub-gating module 22 being turned on.
Alternatively, as shown in fig. 8, the duration t1 of the first sub-gate module 21 being turned on is longer than the duration t2 of the second sub-gate module 22 being turned on.
In the embodiment of the present application, when the time period for turning on the first sub-gate module 21 is longer than the time period for turning on the second sub-gate module 22, the time for writing the gate potential of the driving transistor Td into the second node N2 can be increased, which is favorable for more completely storing the gate potential of the driving transistor Td in the second node N2, so that the potential of the first node N1 is further close to the gate potential of the driving transistor Td after the first node N1 and the second node N2 are turned on, and further, the problem of leakage of the first node N1 to the gate of the driving transistor Td is further reduced.
When the duration of the first sub-gate module 21 is equal to the duration of the second sub-gate module 22, it is possible that the second scan line S2 and the third scan line S3 are provided by the same peripheral circuit, which is beneficial to reducing the number of peripheral driving circuits and reducing the design difficulty and the preparation difficulty of the display panel 01.
Fig. 9 is a timing diagram of a first type of pixel circuit shown in fig. 3.
In one embodiment of the present application, during operation of the first type pixel circuit 111, the first sub-gate module 21 is turned on for a period of time not less than the period of time for which the data voltage writing module 30 is turned on, and the second sub-gate module 22 is turned on for a period of time not less than the period of time for which the data voltage writing module 30 is turned on.
That is, during operation of the first-type pixel circuit 111, the second scan line S2 transmits an effective signal (e.g., low level) for a period of time not less than that of the first scan line S1, and the third scan line S3 transmits an effective signal (e.g., low level) for a period of time not less than that of the first scan line S1.
Alternatively, as shown in fig. 6, the duration t1 of the first sub-gate module 21 being turned on is equal to the duration t3 of the data voltage writing module 30 being turned on, and the duration t2 of the second sub-gate module 22 being turned on is equal to the duration t3 of the data voltage writing module 30 being turned on.
Alternatively, as shown in fig. 9, the duration t1 of the first sub-gate module 21 being turned on is greater than the duration t3 of the data voltage writing module 30 being turned on, and the duration t2 of the second sub-gate module 22 being turned on is greater than the duration t3 of the data voltage writing module 30 being turned on.
Of course, it is also possible to set the first sub-gate module 21 and the second sub-gate module 22 such that one of them is turned on for a period of time equal to the period of time for which the data voltage writing module 30 is turned on and the other is turned on for a period of time greater than the period of time for which the data voltage writing module 30 is turned on.
In the embodiment of the present application, when the on-time of the first sub-gate module 21 and the on-time of the second sub-gate module 22 are both longer than the on-time of the data voltage writing module 30, the time for writing the gate potential of the driving transistor Td into the second node N2 and the time for neutralizing the potential of the second node N2 with the potential of the first node N1 can be increased, which is favorable for more fully writing the gate potential of the driving transistor Td into the second node N2 and fully neutralizing the potential of the first node N1, so that the potential of the first node N1 is closer to the gate potential of the driving transistor Td after the data writing stage E1, thereby being favorable for further reducing the problem of leakage of the first node N1 into the gate of the driving transistor Td, and further being favorable for further improving the display effect of the display panel 01.
When the on-time of the first sub-gate module 21 and the on-time of the second sub-gate module 22 are both equal to the on-time of the data voltage writing module 30, the second scan line S2, the third scan line S3 and the first scan line S1 are provided by the same peripheral driving circuit while the adjustment of the potential of the first node N1 by the gate potential of the driving transistor Td is ensured, which is beneficial to further reducing the number of peripheral driving circuits and reducing the design difficulty and the preparation difficulty of the display panel 01.
Fig. 10 is a schematic diagram of still another first type of pixel circuit according to an embodiment of the present application.
In one embodiment of the present application, as shown in fig. 2, 3, 5 and 10, the first type pixel circuit 111 further includes a power supply voltage writing module 50 and a light emitting control module 60, wherein an input end of the power supply voltage writing module 50 is electrically connected to the second power supply voltage signal line PVDD, an output end of the power supply voltage writing module is electrically connected to the first pole of the driving transistor Td, a control end of the power supply voltage writing module is electrically connected to the light emitting control signal line EM, an input end of the light emitting control module 60 is electrically connected to the second pole of the driving transistor Td, an output end of the power supply voltage writing module is electrically connected to the first pole of the light emitting module 12, and a control end of the power supply voltage writing module is electrically connected to the light emitting control signal line EM.
Specifically, as shown in fig. 3, 5 and 10, the power supply voltage writing module 50 includes an eighth transistor T8, the light emission control module 60 includes a ninth transistor T9, a first pole of the eighth transistor T8 is electrically connected to the second power supply voltage signal line PVDD, a second pole is electrically connected to the first pole of the driving transistor Td, a gate is electrically connected to the light emission control signal line EM, a first pole of the ninth transistor T9 is electrically connected to the second pole of the driving transistor Td, a second pole is electrically connected to the first pole of the light emitting module 12, a gate is electrically connected to the light emission control signal line EM, and a second pole of the light emitting module 12 is electrically connected to the first power supply voltage signal line PVEE.
In the light emitting stage E2, the light emitting control signal line EM transmits an active signal to control the eighth transistor T8 and the ninth transistor T9 to be turned on, and the driving transistor Td generates a light emitting driving current according to the gate potential thereof and transmits the light emitting driving current to the first electrode of the light emitting module 12, so as to drive the light emitting module 12 to emit light. The light emitting module 12 may include an organic light emitting diode, a first pole of the light emitting module 12 may be an anode of the organic light emitting diode, and a second pole of the light emitting module 12 may be a cathode of the organic light emitting diode.
As shown in fig. 10, the third scan line S3 is electrically connected to the emission control signal line EM, and the signals transmitted by the emission control signal line EM control the switching states of the power supply voltage writing module 50, the emission control module 60, and the fourth transistor T4 to be the same. That is, the channel types of the eighth transistor T8, the ninth transistor T9, and the fourth transistor T4 are the same.
In the embodiment of the application, the third scan line S3 is electrically connected with the light emission control signal line EM, that is, the signal transmitted by the light emission control signal line EM is multiplexed to control the on-off state of the fourth transistor T4, so that the potential of the first node N1 can be regulated in the light emission stage E2 without additionally setting the control signal of the fourth transistor T4, which is beneficial to simplifying the design of peripheral driving circuits in the display panel 01 and reducing the manufacturing difficulty of the display panel 01.
With continued reference to fig. 2, in one embodiment of the present application, the first type pixel circuit 111 further includes a second reset module 70, an input terminal of the second reset module 70 is electrically connected to the first reset signal line SL1, an output terminal of the second reset module 70 is electrically connected to the first pole of the light emitting module 12, and the second reset module 70 is configured to transmit the first reset voltage Vref1 transmitted by the first reset signal line SL1 to the first pole of the light emitting module 12 to reset the first pole of the light emitting module 12.
Specifically, as shown in fig. 3, 5 and 10, the second reset module 70 includes a tenth transistor T10, a first electrode of the tenth transistor T10 is electrically connected to the first reset signal line SL1, a second electrode is electrically connected to the first electrode of the light emitting module 12, and a gate electrode is electrically connected to the first scan line S1. The tenth transistor T10 has the same channel type as the first and second transistors T1 and T2.
In the data writing stage E1, the tenth transistor T10 is turned on, and the first reset voltage Vref1 transmitted by the first reset signal line SL1 is transmitted to the first pole of the light emitting module 12 through the turned-on tenth transistor T10, thereby completing the reset of the light emitting module 12.
For the sake of clarity of explanation of the technical solution of the embodiment of the present application, the operation of the first-type pixel circuit 111 shown in fig. 3 is described below with reference to fig. 3 and 4.
The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are exemplified as P-type transistors.
The operation process of the first type pixel circuit 111 includes a reset phase E0, a data writing phase E1, and a light emitting phase E2, which are sequentially performed.
In the reset stage E0, the fourth scan line S4 transmits an on signal, i.e., a low level signal, the sixth transistor T6 and the seventh transistor T7 are turned on, and the first scan line S1, the second scan line S2, the third scan line S3 and the emission control signal line EM transmit an off signal, i.e., a high level signal, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are turned off. Meanwhile, the first reset signal line SL1 transmits the first reset voltage Vref1, and the first reset voltage Vref1 is transmitted to the gate of the driving transistor Td through the turned-on sixth transistor T6 and seventh transistor T7, thereby completing the reset of the gate of the driving transistor Td.
In the data writing stage E1, the first scan line S1 transmits an on signal, i.e., a low level signal, and the first, second, fifth and tenth transistors T1, T2, T5 and T10 are turned on, and the second, third, fourth and emission control signal lines S2, S3, S4 and EM transmit an off signal, i.e., a high level signal, and the third, fourth, sixth, seventh, eighth and ninth transistors T3, T4, T6, T7, T8 and T9 are turned off. Meanwhile, the data signal line DL1 transmits the data voltage Vdata, at the start point of the data writing stage E1, the gate potential of the driving transistor Td is the first reset voltage Vref1, the source potential of the driving transistor Td is the data voltage signal Vdata, the potential difference between the source and the gate of the driving transistor Td is (Vdata-Vref 1), and the potential difference between the source and the gate of the driving transistor Td is greater than 0, so that the driving transistor Td is turned on, and the data voltage Vdata is transmitted to the gate of the driving transistor Td through the turned-on driving transistor Td and the turned-on first transistor T1 and second transistor T2, such that the gate potential of the driving transistor Td gradually increases. When the gate potential of the driving transistor Td is equal to (Vdata-vth|), the driving transistor Td is turned off. Where Vth is the threshold voltage of the driving transistor Td.
Meanwhile, the first reset voltage Vref1 resets the first pole of the light emitting module 12 through the turned-on tenth transistor T10. Alternatively, the light emitting module 12 includes an organic light emitting diode, and the first reset voltage Vref1 resets an anode of the organic light emitting diode through the turned-on tenth transistor T10.
In the light emitting stage E2, the first scan line S1 and the fourth scan line S4 transmit off signals, i.e., high signals, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the tenth transistor T10 are turned off, the second scan line S2, the third scan line S3 and the light emitting control signal line EM transmit on signals, i.e., low signals, and the third transistor T3, the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 are turned on. Meanwhile, the second power voltage signal line PVDD transmits the second power voltage VDD, that is, the potential of the source of the driving transistor Td is the second power voltage VDD. Since the potential of the second power voltage VDD is greater than the potential of the data voltage Vdata, the driving transistor Td generates a light emitting driving current and transmits the light emitting driving current to the light emitting module 12 through the ninth transistor T9, controlling the light emitting module 12 to emit light.
Meanwhile, the third transistor T3 and the fourth transistor T4 are turned on in sequence, so that the gate potential of the driving transistor Td can be written into the second node N2 through the third transistor T3, and then written into the first node N1 through the fourth transistor T4 to adjust the potential of the first node N1, while avoiding the potential of the first node N1 from influencing the gate potential of the driving transistor Td through the third transistor T3 and the fourth transistor T4, the potential difference between the first node N1 and the gate of the driving transistor Td can be reduced, thereby being beneficial to improving the problem of the gate leakage of the first node N1 to the driving transistor Td, stabilizing the gate potential of the driving transistor Td, and further being beneficial to avoiding the occurrence of larger change in brightness of the display frame picture, and improving the display effect of the display panel 01.
Fig. 11 is a schematic diagram showing a connection between adjacent three rows of the first type pixel circuits in fig. 1.
In one embodiment of the present application, as shown in fig. 1 and 11, the display panel 01 includes a plurality of rows of the first type pixel circuits 111, the second scan line S2 electrically connected to the i-th row of the first type pixel circuits 111 is electrically connected to the first scan line S1 electrically connected to the i+1th row of the first type pixel circuits 111, and the third scan line S3 electrically connected to the i-th row of the first type pixel circuits 111 is electrically connected to the first scan line S1 electrically connected to the i+2th row of the first type pixel circuits 111. Wherein i is not less than 1.
That is, the gate of the third transistor T3 in the i-th row first-type pixel circuit 111 is electrically connected to the gate of the fifth transistor T5 in the i+1-th row first-type pixel circuit 111, and the gate of the fourth transistor T3 in the i-th row first-type pixel circuit 111 is electrically connected to the gate of the fifth transistor T5 in the i+2-th row first-type pixel circuit 111.
In the embodiment of the application, the second scan line S2, the third scan line S3 and the first scan line S1 can be provided by the same peripheral driving circuit, which is beneficial to reducing the number of peripheral driving circuits and reducing the design difficulty and the preparation difficulty of the display panel 01.
Further, referring to fig. 11, the first scan line S1 electrically connected to the i-th row of the first type pixel circuits 111 may be electrically connected to the fourth scan line S4 electrically connected to the i+1th row of the first type pixel circuits 111, so that the first scan line S1, the second scan line S2, the third scan line S3 and the fourth scan line S4 may be provided by the same peripheral driving circuit, thereby being beneficial to further reducing the number of peripheral driving circuits and reducing the design difficulty and the manufacturing difficulty of the display panel 01.
Fig. 12 is a schematic diagram of another display panel according to an embodiment of the present application, and fig. 13 is a schematic diagram of connection between a second type pixel circuit and a first type pixel circuit according to an embodiment of the present application.
In one embodiment of the present application, as shown in fig. 12 and 13, the plurality of pixel circuits 11 further includes a second type of pixel circuit 112, and the second type of pixel circuit 112 may be arranged in line with the first type of pixel circuit 111.
The second type pixel circuit 112 includes a second gate module 80, and a first end of the second gate module 80 is electrically connected to the first node N1, and a second end of the second gate module 80 is electrically connected to the second node N2 in the first type pixel circuit 111.
The switching state of the second gating module 80 is the same as the switching state of the second sub-gating module 22 in the first-type pixel circuit 111.
Specifically, in the second type pixel circuit 112, the second gating module 80 includes a fourth transistor T4, the first pole of the fourth transistor T4 is electrically connected to the first node N1, the second pole is electrically connected to the second node N2 in the first type pixel circuit 111, and the gate is electrically connected to the third scan line S3 electrically connected in the first type pixel circuit 111. The second type pixel circuit 112 is located in the same row as the first type pixel circuit 111.
The second type pixel circuit 112 shown in fig. 13 is different from the first type pixel circuit 111 mainly in that the third transistor T3 and the first capacitor C1 are not disposed in the second type pixel circuit 112.
In the embodiment of the present application, after the first sub-gate module 21 in the first type pixel circuit 111 writes the gate potential of the driving transistor Td in the first type pixel circuit 111 into the second node N2, the second gate module 80 in the second type pixel circuit 112 is turned on, so that the first node N1 in the second type pixel circuit 112 is turned on with the second node N2 in the first type pixel circuit 111, and the potential of the second node N2 in the first type pixel circuit 111 and the potential of the first node N1 in the second type pixel circuit 112 are utilized to reduce the potential difference between the first node N1 in the second type pixel circuit 112 and the gate of the driving transistor Td in the second type pixel circuit 112, thereby being beneficial to improving the stability of the brightness of the light emitting module 12 driven by the second type pixel circuit 112, and further ensuring the display quality of the display panel 01.
The embodiment of the application can reduce the number of the transistors in the display panel 01 while improving the display quality of the display panel 01, thereby being beneficial to reducing the cost of the display panel 01.
Fig. 14 is a schematic diagram of a display device according to an embodiment of the application.
An embodiment of the present application provides a display device 02, as shown in fig. 14, where the display device 02 includes a display panel 01 provided in the above embodiment. The display device 02 provided by the embodiment of the application can be a mobile phone, and in addition, the display device 02 can also be an electronic device such as a computer, a television and the like.
In the display device 02, by disposing the first gating module 20 between the first node N1 and the gate of the driving transistor Td and adjusting the potential of the first node N1 by using the gate potential of the driving transistor Td, the potential difference between the first node N1 and the gate of the driving transistor Td can be reduced, so that the problem of leakage of the first node N1 to the gate of the driving transistor Td can be advantageously improved, the gate potential of the driving transistor Td can be stabilized, and further, a larger variation in brightness of the display frame can be advantageously avoided, and the display effect of the display device 02 can be improved.
In addition, in the first gating module 20, the period when the first sub-gating module 21 is turned on is set before the period when the second sub-gating module 22 is turned on, the gate potential of the driving transistor Td may be written into the second node N2 through the first sub-gating module 21, and then written into the first node N1 through the second sub-gating module 22 to adjust the potential of the first node N1, so that the potential of the first node N1 may be prevented from affecting the gate potential of the driving transistor Td through the first gating module 20, thereby being beneficial to further ensuring stability and accuracy of the gate potential of the driving transistor Td and further improving the display effect of the display device 02.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the application.
Claims (14)
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| CN115084165A (en) * | 2022-06-28 | 2022-09-20 | 云谷（固安）科技有限公司 | Array substrate, display panel and display device |
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| CN111179859B (en) * | 2020-03-16 | 2021-03-02 | 京东方科技集团股份有限公司 | Pixel circuit, display panel and display device |
| KR102772693B1 (en) * | 2020-06-02 | 2025-02-26 | 삼성디스플레이 주식회사 | Pixel of an organic light emitting diode display device, and organic light emitting diode display device |
| CN114038427B (en) * | 2021-11-08 | 2024-03-29 | 维信诺科技股份有限公司 | display panel |
| CN114038430B (en) * | 2021-11-29 | 2023-09-29 | 武汉天马微电子有限公司 | Pixel circuit and driving method thereof, display panel, display device |
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| CN115084165A (en) * | 2022-06-28 | 2022-09-20 | 云谷（固安）科技有限公司 | Array substrate, display panel and display device |
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