CN115630537B - A navigation signal simulation method and system based on on-chip simulation - Google Patents

Abstract

The invention discloses a navigation signal simulation method and a system based on-chip simulation, which comprises the following steps: the control software analyzes the scene and sends the scene to the mathematical simulation software; the control software sends an initialization instruction to the mathematical simulation software; carrying out simulation initialization by mathematical simulation software according to configuration items and scenes in the configuration file; and the control software sends a simulation starting instruction to the mathematical simulation software. The FPGA chip provided by the invention has the advantages that the hardware core processor added on the internal circuit is basically independent from the logic work of the FPGA, the software programmability of the processor and the hardware programmability of the FPGA are integrated, a Linux real-time operating system is operated at the end of the hardware core processor, and meanwhile, the high-real-time, high-performance and modularized navigation signal simulation system for on-chip simulation is realized by combining the parallel processing capability of the FPGA and the advantage of high-bandwidth connection between the SOC FPGA chip processor and the FPGA.

Description

A navigation signal simulation method and system based on on-chip simulation

Technical Field

The present invention relates to the field of navigation, and in particular to a navigation signal simulation method and system based on on-chip simulation.

Background Art

At present, satellite navigation signal simulation in the domestic market generally adopts host computer + CPU + FPGA architecture, host computer + FPGA architecture or ZYNQ-based system architecture.

Satellite navigation signal simulators based on independent host computer + CPU + FPGA architecture or host computer + FPGA architecture occupy a large volume, are costly, and have limited real-time performance;

Satellite navigation signal simulator based on ZYNQ The integrated miniaturized satellite navigation, although small in size, has a single function and a limited number of channels, and cannot realize multi-system and multi-user simulation.

The signal simulation unit in the navigation signal simulator needs to complete the simulation of navigation signals of four major and two small navigation systems, including the requirements of parallel simulation of dozens of navigation signal frequencies and hundreds of satellites. The amount of simulation calculation data is relatively large, which places high demands on the simulation computing capabilities of the simulator.

Summary of the invention

The object of the present invention is to provide a navigation signal simulation method and system based on on-chip simulation to solve the problems raised in the above background technology.

To achieve the above object, the present invention provides the following technical solutions:

A navigation signal simulation method based on on-chip simulation comprises the following steps:

Step S1, the control software analyzes the scene and sends it to the mathematical simulation software;

Step S2, the control software sends an initialization instruction to the mathematical simulation software;

Step S3, the mathematical simulation software performs simulation initialization according to the configuration items and scenarios in the configuration file;

Step S4, the control software sends a simulation start instruction to the digital simulation software to start the simulation;

Step S5, the mathematical simulation software performs simulation according to the simulation frequency and scenario parameters in the configuration items, simulation time, carrier trajectory, ephemeris and other parameters, generates observation data and telegram data, and packages them into DDS data packets and sends them to FPGA;

Step S6, the DDS core generates a digital baseband signal according to the DDS data packet sent by the digital simulation;

In step S7, the DA chip converts the digital signal into an analog baseband signal, and then performs up-conversion and power control through an external RF module to output an analog satellite signal.

Furthermore, in step S1, the control software configures the IP address of the mathematical simulation software that needs to participate in the simulation, and the control software configures the startup method of the mathematical simulation software that needs to participate in the simulation, including immediate startup, in which the mathematical simulation software directly starts the simulation calculation after receiving the startup instruction; synchronous startup, in which the mathematical simulation software starts the simulation calculation when the next PPS edge arrives; external signal triggered startup, in which the mathematical simulation software starts the simulation when it detects that the external startup signal is pulled high. When multiple on-chip simulation systems are combined for simulation, they can be configured as synchronous startup or external signal triggered startup to achieve synchronous simulation.

Furthermore, in step S3, the mathematical simulation software performs simulation initialization according to configuration items such as frequency configuration and channel configuration in the configuration file, and reports information such as frequency to the control software.

Furthermore, in step S4, the control software parses the scene and sends it to the mathematical simulation software, mainly including simulation time, simulation beat, constellation parameters, carrier trajectory, antenna parameters, interference parameters, etc., and sends corresponding ephemeris parameters to the mathematical simulation software according to the configuration information such as frequency reported by the mathematical simulation software.

Furthermore, in step S5, the mathematical simulation software determines whether the simulation duration has ended. If not, it waits for the FPGA to feedback the next beat ready flag, and waits for the next beat to be ready to start the next beat simulation.

A navigation signal simulation system based on on-chip simulation comprises a simulation control software module and an on-chip simulation module, wherein the on-chip simulation module comprises a SOC FPGA chip, a DA chip and a clock module, wherein the SOC FPGA chip integrates a processor and an FPGA, wherein the mathematical simulation software module runs on the processor, and the digital baseband signal generation module runs on the FPGA, wherein the digital baseband signal generation module receives a signal input from a clock module and outputs the generated baseband signal to the DA chip, wherein the simulation control software module runs on the SOC FPGA chip processor or a host computer; wherein the clock module is connected to an input interface for receiving a clock signal; and wherein the DA chip is connected to a radio frequency submodule for transmitting a radio frequency signal.

Furthermore, there are one or more on-chip simulation modules, and the simulation control software module runs in the host computer and controls one or more on-chip simulation modules at the same time.

Furthermore, the mathematical simulation software module includes a multi-frequency point unit, a multi-element unit and a multi-carrier unit; the multi-frequency point unit generates multi-frequency points through navigation message simulation and/or satellite constellation simulation and/or orbit simulation; the multi-element unit generates multiple elements through attitude simulation, and the attitude simulation includes at least one of carrier attitude simulation, antenna element attitude simulation, antenna installation position simulation, and antenna pattern simulation; the multi-carrier unit generates multiple carriers through trajectory simulation, and the trajectory simulation includes multi-carrier position simulation and/or multi-carrier dynamic simulation.

Furthermore, a plurality of the mathematical simulation software modules form a signal submodule, and the signal submodule sends the multi-array data to the radio frequency submodule, and the signal submodule corresponds to the radio frequency submodule one by one.

Furthermore, multiple mathematical simulation software modules and their corresponding radio frequency sub-modules form a signal generation board, and the signal generation board is one or more. The multi-element navigation signals output by the multiple signal generation boards are sent to a power control and synthesis board. Multiple antenna elements are arranged on the power control and synthesis board to combine and broadcast the simulation signals.

Furthermore, the signal submodule includes 4 ZYNQ units, the ZYNQ unit is a signal generation unit, and a mathematical simulation calculation software module runs on the ZYNQ unit. Each calculation module opens up multiple calculation processes for parallel calculation based on an embedded real-time operating system, and supports the configuration of signal simulation modes, thereby realizing the combined simulation of multi-frequency points, multi-satellites, multi-antennas, multi-carriers, and multi-element modes.

Furthermore, the simulation system adopts a multi-task concurrent mode and runs a mathematical simulation calculation software module on the ZYNQ of each signal sub-module; the mathematical simulation calculation software module receives at least one of the frequency parameters/ephemeris parameters/telegram parameters/trajectory data/antenna parameters, and sends out the multiple satellite observation data obtained by simulation through different DDS channels.

Furthermore, the method for implementing on-chip simulated navigation signal and communication signal transmission is as follows: A new integrated navigation/communication signal is adopted, in which the traditional satellite navigation system signal is used as a navigation channel and the cyclic shift keying signal is used as a communication channel.

Furthermore, in order to improve the resistance of the communication signal to multi-channel interference, a master-slave receiving method based on a Rake receiver is adopted, and the parameters of the Rake receiver are estimated by the navigation signal. The energy of the multipath signal is obtained from the Rake receiver using multiple parallel correlators, and the energy is combined according to the maximum ratio combining algorithm. In the navigation signal simulation system based on chip simulation, the method can effectively suppress the interference of multiple channels and improve the communication quality. The traditional satellite navigation signal and the corresponding Rake receiver can still work independently, ensuring the compatibility of the integrated signal.

Compared with the prior art, the present invention has the following beneficial effects:

1. The present invention is based on SOC+FPGA chip. A hard-core processor is added to the internal circuit of the FPGA chip. The processor and the FPGA logic work basically independently, integrating the software programmability of the processor and the hardware programmability of the FPGA. Based on the characteristics of the SOC+FPGA chip, the Linux real-time operating system is run on the hard-core processor end. At the same time, the FPGA parallel processing capability and the advantages of the high-bandwidth connection between the SOC FPGA chip processor and the FPGA are combined to realize a high real-time, high-performance, modular on-chip simulation navigation signal simulation system.

2. The DA chip of the present invention converts digital signals into analog baseband signals and then performs up-conversion and power control through an external RF module to realize satellite signal simulation. The clock module generates a 10MHz clock signal and a 1PPS signal and distributes them to the FPGA and DA chip for clock synchronization. The clock module has an external 10MHz clock input interface. When there is an external clock input, the external clock will be used for synchronization between multiple systems.

3. In the present invention, the simulation control software and the mathematical simulation software can be connected to the communication module and communicate using the TCP protocol. The simulation control software can run independently on the processor or the host computer and only needs to be in the same local area network as the on-chip simulation module B. The simulation control software can be connected to multiple mathematical simulation software at the same time for control. Multiple on-chip simulation modules use the same external input clock, thereby realizing the combined synchronous simulation of multiple on-chip simulation systems.

4. The present invention innovatively adopts high-precision navigation signal simulation technology based on distributed on-chip real-time simulation to solve the problem of parallel simulation of large-scale satellite navigation signals with multi-system compatibility and interoperability under a unified platform. The modular design is easy to combine and expand, and has the characteristics of small size, high integration, comprehensive functions, strong real-time performance, and multiple channels.

5. The new integrated navigation/communication signal and the master-slave receiving method based on the Rake receiver can effectively suppress the interference of multiple channels and improve the communication quality. The traditional satellite navigation signal and the corresponding Rake receiver can still work independently, which ensures the compatibility of the integrated signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic flow chart of a navigation signal simulation method based on on-chip simulation according to the present invention;

FIG2 is a schematic diagram of the structure of a navigation signal simulation system based on on-chip simulation according to the present invention;

FIG3 is a schematic diagram of a simulation flow of a navigation signal simulation system based on on-chip simulation according to the present invention;

FIG4 is a schematic diagram of the structure of an embodiment of a distributed on-chip simulation system according to the present invention;

FIG5 is a schematic diagram of a signal submodule of the present invention;

FIG6 is a schematic diagram of a parallel computing simulation of the present invention;

FIG7 is a structure of integrated navigation/communication signals of the present invention;

FIG8 is a flow chart of receiving a signal according to the present invention;

FIG. 9 is a master-slave Rake receiver model of the present invention.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

Example 1

Please refer to Figures 1-3, the present invention provides a technical solution:

A navigation signal simulation method based on on-chip simulation comprises the following steps:

Step S1, the control software analyzes the scene and sends it to the mathematical simulation software;

Step S2, the control software sends an initialization instruction to the mathematical simulation software;

Step S3, the mathematical simulation software performs simulation initialization according to the configuration items and scenarios in the configuration file;

Step S4, the control software sends a simulation start instruction to the digital simulation software to start the simulation;

Step S5, the mathematical simulation software performs simulation according to the simulation frequency and scenario parameters in the configuration items, simulation time, carrier trajectory, ephemeris and other parameters, generates observation data and telegram data, and packages them into DDS data packets and sends them to FPGA;

Step S6, the DDS core generates a digital baseband signal according to the DDS data packet sent by the digital simulation;

In step S7, the DA chip converts the digital signal into an analog baseband signal, and then performs up-conversion and power control through an external RF module to output an analog satellite signal.

In the present invention, the simulation control software is used to implement scene analysis, interface display, simulation parameter distribution and other functions, and the mathematical simulation software is used to implement mathematical simulation calculations of multiple frequency points, receive ephemeris parameters, trajectory parameters and other simulation parameters from the outside, calculate observation data, arrange navigation messages, calculate and distribute DDS data. The FPGA interface processing module is used to transfer DDS parameters, simulation parameters, control instructions, etc. to the DDS kernel, and provide hardware beats, simulation status and other information for the digital simulation. The DDS kernel generates a navigation baseband signal based on the DDS data.

In step S1, the control software configures the IP address of the mathematical simulation software that needs to participate in the simulation, and the control software configures the startup mode of the mathematical simulation software that needs to participate in the simulation, including immediate startup, in which the mathematical simulation software directly starts the simulation calculation after receiving the startup instruction; synchronous startup, in which the mathematical simulation software starts the simulation calculation when the next PPS edge arrives; external signal triggered startup, in which the mathematical simulation software starts the simulation when it detects that the external startup signal is pulled high. When multiple on-chip simulation systems are combined for simulation, they can be configured as synchronous startup or external signal triggered startup to achieve synchronous simulation.

In the present invention, in step S3, the mathematical simulation software performs simulation initialization according to configuration items such as frequency configuration and channel configuration in the configuration file, and reports information such as frequency to the control software.

In the present invention, in step S4, the control software analyzes the scene and sends it to the mathematical simulation software, mainly including simulation time, simulation beat, constellation parameters, carrier trajectory, antenna parameters, interference parameters, etc., and sends corresponding ephemeris parameters to the mathematical simulation software according to the configuration information such as frequency reported by the mathematical simulation software.

In the present invention, in step S5, the mathematical simulation software determines whether the simulation duration is over, and if not, waits for the FPGA to feedback the next beat ready flag, and waits for the next beat to be ready to start the next beat simulation.

Example 2

In the present invention, the navigation signal simulation system based on on-chip simulation includes a simulation control software module and an on-chip simulation module. The on-chip simulation module includes a SOC FPGA chip, a DA chip, and a clock module. The SOC FPGA chip integrates a processor and an FPGA. The mathematical simulation software module runs on the processor, and the digital baseband signal generation module runs on the FPGA. The digital baseband signal generation module receives a signal input from the clock module and outputs the generated baseband signal to the DA chip. The clock module is connected to an input interface to receive a clock signal. The DA chip is connected to a radio frequency submodule, and the radio frequency submodule transmits a radio frequency signal.

SOC FPGA chip, DA chip and clock module, among which the SOC FPGA chip is an FPGA with an embedded processor core, which mainly performs simulation calculations to generate digital baseband signals; the DA chip converts digital signals into analog baseband signals and then performs up-conversion and power control through an external RF module to realize satellite signal simulation; the clock module generates 10MHz clock signals and 1PPS signals and distributes them to FPGA and DA chips for clock synchronization. In particular, the clock module has an external 10MHz clock input interface. When there is an external clock input, the external clock will be used for synchronization between multiple systems.

The present invention is based on SOC FPGA chips. Such FPGA chips add hard-core processors to the internal circuits. The processor and FPGA logic work basically independently. Such structures integrate the software programmability of the processor and the hardware programmability of the FPGA, such as XILINX ZYNQ-7000 series, Altera Cyclone V series, Microsemi SmartFusion series, Fudan Micro FMQL45T900, etc. Based on the characteristics of SOC FPGA chips, the present invention runs the Linux real-time operating system on the hard-core processor side, and combines the FPGA parallel processing capabilities and the advantages of high-bandwidth connection between the SOC FPGA chip processor and the FPGA to realize a high-real-time, high-performance, modular on-chip simulation navigation signal simulation system.

In some embodiments, the simulation control software module runs on the SOC FPGA chip processor, and in other embodiments, the simulation control software module runs on the host computer and can control one or more on-chip simulation modules at the same time. The simulation control software and the mathematical simulation software use the TCP protocol for communication, and the simulation control software can run independently on the host computer, and only needs to be in the same local area network as the on-chip simulation module.

In some embodiments, there are one or more on-chip simulation modules, and the simulation control software module runs in the host computer. The simulation control software module controls the on-chip simulation modules in a distributed manner, and multiple on-chip simulation modules use the same external input clock, thereby realizing the combined synchronous simulation of multiple on-chip simulation systems. In this case, it is only necessary to configure the IP addresses of multiple mathematical simulation software in the simulation control software.

Referring to Figure 4, the mathematical simulation software module includes a multi-frequency point unit, a multi-element unit and a multi-carrier unit; the multi-frequency point unit generates multi-frequency points through navigation message simulation, or satellite constellation simulation, or orbit simulation; the multi-element unit generates multiple elements through attitude simulation, and attitude simulation includes but is not limited to carrier attitude simulation, antenna element attitude simulation, antenna installation position simulation, and antenna radiation pattern simulation; the multi-carrier unit generates multiple carriers through trajectory simulation, and trajectory simulation includes but is not limited to multi-carrier position simulation and multi-carrier dynamic simulation.

Example 3

In this embodiment, the on-chip simulation module is distributed. The signal simulation unit in the navigation signal simulator needs to complete the simulation of navigation signals of four major and two minor navigation systems at most, including the requirements of parallel simulation of dozens of navigation signal frequencies and hundreds of satellites. The amount of simulation calculation data is relatively large, which puts high demands on the simulation calculation ability of the simulator. Therefore, this embodiment is based on the high-precision navigation signal simulation technology of distributed on-chip real-time simulation to solve the problem of parallel simulation of large-scale satellite navigation signals with multi-system compatibility and interoperability under a unified platform.

Taking into account the requirements of satellite constellation simulation, environment simulation, user simulation, etc. and time synchronization margin, the present invention uses a processor with a distributed architecture based on real-time mathematical simulation software to complete high-density computing. Referring to Figures 4-6, multiple mathematical simulation software modules form a signal submodule, and the signal submodule sends multiple array data to the radio frequency submodule, and the signal submodule corresponds to the radio frequency submodule one by one. Multiple mathematical simulation software modules and their corresponding radio frequency submodules form a signal generation board, and the signal generation board is one or more. The multi-element navigation signals output by multiple signal generation boards at the same time are sent to the power control and synthesis board, and multiple antenna array elements are set on the power control and synthesis board to combine the simulation signals and broadcast them.

The signal submodule includes 1 to 4 ZYNQ (scalable processing platform launched by Xilinx) units. One ZYNQ is a signal generation unit. Mathematical simulation computing software modules run on ZYNQ. Each computing module opens up multiple computing processes for parallel computing based on an embedded real-time operating system and supports the configuration of signal simulation modes, thereby realizing combined simulation of multi-frequency points, multi-satellites, multi-antennas, multi-carriers, and multi-element modes.

Referring to Figure 5, each signal submodule may include 1 to 4 ZNYQ modules, DA chips, memory cards, physical layers, etc., and one ZYNQ module is a signal generation unit. The ZNYQ module has multiple bus interfaces, among which the SD0 interface is connected to the TF card, the SD1 interface is connected to the eMMC card, the SPI interface is connected to the QSPI FLASH, and the PCIE X2 interface/GTX_RX/UART/I2C/pps/PCODEST and other interfaces are connected to the RF submodule. The ZNYQ module is connected to the DA chip, and the DA chip outputs I and Q baseband signals. The ZNYQ module is connected to the physical layer through the GMII interface, and the physical layer is connected to the RF submodule through the GPHY interface.

Referring to Figure 6, the simulation system adopts a multi-task concurrent mode and runs a mathematical simulation calculation software module on the ZYNQ of each signal sub-module; the mathematical simulation calculation software module receives at least one of the frequency point parameters/ephemeris parameters/telegram parameters/trajectory data/antenna parameters, and sends out multiple satellite observation data obtained by simulation through different DDS (Direct Digital Frequency Synthesis) channels.

The digital simulation computing module is run on ZYNQ (each signal sub-module can be configured with 4 distributed processor real-time digital simulation computing modules). Each computing module opens up multiple computing processes for parallel computing based on the embedded real-time operating system, and supports the configuration of signal simulation mode to achieve combined simulation of multi-frequency points, multi-satellites, multi-antennas, multi-carriers, and multi-element modes.

Taking into account the real-time operating system's ability to have multiple concurrent functions, in order to give full play to the computing efficiency of the real-time operating system, the present invention adopts a multi-task concurrent simulation engine. Based on the concept of "on-chip simulation", mathematical simulation software is run on the ZYNQ of each signal sub-module to perform mathematical simulation, making full use of the parallel computing capabilities of multi-CPU and multi-core operating systems.

The concurrency and communication between multiple tasks are carried out at two levels: first, the concurrent tasks used within a CPU use shared memory and semaphore mode for communication, which is the fastest mode; second, between multiple real-time computing modules in an AXI chassis, the AXI high-speed backplane can be used to realize the exchange of model data between multiple real-time computing boards. Therefore, the simulation engine must adapt to the characteristics of hierarchical real-time communication. At the same time, in order to further improve the efficiency of the simulation engine, a customized real-time operating system is used to optimize the efficiency while improving the real-time control performance of the system.

The working principle of the present invention is as follows: the control software is configured with the IP address of the mathematical simulation software that needs to participate in the simulation, and the control software is configured with the startup mode of the mathematical simulation software that needs to participate in the simulation, including immediate startup: the mathematical simulation software directly starts the simulation calculation after receiving the startup instruction, synchronous startup: the mathematical simulation software starts the simulation calculation when the next PPS edge arrives; external signal trigger startup: the mathematical simulation software starts the simulation when it detects that the external startup signal is pulled high. When multiple on-chip simulation systems are combined for simulation, it can be configured as synchronous startup or external signal trigger startup to realize synchronous simulation. The control software sends an initialization instruction to the mathematical simulation software, and the mathematical simulation software The software performs simulation initialization according to the frequency configuration, channel configuration and other configuration items in the configuration file, and reports the frequency and other information to the control software. The control software parses the scene and sends it to the mathematical simulation software, mainly including simulation time, simulation beat, constellation parameters, carrier trajectory, antenna parameters, interference parameters, etc., and sends the corresponding ephemeris parameters to the mathematical simulation software according to the frequency and other configuration information reported by the mathematical simulation software. The control software sends a simulation start instruction to the mathematical simulation software to start the simulation. The mathematical simulation software performs simulation according to the simulation frequency, ephemeris, simulation time, carrier trajectory and other parameters in the configuration items according to the beat, generates observation data and telegram data, and packages them into DDS data packets and sends them to FPGA. The mathematical simulation software determines whether the simulation duration is over. If not, it waits for the FPGA to feedback the next beat ready flag, and waits for the next beat to be ready to start the next beat simulation.

Example 4

A navigation signal simulation system based on on-chip simulation realizes the on-chip simulation navigation signal and communication signal transmission in the following way: a new integrated navigation/communication signal is adopted, a traditional satellite navigation system signal is used as a navigation channel, and a cyclic shift keying signal is used as a communication channel.

The cyclic shift keying signal provides the communication service, while the conventional navigation system signal is used as the navigation channel, and they are transmitted synchronously at the same frequency and phase. Therefore, the navigation channel also provides synchronization assistance for the communication signal. The integrated navigation/communication signal can be expressed as:

表示载波的初始相位。集成导航/通信信号的结构如图7所示。Where, j represents the satellite number, i represents the cyclic shift number of the pseudo-noise code, A represents the signal amplitude, C and B are the pseudo-noise codes for modulating the navigation signal and the communication signal respectively, D and E are the data codes, f _c represents the carrier frequency,

Indicates the initial phase of the carrier. The structure of the integrated navigation/communication signal is shown in Figure 7.

计算为：Information is transmitted by the number of cyclic shifts of the pseudo-noise code in the communication signal. A pseudo-noise code carries multiple bits of data through cyclic shifts. The receiver converts the correlation function

is calculated as:

Where, N is the length of the pseudo noise code, h = 0, 1, ..., N-1; i = 0, 1, ..., N-1. It can be seen from the above formula that the position of the peak in the correlation function changes with the number of cyclic shifts of the pseudo noise code. Therefore, when the communication signal is sent independently, the signal delay of different paths cannot be estimated by the autocorrelation peak position, which makes the communication signal more sensitive to multi-channel interference.

A signal subjected to multi-channel fading can be expressed as:

Where, M is the number of paths, A _l (t) is the amplitude of the lth path signal, τ _l (t) represents the delay of the lth channel signal, θ _l (t) represents the phase of the lth path signal, and x ^j (t) represents the line of sight signal when M=l.

Assuming the number of paths is 2, the multi-channel signal is delayed by half a chip compared to the line-of-sight signal, and the received signal is:

Where, T _c is the chip period. If the local signal is,

Wherein, A ₁ (t) represents the estimated amplitude of the line of sight signal, τ ₁ (t) represents the estimated delay, and θ ₁ (t) is the estimated phase.

The GNSS receiver calculates the correlation between the received signal and the local signal, which can be expressed as

为延迟误差，

和

分别表示导航视线信号与本地信号的相关结果和通信视线信号与本地信号的相关结果；

和

表示导航多信道信号与本地信号的相关结果和通信多信道信号与本地信号的相关结果。以导航信号为例，

和

的表达式为，in,

is the delay error,

and

Respectively represent the correlation results between the navigation sight line signal and the local signal and the correlation results between the communication sight line signal and the local signal;

and

Indicates the correlation results between the navigation multi-channel signal and the local signal and the correlation results between the communication multi-channel signal and the local signal. Taking the navigation signal as an example,

and

The expression of is,

From the above formula, we can see that the impact of multi-channel signals on the correlation results varies according to the value of θ ₂ - θ _1. When the multi-channel signal and the line of sight signal are in the same or opposite phase, the impact reaches the maximum. Since the multi-channel signal affects the tracking performance of the receiver, the correlation results are distorted, which ultimately reduces the positioning accuracy.

Furthermore, in order to improve the resistance of the communication signal to multi-channel interference, the navigation signal simulation system based on chip simulation further adopts a master-slave receiving method based on a Rake receiver, and the parameters of the Rake receiver are estimated by the navigation signal. This method can effectively suppress the interference of multiple channels and improve the communication quality. The traditional satellite navigation signal and the corresponding Rake receiver can still work independently, ensuring the compatibility of the integrated signal.

Since the navigation signal and the communication signal are transmitted synchronously on the same frequency, their multi-channel fading is the same. The Rake receiver of the communication channel can be configured by using the parameters of the navigation channel measured by the corresponding Rake receiver. The receiving process is shown in Figure 8.

The master-slave Rake receiver model is shown in Figure 9. The time delay of each path, i.e., τ ₁ , τ ₂ , ... , τ _M, has been measured by the master Rake receiver, and the integration time of the correlator is the symbol period. The slave Rake receiver uses multiple parallel correlators to obtain the energy of the multipath signal and combines the energy according to the maximum ratio combining algorithm. Because the maximum ratio combining algorithm has the best performance among the three common combining algorithms. In the maximum ratio combining algorithm, the weighting coefficient of the multi-channel signal is determined by the ratio of the signal envelope to the noise power, which can be expressed as:

Where P _l (t) is the signal envelope and n _l is the noise power. The expression of the output signal envelope is

Among them, γ _max is the maximum signal-to-noise ratio that the output signal can achieve, which is equal to the sum of the maximum signal-to-noise ratios of each branch signal.

It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims (16)

1. A navigation signal simulation method based on-chip simulation is characterized in that: the method comprises the following steps:

s1, controlling software to analyze a scene and transmitting the scene to mathematical simulation software;

s2, the control software sends an initialization instruction and a configuration file to the mathematical simulation software;

s3, carrying out simulation initialization by the mathematical simulation software according to configuration items and scenes in the configuration file;

s4, the control software sends a simulation starting instruction to the mathematical simulation software to start simulation;

s5, simulating by mathematical simulation software according to simulation frequency points in configuration items, scene parameter simulation time, carrier tracks and ephemeris parameters according to beats to generate observation data and telegraph text data, and packaging the observation data and the telegraph text data into a DDS data packet to be sent to the FPGA;

s6, generating a digital baseband signal by the DDS kernel according to a DDS data packet issued by mathematical simulation software;

and S7, converting the digital signal into an analog baseband signal by the DA chip, and outputting an analog satellite signal by performing up-conversion and power control through an external radio frequency module.

2. The on-chip simulation-based navigation signal simulation method of claim 1, wherein: in the step S1, the control software configures the IP address of the mathematical simulation software participating in the simulation and the starting mode of the simulated mathematical simulation software.

3. The on-chip simulation-based navigation signal simulation method according to claim 2, wherein: the starting mode comprises immediate starting, and the mathematical simulation software directly starts simulation calculation after receiving a starting instruction; synchronously starting, starting simulation calculation by mathematical simulation software when the next PPS edge arrives; and triggering and starting by an external signal, and starting simulation by the mathematical simulation software when detecting that the external starting signal is pulled high.

4. The on-chip simulation based navigation signal simulation method of claim 3, wherein: if a plurality of on-chip simulation modules are combined for simulation, synchronous starting or external signal triggering starting is configured, and synchronous simulation is achieved.

5. The on-chip simulation-based navigation signal simulation method of claim 1, wherein: in step S3, the mathematical simulation software performs simulation initialization according to the frequency point configuration and the channel configuration in the configuration file, and reports the frequency point information and the channel information to the control software.

6. The on-chip simulation-based navigation signal simulation method of claim 1, wherein: in the step S1, the control software analyzes the scene and issues the scene to mathematical simulation software, wherein the scene comprises simulation time, simulation beat, constellation parameters, carrier track, antenna parameters and interference parameters, and issues corresponding ephemeris parameters to the mathematical simulation software according to frequency points and channel configuration information reported by the mathematical simulation software.

7. The on-chip simulation-based navigation signal simulation method of claim 1, wherein: in step S5, the mathematical simulation software determines whether the simulation duration is finished, and waits for the FPGA to feed back the next beat ready flag and waits for the next beat ready to start the next beat simulation if the simulation duration is not finished.

8. A navigation signal simulation system based on-chip simulation is characterized in that: the system comprises a simulation control software module and an on-chip simulation module, wherein the on-chip simulation module comprises an SOC FPGA chip, a DA chip and a clock module, the SOC FPGA chip integrates a processor and an FPGA, a mathematical simulation software module runs on the processor, a digital baseband signal generation module runs on the FPGA, the digital baseband signal generation module receives signal input of the clock module and outputs a generated baseband signal to the DA chip, and the simulation control software module runs on the SOC FPGA chip processor or an upper computer; the clock module is connected with an input interface and receives a clock signal; the DA chip is connected with a radio frequency sub-module, the digital signal is converted into an analog baseband signal, the radio frequency sub-module performs up-conversion and power control on the analog baseband signal, and outputs an analog satellite signal, so that the simulation method based on the on-chip simulation navigation signal according to any one of claims 1 to 7 is realized.

9. The on-chip simulation based navigation signal simulation system of claim 8, wherein: the number of the on-chip simulation modules is 1 or more, and the simulation control software module runs in the upper computer and controls 1 or more on-chip simulation modules simultaneously.

10. The on-chip simulation based navigation signal simulation system of claim 8, wherein: the mathematical simulation software module comprises a multi-frequency point unit, a multi-array element unit and a multi-carrier unit; the multi-frequency point unit generates multi-frequency points through navigation message simulation and/or satellite constellation simulation and/or orbit simulation; the multi-array element unit generates multi-array elements through attitude simulation, wherein the attitude simulation at least comprises one of carrier attitude simulation, antenna array element attitude simulation, antenna installation position simulation and antenna pattern simulation; the multi-carrier unit generates a multi-carrier through track simulation, wherein the track simulation comprises multi-carrier position simulation and/or multi-carrier dynamic simulation.

11. The on-chip simulation based navigation signal simulation system of claim 10, wherein: the plurality of mathematical simulation software modules form a signal submodule, the signal submodule sends multi-array metadata to a radio frequency submodule, and the signal submodule corresponds to the radio frequency submodule one to one.

12. The on-chip simulation based navigation signal simulation system of claim 11, wherein: the plurality of mathematical simulation software modules and the radio frequency sub-modules corresponding to the mathematical simulation software modules form 1 or more signal generation board cards, multi-array element navigation signals output by the plurality of signal generation board cards are sent to the power control and synthesis board cards, and the power control and synthesis board cards are provided with a plurality of antenna array elements to broadcast simulation signals in a combined way.

13. The on-chip simulation based navigation signal simulation system of claim 11, wherein: the signal submodule comprises 4 ZYNQ units, the ZYNQ units are signal generating units, mathematical simulation calculating software modules are operated on the ZYNQ units, each calculating module starts up a plurality of calculating processes based on an embedded real-time operating system to perform parallel calculation, and a signal simulation mode is supported and configured, so that combined simulation of multi-frequency point, multi-satellite, multi-antenna, multi-carrier and multi-array element modes is realized.

14. The on-chip simulation based navigation signal simulation system of claim 11, wherein: the simulation system adopts a multi-task concurrent mode, and a mathematical simulation calculation software module is operated on a ZYNQ unit of each signal sub-module; the mathematical simulation calculation software module receives at least one of frequency point parameters, ephemeris parameters, text parameters, track data and antenna parameters, and sends out a plurality of simulated satellite observation data through different DDS channels.

15. The on-chip simulation based navigation signal simulation system of claim 11, wherein: the method for realizing the transmission of the on-chip simulation navigation signal and the communication signal comprises the following steps: employing integrated navigation/communication signals; satellite navigation system signals are used as navigation channels and cyclic shift keying signals are used as communication channels.

16. The on-chip simulation based navigation signal simulation system of claim 15, wherein: a master-slave receiving method based on a Rake receiver is adopted, and the time delay of each path is measured by the master Rake receiver; the energy of the multipath signals is acquired from the Rake receiver using a plurality of parallel correlators and combined according to a maximal ratio combining algorithm.

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