CN115602106B - Array substrate, display panel and display terminal - Google Patents

Abstract

The embodiment of the application discloses an array substrate which comprises a scanning driving circuit and a plurality of pixel units which are arranged in an array, wherein the scanning driving circuit is used for controlling the pixel units to receive data signals for image display. The i-a scanning signal in the plurality of scanning signals is used for controlling the i-a row pixel units to receive the first data signal, and the i+b scanning signal is used for controlling the i+b row pixel units to receive the second data signal. The i-th row pixel unit also receives the first data signal during a first period of time during which the i-th row pixel unit receives the first data signal, and the i-th row pixel unit also receives the second data signal during a second period of time during which the i+b-th row pixel unit receives the second data signal. The image refresh rate can be effectively improved by controlling the preset row of pixel units to share the data signals of the other two rows of pixel units in different periods. The embodiment of the application discloses a display panel and a display terminal comprising the array substrate.

Description

Array substrate, display panel and display terminal

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a display panel and a display terminal.

Background

An Organic Light-Emitting Diode (OLED) display device has many advantages of self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, a viewing angle of nearly 180 degrees, wide use temperature range, capability of realizing flexible display, large-area full-color display, and the like, and is considered as a display device with the most development potential in the industry.

At present, when an OLED display panel displays images, due to the limitation of signal transmission rate, the refresh rate of the OLED display panel has an upper limit, and along with the development of display technology, the size and resolution of the OLED display panel are also larger and larger, so that the requirement of the refresh rate of the panel is also higher and higher, and how to meet the requirement of the large-size and high-resolution OLED display panel on the refresh rate is a problem to be solved.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the embodiment of the application discloses an array substrate, a display panel and a display terminal capable of effectively improving a refresh rate.

An array substrate comprises a scanning driving circuit and a plurality of pixel units which are arranged in an array, wherein the scanning driving circuit is used for outputting a plurality of scanning signals to the pixel units at preset intervals to control the pixel units to receive data signals for image display. The ith-a scanning signal in the plurality of scanning signals is used for controlling the ith-a row pixel units to receive the first data signals, and the (i+b) scanning signal in the plurality of scanning signals is used for controlling the ith+b row pixel units to receive the second data signals, wherein i, a and b are positive integers. In a first time period in the process of receiving the first data signal by the pixel units in the i-a row, the pixel units in the i row also receive the first data signal; the i+b-th row pixel unit also receives the second data signal during a second period of time in the process of receiving the second data signal.

Optionally, when a and b are equal, the pixel unit of the i-th row also receives the first data signal during a first period of time during which the pixel unit of the i-th row receives the first data signal; the i+a-th row pixel unit also receives the second data signal during a second period of time in the process of the i+a-th row pixel unit receiving the second data signal.

Optionally, when a is 1, in a first period of time during which the i-1 th row of pixel units receive the first data signal, the i-1 th row of pixel units also receive the first data signal; the i+1th row pixel unit also receives the second data signal during a second period of time in the process of receiving the second data signal.

Optionally, the first period and the second period are consecutive and have no time overlap, and the total duration of the i-1 row of pixel units receiving the first data signal is equal to the sum of the first period and the second period, and the i+1 row of pixel units receiving the sum of the first period and the second period of the second data signal.

Optionally, the duration of the first period is equal to the duration of the second period.

Optionally, the 1 st row pixel unit to the n th row pixel unit respectively receive the 1 st data signal to the n th data signal, and in a first period of time in the process that the i th row pixel unit receives the i th data signal, the i+a th row pixel unit also receives the i th data signal; in a second period of time during which the i+2a-th row pixel unit receives the i+2a-th data signal, the i+2a-th row pixel unit also receives the i+2a-th data signal, the i-th data signal is used as first data, and the i+2a-th data signal is used as second data, wherein 1 < a < n,1 < i < n, i=2j+1, a=2k+2, and j and K are natural numbers.

Optionally, when a is 1, in a first period of time during which the ith row of pixel cells receive the ith data signal, the (i+1) th row of pixel cells also receive the ith data signal; in a second period of time during which the i+2 th row of pixel units receive the i+2 th data signal, the i+1 th row of pixel units also receive the i+2 th data signal.

Optionally, the first time period and the second time period are consecutive and have no overlapping in time, the total duration of the i-th row of pixel units receiving the i-th data signal is equal to the sum of the first time period and the second time period, the total duration of the i+2-th row of pixel units receiving the i+2-th data signal is equal to the sum of the first time period and the second time period, and the duration of the first time period is equal to the duration of the second time period.

The embodiment of the application also discloses a display panel which comprises a data driving circuit, a time sequence control circuit and the array substrate, wherein the time sequence control circuit is used for outputting clock signals to the data driving circuit and a scanning driving circuit arranged on the array substrate and is used for controlling the data driving circuit and the scanning driving circuit to output data signals and scanning signals to pixel units arranged on the array substrate according to preset time sequences so as to drive the pixel units to display images.

The embodiment of the application also discloses a display terminal which comprises a support frame, a power supply module and the display panel, wherein the power supply module provides power supply voltage for the display panel to display images, and the display panel and the power supply module are fixed on the support frame.

Compared with the prior art, the method has the advantages that the pixel units of the preset row are controlled to respectively receive the data signals for displaying the images of the pixel units of the different two rows in two continuous time periods, so that the image refresh rate can be effectively improved, the pixel units of the preset row receive the data signals of the pixel units of the front and rear adjacent two rows in two continuous time periods for displaying the images, and when the pixel units of the preset row display the images, the display panel displays the images gradually, and the display effect is more uniform.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a display terminal according to an embodiment of the present application;

FIG. 2 is a schematic side view of the display panel of FIG. 1;

FIG. 3 is a schematic diagram of a planar layout structure of the array substrate in the display panel of FIG. 2;

FIG. 4 is a block diagram of the scan driving circuit in FIG. 3;

FIG. 5 is a timing diagram of the control signal output of FIG. 4;

FIG. 6 is a block diagram of a scan driving circuit according to a second embodiment of the present application;

FIG. 7 is a timing diagram of the scan signal output in FIG. 6;

fig. 8 is a timing chart of the scan signals as shown in fig. 6 according to a third embodiment of the present application.

Reference numerals illustrate: the display device includes a display terminal-100, a display panel-10, a power module-20, a support frame-30, a timing control circuit-11, a Data driving circuit-12, a scan driving circuit-13, a display region-10 a, a non-display region-10 b, an array substrate-10 c, a counter substrate-10 d, a display medium layer-10 e, a pixel unit-P, a first direction-F1, a second direction-F2, a clock signal-CLK, a Data line-S, a scan line-G, a Data signal-Data, a shift register unit-SR, a level converting unit-LS, a potential boosting unit-BUF, an enable signal-OE, a start signal-STV, an on signal-VGH, an off signal-VGL, a first period-T1, a second period-T2, a first time-T1, a second time-T2, a third time-T3, a fourth time-T4, a fifth time-T5, a first scan signal-G1, a second scan signal-G2, a third scan signal-G3, a fourth scan signal-G4, and a fourth scan signal-Gn.

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. The drawings illustrate preferred embodiments of the application. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the application may be practiced. The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The term "coupled" as used herein includes both direct and indirect coupling (coupling), unless otherwise indicated. Directional terms, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., in the present application are merely referring to the directions of the attached drawings, and thus, directional terms are used for better, more clear explanation and understanding of the present application, rather than indicating or implying that the apparatus or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be a mechanical connection; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art. It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order.

Furthermore, the terms "comprises," "comprising," "includes," "including," or "having," when used in this specification, are intended to specify the presence of stated features, operations, elements, etc., but do not limit the presence of one or more other features, operations, elements, etc., but are not limited to other features, operations, elements, etc. Furthermore, the terms "comprises" or "comprising" mean that there is a corresponding feature, number, step, operation, element, component, or combination thereof disclosed in the specification, and that there is no intention to exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof. Furthermore, when describing embodiments of the application, use of "may" means "one or more embodiments of the application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a display terminal 100 according to a first embodiment of the present application. The display terminal 100 includes a display panel 10, a power module 20 and a supporting frame 30, wherein the display panel 10 and the power module 20 are fixed on the supporting frame 30, and the power module 20 is disposed on the back of the display panel 10, i.e. the non-display area of the display panel 10. The power module 20 is used for providing power voltage for the display panel 10 to display images, and the support frame 30 provides fixing and protecting functions for the display panel 10 and the power module 20.

Referring to fig. 2, fig. 2 is a schematic side view of the display panel 10 in fig. 1.

As shown in fig. 2, the display panel 10 includes a display area 10a for images and a non-display area 10b. The display area 10a is used for performing image display, and the non-display area 10b is disposed around the display area 10a to provide other auxiliary components or modules, and specifically, the display panel 10 includes an array substrate 10c and an opposite substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the opposite substrate 10 d. In this embodiment, the display medium in the display medium layer is an organic light emitting semiconductor material (Organic Electroluminescence Diode, OLED).

Referring to fig. 3, fig. 3 is a schematic plan layout structure of the array substrate 10c of the display panel 10 in fig. 2. As shown in fig. 3, the array substrate 10c includes a plurality of m×n Pixel units (pixels) P, m Data lines (Data lines) S1 to Sm and n scan lines (Gate lines) G1 to Gn arranged in a matrix, where m and n are natural numbers greater than 1.

The plurality of scan lines G1 to Gn extend along a first direction F1 and are arranged in parallel with each other at a first predetermined distance, the plurality of data lines S1 to Sm extend along a second direction F2 and are arranged in parallel with each other at a second predetermined distance, and the plurality of scan lines G1 to Gn are insulated from the plurality of light-emitting data lines S1 to Sm, wherein the first direction F1 and the second direction F2 are perpendicular to each other.

The display terminal 100 further includes a timing control circuit 11 for driving the pixel units to display an image, a data driving circuit 12, and a scan driving circuit 13 provided in the array substrate 10c corresponding to the non-display region 10b of the display panel 10.

The Data driving circuit 12 is electrically connected to the plurality of Data lines S1 to Sm, and is configured to transmit the Data signal Data for display to the plurality of pixel units P in the form of Data voltages through the plurality of Data lines S1 to Sm.

The scan driving circuit 13 is electrically connected to the plurality of scan lines G1 to Gn, and is configured to output a scan signal Gn through the plurality of scan lines G1 to Gn for controlling when the pixel unit P receives the data signal. The scan driving circuit 13 sequentially outputs scan signals from the plurality of scan lines G1 to Gn in the position arrangement order from the scan lines G1, G2, … …, gn in the scan period.

The timing control circuit 11 is electrically connected to the Data driving circuit 12 and the scan driving circuit 13, and is used for controlling the operation timings of the Data driving circuit 12 and the scan driving circuit 13, that is, outputting corresponding timing control signals to the Data driving circuit 12 and the scan driving circuit 13 so as to control when to output corresponding scan signals Gn and Data signals Data.

In the present embodiment, the circuit elements in the scan driving circuit 13 and the pixel units P in the display panel 10 are fabricated in the array substrate 10c by the same process, i.e. GOA (Gate Driver on Array) technology.

It can be appreciated that the display terminal 100 further includes other auxiliary circuits for jointly completing the display of the image, such as an image receiving processing circuit (Graphics Processing Unit, GPU), a power circuit, etc., which will not be described in detail in this embodiment.

Specifically, the timing control circuit 11 is configured to output the clock signal CLK to the Data driving circuit 12 and the scan driving circuit 13 disposed on the array substrate 10c, and is configured to control the Data driving circuit 12 and the scan driving circuit 13 to output the Data signal Data and the scan signal to the pixel unit P disposed on the array substrate 10c according to a predetermined timing, so as to drive the pixel unit P to perform image display.

Referring to fig. 4, fig. 4 is a block diagram of the scan driving circuit in fig. 3.

As shown in fig. 4, the scan driving circuit 13 includes a plurality of shift register units SR, a plurality of level shift units LS and a plurality of potential boosting units BUF, wherein the plurality of shift register units SR are configured to receive and store a clock signal CLK with a low potential from the timing control circuit 11, transmit the clock signal CLK to the level shift units LS under the control of a start signal STV and an enable signal OE, generate an on signal VGH and an off signal VGL according to the clock signal CLK, and transmit the on signal VGH and the off signal VGL to the potential boosting units BUF, and the potential boosting units BUF are configured to adjust the on signal VGH and the off signal VGL to a predetermined potential and transmit the adjusted on signal VGL to the corresponding pixel units P through the scan lines to control the pixel units P to receive a Data signal Data for image display. The pixel unit P receives the Data signal Data output by the Data driving circuit 12 when the on voltage signal VGH is output to the pixel unit P, and stops receiving the Data signal Data when the off voltage signal VGL is output to the pixel unit P.

The shift registers SR are sequentially cascaded, and the scan signal output by the previous shift register SR is controlled to output the scan signal by the next shift register. And sequentially outputting scanning signals to the pixel units P in a row-by-row cascade mode so as to control each row of pixel units P to be sequentially refreshed according to a preset time sequence.

Referring to fig. 5, fig. 5 is a timing chart of the control signal output in fig. 4.

As shown in fig. 5, after the start signal STV is turned on, the clock signal CLK is transmitted to the level converting unit LS and the potential boosting unit BUF through the shift register unit SR and then outputted to the corresponding scan line to control the pixel unit corresponding to the scan line to receive the Data signal Data.

For example, at the first time t1, the clock signal CLK is at a high level, and is used to control the first row of pixel units P to perform image display. According to the control of the clock signal CLK, the first scan signal G1 is also at a high level at the first time t1, and at this time, the turn-on voltage signal VGH is output to the first row of pixel units P, and the first row of pixel units P starts to receive the Data signal Data at the first time t1 and perform image display.

At the second time t2, the clock signal CLK is at a high level for controlling the second row of pixel cells P to display an image, and the first scan signal G1 becomes at a low level. According to the control of the clock signal CLK, the second scan signal G2 becomes high level at the second time t2, and then outputs the on signal VGH to the second row of pixel units P, and the second row of pixel units P starts to receive the Data signal Data at the second time t2 for displaying the image.

And the pixel units P sequentially perform image display according to the row sequence until the display of the pixel units of the last row is completed, namely one frame of image display is completed.

Referring to fig. 6, fig. 6 is a block diagram of a scan driving circuit according to a second embodiment of the present application. As shown in fig. 6, the scan driving circuit 13 drives a first group of pixel units and a second group of pixel units respectively to display images, wherein the first group of pixel units are pixel units of odd lines, and the second group of pixel units are pixel units of even lines. And respectively outputting corresponding scanning signals to the pixel units of the corresponding rows to control at least two rows of pixel units to receive the same data signals in a preset period so as to display images.

In an exemplary embodiment, the first group of pixel units and the second group of pixel units may be further configured as a combination of other rows of pixel units according to specific needs, which is not limited in the present application.

Referring to fig. 7, fig. 7 is a timing diagram of the scan signal output in fig. 6. As shown in fig. 7, the first group of pixel units is a first row of pixel units, a third row of pixel units, and an n-1 th row of pixel units, i.e., odd-numbered row of pixel units, correspondingly driven by the first scan signal G1, the third scan signal G3, and the n-1 th scan signal Gn-1. The second group of pixel units are second row pixel units, fourth row pixel units and nth row pixel units, namely even row pixel units, correspondingly driven by the second scanning signal G2 and the fourth scanning signals G4 to nth scanning signals Gn.

The scan driving circuit 13 controls two adjacent rows of pixel units to simultaneously turn on and receive the same Data signal Data for image display. For example, in the first period T1, the first scanning signal G1 is controlled to be output to the first row of pixel units to drive the first row of pixel units to receive the first data signal for image display, and the second scanning signal G2 is controlled to be output to the second row of pixel units to drive the second row of pixel units to also receive the first data signal for image display. In the second period T2, the third scanning signals G3 to the third row pixel units are controlled to be output to drive the third row pixel units to receive the second data signals for image display, and the fourth scanning signals G4 to the fourth row pixel units are controlled to be output to drive the fourth row pixel units to also receive the second data signals for image display. And the like, until the nth scanning signal Gn is controlled to be output to the nth row pixel units so as to drive the nth row pixel units to display images, thereby completing the display of one frame of images.

By controlling two adjacent rows of pixel units to display images at the same time, the data consumption of one frame of image can be reduced, and the refreshing time of one frame of image can be shortened, so that the refreshing rate of the image can be improved.

Referring to fig. 8, fig. 8 is a timing chart of outputting the scan signal as shown in fig. 6 according to a third embodiment of the present application.

As shown in fig. 8, the scan driving circuit 13 is configured to output a plurality of scan signals to the pixel units at predetermined intervals to control the pixel units to receive data signals for image display.

The ith-a scanning signal in the plurality of scanning signals is used for controlling the ith-a row pixel units to receive the first data signals, and the (i+b) scanning signal in the plurality of scanning signals is used for controlling the ith+b row pixel units to receive the second data signals, wherein i, a and b are positive integers.

The i-th row pixel unit also receives the first data signal during a first period of time during which the i-th row pixel unit receives the first data signal, and the i-th row pixel unit also receives the second data signal during a second period of time during which the i+b-th row pixel unit receives the second data signal.

For example, when i=5, a=3, and b=2, the row 2 pixel unit receives the first data signal during a first period, the row 5 pixel unit also receives the first data signal during a second period, and the row 5 pixel unit also receives the second data signal during a second period, and the row 5 pixel unit performs image display according to the received first data signal and the second data signal.

In an exemplary embodiment, the total duration of receiving the first data signal by the i-a-th row pixel unit may be a sum of the first time period and the second time period, and the total duration of receiving the second data signal by the i+b-th row pixel unit may be a sum of the first time period and the second time period, which may, of course, be set to other durations according to specific needs.

When a=b, the i-th row pixel unit also receives the first data signal during a first period of time in the process of the i-th row pixel unit receiving the first data signal, and the i-th row pixel unit also receives the second data signal during a second period of time in the process of the i+th row pixel unit receiving the second data signal.

For example, when i=5 and a=2, in a first period of time in the process that the 3 rd row of pixel units receive the first data signal, the 5 th row of pixel units also receive the first data signal, and in a second period of time in the process that the 7 th pixel units receive the second data signal, the 5 th row of pixel units also receive the second data signal, and the 5 th row of pixel units performs image display according to the received first data signal and the second data signal.

When a=b=1, the i-1 th row pixel unit also receives the first data signal for a first period of time during which the i-1 th row pixel unit receives the first data signal; the i+1th row pixel unit also receives the second data signal during a second period of time in the process of receiving the second data signal.

For example, when i=3, in a first period of time during which the row 2 pixel unit receives the first data signal, the row 3 pixel unit also receives the first data signal; in a second period of time in the process that the 4 th row of pixel units receive the second data signals, the 3 rd row of pixel units also receive the second data signals, and the 3 rd row of pixel units perform image display according to the received first data signals and the second data signals.

In an exemplary embodiment, the duration corresponding to the first time period may be equal to the duration corresponding to the second time period, and of course, the first time period and the second time period may also be set to other durations according to specific needs, which is not limited in the present application.

The i+a row pixel unit also receives the i data signal in a first time period in the process of receiving the i data signal by the i row pixel unit, the i+2a row pixel unit also receives the i+2a data signal in a second time period in the process of receiving the i+2a data signal by the i+2a row pixel unit, the i data signal is used as first data, the i+2a data signal is used as second data, wherein 1 < a < n,1 < i < n, i=2j+1, a=2k+2, j and K are natural numbers i=2j+1, and j is a natural number (0, 1, 2, 3 and … …).

For example, when i=5 and a=2, the 5 th data signal is received by the 5 th row pixel unit in a first period, the 5 th data signal is also received by the 7 th row pixel unit, the 9 th data signal is also received by the 7 th row pixel unit in a second period, and the 7 th row pixel unit performs image display according to the received 5 th data signal and 9 th data signal.

When a is 1, the i+1th row pixel unit also receives the i data signal during a first period of time in which the i+2th row pixel unit receives the i+2th data signal, and the i+1th row pixel unit also receives the i+2th data signal during a second period of time in which the i+2th row pixel unit receives the i+2th data signal. The ith row of pixel units are odd rows of pixel units. That is, the scan driving circuit 13 drives the even-numbered row pixel units to respectively receive the data signals for image display of the odd-numbered row pixel units spaced apart by the predetermined distance.

For example, when i=1, the 2 nd row pixel unit also receives the 1 st data signal during a first period of time during which the 1 st row pixel unit receives the 1 st data signal, and the 2 nd row pixel unit also receives the 3 rd data signal during a second period of time during which the 3 rd row pixel unit receives the 3 rd data signal.

The 1 st row of pixel units receives the 1 st data signal during a first period of time, i.e., from a first time t1 to a third time t3, and the 2 nd row of pixel units also receives the 1 st data signal during a second time t2 to a third time t 3. The 3 rd row of pixel units receives the 3 rd data signal in the second time period, namely, the third time t3 to the fifth time t5, and the 2 nd row of pixel units receives the 3 rd data signal in the third time t3 to the fourth time t4, and the 2 nd row of pixel units performs image display according to the received 1 st data signal and the 3 rd data signal as data signals for display.

The pixel units of the preset row are controlled to respectively receive the data signals for displaying the images of the pixel units of different two rows in two continuous time periods, so that the image refresh rate can be effectively improved, the pixel units of the preset row receive the data signals of the pixel units of the front and rear adjacent two rows in two continuous time periods for displaying the images, and when the pixel units of the preset row display the images, the display panel displays the images, and the image display has progressive display effect and is more uniform.

It is to be understood that the application is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.

Claims (4)

1. An array substrate comprises a scanning driving circuit and a plurality of pixel units which are arranged in an array, wherein the scanning driving circuit is used for outputting a plurality of scanning signals to the pixel units at preset intervals in sequence so as to control the pixel units to receive data signals for image display;

the method is characterized in that an i-a scanning signal in the plurality of scanning signals is used for controlling an i-a row pixel unit to receive a first data signal, and an i+b scanning signal in the plurality of scanning signals is used for controlling an i+b row pixel unit to receive a second data signal, wherein i, a and b are positive integers;

the pixel units in the ith row also receive the first data signals in a first time period in the process of receiving the first data signals by the pixel units in the ith row; the pixel units in the ith row also receive the second data signals in a second time period in the process of receiving the second data signals by the pixel units in the ith row;

the 1 st row pixel unit to the n th row pixel unit respectively receive the 1 st data signal to the n th data signal, and the i+a th row pixel unit also receives the i data signal in the first time period in the process that the i th row pixel unit receives the i data signal; in the second period of time during which the i+2a-th row pixel unit receives the i+2a-th data signal, the i+2a-th row pixel unit also receives the i+2a-th data signal, the i-th data signal is used as the first data signal, and the i+2a-th data signal is used as the second data signal, wherein 1 < a < n,1 < i < n, i=2j+1, a=2k+2, j, K is a natural number;

the first time period and the second time period are consecutive and have no time overlapping, the total duration of the i-th row of pixel units receiving the i-th data signal is equal to the sum of the first time period and the second time period, the total duration of the i+2a-th row of pixel units receiving the i+2a-th data signal is equal to the sum of the first time period and the second time period, and the duration of the first time period is equal to the duration of the second time period.

2. The array substrate of claim 1, wherein when a is 1, the i+1th row pixel cell receives the i data signal during the first period of time during which the i row pixel cell receives the i data signal; the i+1th row pixel unit also receives the i+2th data signal during the second period in the process that the i+2th row pixel unit receives the i+2th data signal.

3. A display panel, comprising a data driving circuit, a timing control circuit and an array substrate according to any one of claims 1-2, wherein the timing control circuit is used for outputting a clock signal to the data driving circuit and a scan driving circuit arranged on the array substrate, and is used for controlling the data driving circuit and the scan driving circuit to output a data signal and a scan signal to a pixel unit arranged on the array substrate according to a preset timing sequence so as to drive the pixel unit to display an image.

4. A display terminal, characterized by comprising a support frame, a power supply module and the display panel according to claim 3, wherein the power supply module provides power supply voltage for image display of the display panel, and the display panel and the power supply module are fixed on the support frame.