CN115568007A - Power supply control method, device, system and terminal - Google Patents

Abstract

The application provides a power supply control method, device, system and terminal, and belongs to the technical field of communication. The method comprises the following steps: and respectively controlling power supply of a first processing module and a first storage module in the target chip according to a time interval between a first time period and a second time period, wherein the first time period is a time period for executing a first task, the second time period is a time period for executing a second task, the first storage module is used for storing firmware of the target chip, and the first processing module is used for executing the first task and the second task by accessing the first storage module. The method can respectively control the power supply to the first processing module and the first storage module in the target chip based on the time interval between the time period for executing the first task and the time period for executing the second task, so that the power supply mode with lower power consumption can be flexibly selected based on the size of the time interval, and the power consumption is effectively reduced.

Description

Power supply control method, device, system and terminal

technical field

The present application relates to the technical field of communications, and in particular to a power supply control method, device, system and terminal.

Background technique

Usually, the terminal needs to perform various tasks. For example, the radio frequency processing chip on the terminal needs to wake up to monitor the PDCCH (Physical Downlink Control Channel, Physical Downlink Control Channel) subframe. In order to reduce power consumption, the communication system introduces DRX (Discontinuous Reception, discontinuous reception) technology, UE (User Equipment, user terminal) enters sleep state periodically, and UE does not monitor PDCCH subframe in sleep state, and monitors PDCCH subframe after waking up from sleep state.

However, even with DRX technology, power consumption is still high.

Contents of the invention

Embodiments of the present application provide a power supply control method, device, system, and terminal, which can reduce power consumption. The technical scheme is as follows:

According to an aspect of an embodiment of the present application, a power supply control method is provided, the method comprising:

Control the power supply of the first processing module and the first storage module in the target chip respectively according to the time interval between the first time period and the second time period, wherein the first time period is a time period for executing the first task, so The second time period is a time period for executing the second task, the first storage module is used to store the firmware of the target chip, and the first processing module is used to execute the second task by accessing the first storage module. A task and said second task.

According to another aspect of the embodiments of the present application, a power supply control device is provided, the device comprising:

A control module, configured to respectively control the power supply of the first processing module and the first storage module in the target chip according to the time interval between the first time period and the second time period, wherein the first time period is for executing the first task time period, the second time period is the time period for executing the second task, the first storage module is used to store the firmware of the target chip, and the first processing module is used to access the first memory A module performs the first task and the second task.

According to another aspect of the embodiment of the present application, a power supply control system is provided, including a control module, a first processing module of the target chip, and a first storage module of the target chip:

The control module is configured to respectively control the power supply of the first processing module and the first storage module according to the time interval between the first time period and the second time period, wherein the first time period is the execution The time period of the first task, the second time period is the time period for executing the second task, the first storage module is used to store the firmware of the target chip, and the first processing module is used to access the The first storage module performs the first task and the second task.

According to another aspect of the embodiments of the present application, a control module is provided, the control module includes a processor, and the processor is configured to implement the power supply control method described in the above aspect.

According to another aspect of the embodiments of the present application, a terminal is provided, and the terminal includes the control module described in the above aspect.

The power supply control scheme provided by the embodiment of the present application can control the power supply to the first processing module and the first storage module in the target chip based on the time interval between the time period when the first task is executed and the time period when the second task is executed. Power supply, so that based on the size of the time interval, a power supply mode with less power consumption can be flexibly selected, thereby effectively reducing power consumption.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

Fig. 1 shows a schematic structural diagram of a power supply control system provided by an exemplary embodiment of the present application;

Fig. 2 shows a schematic structural diagram of another power supply control system provided by an exemplary embodiment of the present application;

Fig. 3 shows a schematic structural diagram of another power supply control system provided by an exemplary embodiment of the present application;

Fig. 4 shows a schematic diagram of a baseband processing chip and a radio frequency processing chip provided by an exemplary embodiment of the present application;

Fig. 5 shows a schematic structural diagram of another power supply control system provided by an exemplary embodiment of the present application;

Fig. 6 shows a schematic structural diagram of another power supply control system provided by an exemplary embodiment of the present application;

Fig. 7 shows a schematic structural diagram of another power supply control system provided by an exemplary embodiment of the present application;

Fig. 8 shows a flowchart of a power supply control method provided by an exemplary embodiment of the present application;

Fig. 9 shows a flowchart of another power supply control method provided by an exemplary embodiment of the present application;

Fig. 10 shows a flowchart of another power supply control method provided by an exemplary embodiment of the present application;

Fig. 11 shows a schematic diagram of an SSB and a paging message provided by an exemplary embodiment of the present application;

FIG. 12 shows a schematic diagram of a DRX cycle provided by an exemplary embodiment of the present application;

Fig. 13 shows a schematic diagram of various time periods during power supply in a related art provided by an exemplary embodiment of the present application;

Fig. 14 shows a schematic diagram of various time periods during power supply in another related art provided by an exemplary embodiment of the present application;

Fig. 15 shows a schematic diagram of various time periods during a power supply in an idle state provided by an exemplary embodiment of the present application;

Fig. 16 shows a schematic diagram of various time periods during power supply in another idle state provided by an exemplary embodiment of the present application;

Fig. 17 shows a schematic diagram of various time periods during power supply in a connected state provided by an exemplary embodiment of the present application;

Fig. 18 shows a schematic diagram of various time periods during power supply in another connected state provided by an exemplary embodiment of the present application;

Fig. 19 shows a structural block diagram of a power supply control device provided by an exemplary embodiment of the present application.

detailed description

In order to make the purpose, technical solution and advantages of the present application clearer, the implementation manners of the present application will be further described in detail below in conjunction with the accompanying drawings.

The "at least one" mentioned herein means one or more, and the "multiple" means two or more. "And/or" describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B may indicate: A exists alone, A and B exist simultaneously, and B exists independently. The character "/" generally indicates that the contextual objects are an "or" relationship.

It should be noted that the information (including but not limited to user equipment information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application, All are authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with the relevant laws, regulations and standards of the relevant countries and regions.

FIG. 1 is a schematic structural diagram of a power supply control system provided by an embodiment of the present application. Referring to FIG. 1 , the power supply control system 101 includes a control module 1011 , a first processing module 1012 of a target chip, and a first storage module 1013 of a target chip.

Optionally, the power supply control system is a SOC (System On Chip, system-on-chip), a PCB (Printed Circuit Board, printed circuit board) carrying a chip or a terminal, and the terminal is a mobile phone, a notebook computer, a tablet computer, a smart TV, Various types of equipment such as vehicle-mounted terminals are not limited in this embodiment of the present application.

Referring to FIG. 2 , the control module 1011 can respectively control the power-on or power-off of the first processing module 1012 of the target chip and the first storage module 1013 of the target chip. For the specific process, refer to the following embodiments of the power supply control method.

In the first optional manner, the target chip may be a radio frequency processing chip, and the control module 1011 may be a baseband processing chip. The embodiment of the present application does not limit the types of the target chip and the control module 1011 .

Optionally, referring to FIG. 2 , the power supply control system 101 further includes a power management chip 1014, and the control module 1011 can respectively control the power-on of the first processing module 1012 of the target chip and the first storage module 1013 of the target chip through the power management chip 1014. or power off.

Optionally, referring to FIG. 3 , the target chip is a radio frequency processing chip, the control module 1011 is a baseband processing chip, and the radio frequency processing chip and the baseband processing chip work together to complete wireless communication, that is, the signal received by the power supply control system 101 first passes through the radio frequency front-end chip , After passing through the RF processing chip, it becomes a baseband signal, and then digitally demodulates and decodes through the baseband processing chip to restore the original signal.

Optionally, referring to FIG. 4 , the radio frequency processing chip includes a first storage module, a first processing module, a bus, and the like, and the first storage module and the first processing module are respectively connected to the bus. The first storage module includes a memory, and the first processing module includes a high-speed interface, an analog device, a processor, and the like. The baseband processing chip includes a second storage module, a second processing module, a third storage module, a bus, etc., and the second storage module, the second processing module and the third storage module are respectively connected to the bus. The second storage module includes a first memory, and the first memory is used for storing firmware of the radio frequency processing chip. The third storage module includes a second memory, and the second memory is used for storing firmware of the baseband processing chip. The second processing module includes a high-speed interface, a processor, and the like. In addition, the radio frequency processing chip and the baseband processing chip perform data transmission through a high-speed interface, so that the baseband processing chip processes signals sent by the radio frequency processing chip.

Optionally, referring to FIG. 5, the power management chip 1014 supplies power to the radio frequency processing chip and the baseband processing chip, and the baseband processing chip can also control the power management chip 1014 to supply power to the radio frequency processing chip through the control interface, such as through the power management chip 1014 respectively Controlling the power supply of the first processing module and the first storage module in the radio frequency processing chip.

Wherein, both the radio frequency processing chip and the baseband processing chip need to be loaded with firmware before performing an initialization operation, and can work normally only after the initialization operation is completed.

Wherein, each time the baseband processing chip is powered on, the firmware is loaded into the memory. Optionally, the power supply control system 101 further includes an application processor configured with firmware of a baseband processing chip, and the baseband processing chip loads firmware from the application processor and stores it in a memory of the baseband processing chip.

In addition, the baseband processing chip also loads the firmware of the radio frequency processing chip into the second storage module of the baseband processing chip, and then the radio frequency processing chip reads the firmware from the second storage module of the baseband processing chip through a high-speed interface and loads it into In the memory of the RF processing chip.

Optionally, the baseband processing chip includes multiple storage modules, some of the storage modules store firmware of the baseband processing chip, and other part of the storage modules store firmware of the radio frequency processing chip. For example, the firmware of the baseband processing chip is stored by DDR (Double Data Rate Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory), and the firmware of the radio frequency processing chip is stored by SRAM (Static Random Access Memory, static random access memory). firmware.

Optionally, the power supply control system 101 further includes an application processor configured with firmware of a radio frequency processing chip, and the radio frequency processing chip loads the firmware of the radio frequency processing chip from the application processor.

In the second optional manner, the target chip may be a baseband processing chip. Referring to FIG. 6 , the baseband processing chip includes a control module 1011 , a first processing module 1012 of the baseband processing chip, and a first storage module 1013 of the baseband processing chip. The control module 1011 can respectively control the power on or off of the first processing module 1012 of the baseband processing chip and the first storage module 1013 of the baseband processing chip.

Optionally, referring to FIG. 7 , the power management chip 1014 supplies power to the baseband processing chip. Inside the baseband processing chip, the control module 1011 separately controls the power-on or power-off of the first processing module 1012 of the baseband processing chip and the first storage module 1013 of the baseband processing chip.

Fig. 8 is a flow chart of a power supply control method provided by an embodiment of the present application. The method is executed by the control module, referring to Fig. 8, the method includes:

801. The control module respectively controls the power supply of the first processing module and the first storage module in the target chip according to the time interval between the first time period and the second time period.

Wherein, the target chip may be a baseband processing chip or a radio frequency processing chip, which is not limited in this embodiment of the present application.

In the embodiment of the present application, the target chip executes the first task and the second task, the first time period is the time period for executing the first task, and the second time period is the time period for executing the second task. Wherein, the first task and the second task are two adjacent tasks to be executed by the target chip, and may be any tasks. The first task and the second task may include tasks such as receiving data, sending data, processing data, and switching states, and the embodiment of the present application does not limit the types of tasks. Among them, the first task and the second task may be related, that is, the first task must be performed before the second task is performed, and the first task and the second task may also be two independent tasks, which do not affect each other. The embodiment of the application does not limit the relationship between the first task and the second task.

Optionally, the target chip executes the second task periodically, and the time period for each execution of the second task may be determined according to the period. The second task this time refers to the first second task performed after the first task.

In the embodiment of the present application, the target chip includes a first processing module and a first storage module. The first storage module is used to store the firmware of the target chip, and the first processing module is used to execute the first task and the second task by accessing the first storage module.

In the embodiment of the present application, the second task is executed after the first task, and the step of determining the time interval occurs after the first task is executed and before the second task is executed. That is, the target chip executes the first task, and the control module can determine the time period for executing the first task, that is, the first time period. Moreover, although the target chip has not yet executed the second task, the control module can determine the pre-configured time period for performing the second task, that is, the second time period. The control module determines the second time period based on the first time period and the second time period. The time interval between the first time period and the second time period.

The target chip can only work normally when it is powered on, that is, the target chip can execute the first task and the second task only when it is powered on. After the target chip executes the first task, it will execute the second task after a period of time, then in the time interval between the first time period and the second time period, if the first processing module and the The power supply of the first storage module may consume power and cause certain power consumption. If the power supply for the first storage module in the target chip is stopped, although the power can be saved within this time interval, when the second task is performed, the power supply for the first storage module in the target chip needs to be powered again. Afterwards, the firmware needs to be reloaded to the first storage module and initialized, and this process will also cause certain power consumption and time delay. Therefore, the control module can respectively control the power supply to the first processing module and the first storage module according to the length of the time interval between the first time period and the second time period.

In the embodiment of the present application, based on the time interval between the time period for executing the first task and the time period for executing the second task, the power supplies to the first processing module and the first storage module in the target chip are respectively controlled, so that Based on the size of the time interval, a power supply mode with less power consumption can be flexibly selected, so as to effectively reduce power consumption while taking time delay into consideration.

On the basis of the above embodiments, different power supply modes may be adopted based on the difference in the time interval, and the following embodiments will describe this process in detail.

FIG. 9 is a flow chart of another power supply control method provided by an embodiment of the present application. The method is executed by the control module, and the control module can respectively control the power supply to the first processing module and the first storage module based on the difference of the time interval between the first time period and the second time period. Referring to Figure 9, the method includes:

901. The control module keeps supplying power to the first processing module and the first storage module when the time interval is less than the first threshold.

In the embodiment of the present application, if power is supplied to the first processing module and the first storage module, power may be consumed, resulting in certain power consumption. If the power supply to the first processing module and the first storage module is stopped, after the power supply is restored again, both the first processing module and the first storage module will cause a certain amount of power consumption, for example, the target chip needs to load the The firmware to the first processing module also needs to load the firmware of the target chip to the first storage module, so that the target chip can perform initialization operations based on the firmware loaded in the first storage module, and can only work normally and perform tasks after the initialization operation is completed.

For this reason, the control module sets a first threshold, and it can be considered that when the time interval is smaller than the first threshold, the power consumption caused by powering the first processing module and the first storage module is relatively small. Therefore, power to the first processing module and the first storage module can be maintained during the time interval. In this way, when the second time period arrives, the target chip does not need to restart the first processing module and the first storage module, and does not need to reload firmware, and the initialization operation of the target chip is relatively simple, which can effectively save power consumption.

Optionally, the first threshold is 20 milliseconds, that is, the control module keeps supplying power to the first processing module and the first storage module when the time interval is less than 20 milliseconds.

902. When the time interval is not less than the first threshold and is less than the second threshold, the control module stops supplying power to the first processing module, and keeps supplying power to the first storage module.

In the embodiment of the present application, if power is supplied to the first processing module and the first storage module, power may be consumed, resulting in certain power consumption. If the power supply to the first processing module is stopped and the power supply to the first storage module is kept, then after the power supply to the first processing module is restored again, the target chip does not need to load the firmware of the target chip to the first storage module, nor does it need to perform an initialization operation, And save a certain amount of power consumption.

For this reason, the control module sets a second threshold. It can be considered that when the time interval is not less than the first threshold and is smaller than the second threshold, the power consumption caused by supplying power to the first processing module is relatively large, and then the second threshold is stopped. A processing module is powered to reduce power consumption. The power consumption caused by maintaining power supply to the first storage module is less than the power consumption caused by the target chip loading the firmware of the target chip to the first storage module and performing an initialization operation. Therefore, in order to reduce power consumption, the power supply to the first storage module may be kept during the time interval. In this way, when the second time period is reached, the power supply to the first processing module is resumed, and the target chip loads the firmware required for the operation of the first processing module to the first processing module, without reloading the firmware of the target chip to the first memory module, and the initialization operation of the target chip will be relatively simple, which can effectively save power consumption.

Optionally, the second threshold is 40 milliseconds, that is, the control module stops supplying power to the first processing module and keeps supplying power to the first storage module when the time interval falls within the range of 20 milliseconds to 40 milliseconds.

Optionally, if the power supply to the first processing module is to be stopped, and then the power supply to the first processing module is resumed, a first time delay will be generated, and the first threshold set in the embodiment of the present application may be based on the first time delay Sure. For example, the first threshold is greater than the first delay, so as to ensure that the power supply to the first processing module is maintained when the time interval is less than the first threshold, and when the time interval is not less than the first threshold, it may be It is ensured that the time interval is greater than the first time delay, that is, the power supply to the first processing module is resumed after the power supply to the first processing module is stopped, so that the second task can be executed in time.

903. The control module stops supplying power to the first processing module and the first storage module when the time interval is not less than the second threshold.

In the embodiment of the present application, it can be considered that when the time interval is not less than the second threshold, the power consumption caused by maintaining power supply to the first processing module is greater than the target chip loading the firmware required for the operation of the first processing module to the first processing module. The power consumption caused by the processing module and the power consumption caused by maintaining the power supply to the first storage module are also greater than the power consumption caused by reloading the firmware of the target chip to the first storage module and performing an initialization operation. Therefore, in order to reduce power consumption, the power supply to the first processing module and the first storage module may be stopped within the time interval. In this way, when the second time period arrives, the target chip loads the firmware required for the operation of the first processing module to the first processing module, loads the firmware of the target chip to the first storage module and performs an initialization operation, resulting in less power consumption than maintaining the target chip. The power consumption caused by the power supply of the first storage module and the first processing module can effectively save power consumption.

Optionally, when the time interval is not less than the second threshold, the control module first loads the data stored in the first storage module to the second storage module, and then stops supplying power to the first storage module, so that even the first storage module When the power supply of the module is stopped, the data stored in the first storage module disappears, and the above-mentioned stored data can also be reloaded through the second storage module later. Wherein, the second storage module may be inside the target chip or outside the target chip, which is not limited in this embodiment of the present application.

For example, the second memory module is located outside the target chip. The second storage storage module may be DDR, or other types of storage modules. Therefore, even if the power supply to the first storage module is stopped, the second storage module can keep the power supply, and the data in the second storage module will not be lost.

Optionally, after the power supply to the first storage module is restored, the data of the second storage module is loaded to the first storage module, and the data stored before the first storage module is powered off can be reloaded to the first storage module, avoiding the second Data stored in a storage module is lost.

Optionally, the second threshold is 40 milliseconds, that is, the control module stops supplying power to the first processing module and the first storage module when the time interval is greater than 40 milliseconds.

Optionally, if the power supply to the first storage module is to be stopped, and then the power supply to the first storage module is resumed, a second time delay will be generated, and the second threshold set in the embodiment of the present application may be based on the second time delay Sure. For example, the second threshold is greater than the second delay, so as to ensure that the power supply to the first storage module is maintained when the time interval is less than the second threshold, and when the time interval is not less than the second threshold, it can be It is ensured that the time interval is greater than the second time delay, that is, the power supply to the first storage module is resumed after the power supply to the first storage module is stopped, and the second task can also be executed in time.

In the embodiment of the present application, after the first time period of executing the first task, the control module based on the time interval between the time period of executing the first task and the time period of executing the second task and the first threshold and the second threshold , respectively controlling the power supply to the first processing module and the first storage module. If the time interval is less than the first threshold, the control module keeps powering the first processing module and the first storage module. When the time interval is not less than the first threshold and is less than the second threshold, stop supplying power to the first processing module and keep supplying power to the first storage module. When the time interval is not less than the second threshold, the control module stops supplying power to the first processing module and the first storage module. In this way, based on the time interval and the first threshold and the second threshold, a power supply mode with less power consumption can be flexibly selected, thereby effectively reducing power consumption.

On the basis of the above embodiments, the target chip may include a radio frequency processing chip, and the following embodiments will illustrate that the target chip is a radio frequency processing chip.

Fig. 10 is a flow chart of another power supply control method provided by an embodiment of the present application. In this embodiment of the present application, the target chip is an example of a radio frequency processing chip, and the radio frequency processing chip includes a first storage module and a first processing module. The method is executed by the baseband processing chip, and the baseband processing chip can respectively control the power supply to the first processing module and the first storage module based on the difference in the time interval between the first time period and the second time period, as shown in FIG. 10 , the Methods include:

1001. The baseband processing chip keeps supplying power to the first processing module and the first storage module when the time interval is smaller than a first threshold.

In the process of wireless communication in the embodiment of the present application, the radio frequency processing chip sends and receives signals. However, in order to reduce power consumption, the radio frequency processing chip does not always transmit and receive signals, but enters the sleep state periodically, and does not transmit and receive signals in the sleep state, and after the radio frequency processing chip wakes up from the sleep state, The signal can be sent and received, and before the signal is sent and received, an SSB (Synchronization Signal Block, synchronization signal block) needs to be received, so as to perform pre-synchronization based on the received SSB.

For this reason, the communication system introduces DRX (Discontinuous Reception, discontinuous reception) technology, and the radio frequency processing chip enters the dormant state periodically, and the radio frequency processing chip does not monitor the PDCCH subframe in the dormant state. Monitor the PDCCH subframe. DRX is further divided into an idle state and a connected state.

The DRX mechanism in the idle state is a paging mechanism, and the radio frequency processing chip in the idle state can wake up periodically according to the DRX cycle and receive paging messages. Referring to Figure 11, the DRX cycle is 1.28s (seconds), then the RF processing chip will wake up every 1.28s and receive paging messages, and in the first DRX cycle, the RF processing chip will wake up in advance and receive SSB.

Correspondingly, the first task is to receive the synchronization signal block SSB, and when the radio frequency processing chip is in an idle state, the second task is to receive the paging message.

When the radio frequency processing chip is in the connected state, see Figure 12. The DRX cycle includes a wake-up phase and a sleep phase. In the sleep phase, the radio frequency processing chip is in a sleep state, and the radio frequency processing chip does not monitor the PDCCH subframe, but wakes up from the sleep state. After entering the wake-up stage, the radio frequency processing chip monitors the PDCCH subframe again, and the longer the sleep state lasts, the lower the power consumption of the radio frequency processing chip is. Correspondingly, when the radio frequency processing chip is in the connection state, the first task is to receive the SSB, and the second task is to switch from the sleep state to the wake-up state.

In the embodiment of the present application, the first task is to receive the SSB, and the first time period is the time period for the radio frequency processing chip to receive the SSB.

Wherein, the radio frequency processing chip includes a first storage module, and the first storage module is used for loading firmware of the radio frequency processing chip. When the baseband processing chip stops supplying power to the first storage module, the data in the first storage module will disappear. Therefore, after the baseband processing chip resumes supplying power to the first storage module, the firmware of the radio frequency processing chip needs to be reloaded and initialized. The radio frequency processing chip also includes a first processing module. After the power supply to the first processing module is stopped, and the power supply is restored again, the first processing module will also cause a certain amount of power consumption. For example, the radio frequency processing chip needs to load the firmware required for the operation of the first processing module. to the first processing module. When the time interval is less than the first threshold, the power consumption caused by powering the first processing module and the first storage module is relatively small. Therefore, in order to reduce power consumption, the power supply to the first processing module and the first storage module can be kept during the time interval. In this way, when the time period for receiving the paging message is reached in the idle state, or the time period for switching from the sleep state to the wake-up state is reached in the connected state, the radio frequency processing chip does not need to reload the firmware required for the operation of the first processing module, There is also no need to reload the firmware of the radio frequency processing chip, and the initialization operation is relatively simple, which can effectively save power consumption.

Optionally, the first threshold is 20 milliseconds, that is, the baseband processing chip keeps supplying power to the first processing module and the first storage module when the time interval is less than 20 milliseconds.

1002. The baseband processing chip stops supplying power to the first processing module and keeps supplying power to the first storage module when the time interval is not less than the first threshold and is less than the second threshold.

The radio frequency processing chip also includes a first processing module, and the first processing module includes a high-speed interface, an analog device, a processor, and the like. If the time interval is not less than the first threshold and is less than the second threshold, after the first time period, the baseband processing chip keeps supplying power to the first storage module and stops supplying power to the first processing module.

When the time interval is not less than the first threshold and is less than the second threshold, the power consumption caused by supplying power to the first processing module is relatively large, and the power supply to the first processing module is stopped to reduce power consumption. The power consumption caused by maintaining power supply to the first storage module is less than the power consumption caused by the radio frequency processing chip loading the firmware of the radio frequency processing chip to the first storage module and performing an initialization operation. Therefore, in order to reduce power consumption, the power supply to the first storage module may be kept during the time interval. In this way, when the time period for receiving the paging message is reached in the idle state, or the time period for switching from the dormant state to the wake-up state is reached in the connected state, the power supply to the first processing module is resumed, and the radio frequency processing chip loads the first processing module. The firmware required for module operation can be transferred to the first processing module, and there is no need to reload the firmware of the radio frequency processing chip to the first storage module, and the initialization operation of the radio frequency processing chip will be relatively simple. Therefore, when the time interval is not less than the first threshold and is less than the second threshold, the power supply to the first storage module is kept, but the power supply to the first processing module is stopped, which can effectively reduce power consumption.

Optionally, the second threshold is 40 milliseconds, that is, the baseband processing chip stops supplying power to the first processing module and keeps supplying power to the first storage module when the time interval falls within the range of 20 milliseconds to 40 milliseconds.

It should be noted that, in the embodiment of the present application, during the execution of the above step 1001 or 1002, the power management chip keeps supplying power to the radio frequency processing chip, but the radio frequency processing chip can control to stop supplying power to a certain module. For example, when step 1002 is executed, the power management chip still supplies power to the radio frequency processing chip, but inside the radio frequency processing chip, the power supply to the first processing module is stopped.

1003. The baseband processing chip stops supplying power to the first processing module and the first storage module when the time interval is not less than the second threshold.

Wherein, when the time interval is not less than the second threshold, the power consumption caused by maintaining power supply to the first processing module is greater than that caused by the radio frequency processing chip loading the firmware required for the operation of the first processing module to the first processing module. Power consumption, and the power consumption caused by maintaining power supply to the first storage module is also greater than the power consumption caused by reloading the firmware of the radio frequency processing chip to the first storage module and performing initialization operations. Therefore, in order to reduce power consumption, power supply to the first storage module and the first processing module may be stopped within the time interval. In this way, when the time period for receiving the paging message is reached in the idle state, or the time period for switching from the dormant state to the wake-up state is reached in the connected state, the radio frequency processing chip loads the firmware required for the operation of the first processing module to the second A processing module loads the firmware of the radio frequency processing chip to the first storage module and performs an initialization operation, resulting in less power consumption than powering the first storage module and the first processing module, which can effectively save power consumption.

Optionally, the second threshold is 40 milliseconds, that is, the baseband processing chip stops supplying power to the first processing module and the first storage module when the time interval is greater than 40 milliseconds.

It should be noted that the baseband processing chip executes steps 1001-1003 of the above embodiment, and when step 1003 is executed, the baseband processing chip controls the power management chip to keep supplying power to the radio frequency processing chip after the radio frequency processing chip receives the SSB, And the radio frequency processing chip is controlled to stop supplying power to the first storage module and the first processing module.

In the embodiment of this application, the baseband processing chip may be based on the time interval between the time period for receiving SSB in idle state and the time period for receiving paging message, or the time period for receiving SSB in connected state and switching from sleep state to wake-up The time interval between the time periods of the state controls the power supply to the first storage module and the first processing module in the radio frequency processing chip respectively, which can effectively reduce the power consumption of the radio frequency processing chip.

It should be noted that the above embodiments take the power supply of the radio frequency processing chip controlled by the baseband processing chip as an example, but in practical applications, any chip may control the power supply of the radio frequency processing chip, which is not limited in this embodiment of the present application.

The following describes the workflow in various situations:

Related technologies: Stop power supply after the radio frequency processing chip performs tasks:

Figure 13 shows the processor voltage, processor current, high-speed interface current and analog circuit current of the radio frequency processing chip. These parameters can reflect the power consumption of the radio frequency processing chip.

Referring to Fig. 13, after starting to supply power to the radio frequency processing chip, the voltage of the processor rises, the current also rises, and the current of the high-speed interface rises, and the preparation work is carried out, and the firmware of the radio frequency processing chip is loaded through the high-speed interface. After loading, the high-speed interface current drops to 0, and the initialization operation starts. Then the RF processing chip receives the downlink signal. At this time, the high-speed interface current, processor current and analog circuit current all increase. After receiving the downlink data, the analog device enters the standby state. At this time, except for the RF processing chip processor current, the rest The current drops to 0. Finally, the power supply for the RF processing chip is stopped. The power-off process can be divided into internal power-off and power-off. Internal power-off means that only one or more modules of the RF processing chip are finally powered off. At this time, the processor still has voltage and the power supply Power off refers to stop supplying power to the entire RF processing chip, and the processor voltage is 0 at this time.

On the basis of Figure 13, see Figure 14 for the processor current and high-speed interface current in each time period, where T1 is the time from the start of power supply to the radio frequency processing chip to the high-speed interface, about 1ms (milliseconds), T2 is the time for high-speed signal preparation and loading the firmware of the RF processing chip, about 2.5ms, T3 is the time for initialization operation, about 5.5ms, T4 is the time for the RF processing chip to receive downlink signals, and T5 is the time for storing signals , about 3ms, T6 is the time for internal power-off after receiving the power-off signal, after T6, stop supplying power to the entire RF processing chip. T1+T2+T3=9ms, that is, it takes 9ms from the start of powering the RF processing chip to the normal start of the RF processing chip, and it takes about 3ms from the end of the RF processing chip to the internal power off.

However, the method provided by the embodiment of the present application is based on the time interval between the time period for receiving SSB in the idle state and the time period for receiving the paging message, or the time period for receiving the SSB in the connected state and switching from the sleep state to the wake-up state The time intervals between the time periods respectively control the power supply to the first storage module and the first processing module in the radio frequency processing chip. Various situations provided by the embodiments of the present application are described below.

Case 1: The RF processing chip is idle and remains powered after receiving SSB:

Referring to FIG. 15 , the time period T1 is the time from the start of power supply to the radio frequency processing chip and the preparation for the high-speed interface. During the time period T1, the current of the processor rises. In the T2 time period, the high-speed interface prepares and loads the firmware of the RF processing chip, and the current of the high-speed interface rises. In the time period T3, the initialization operation is performed, and at this time, the current of the high-speed interface drops to 0, but the current of the processor still exists. In the T4 time period, the radio frequency processing chip receives the SSB, and at this time, the current of the high-speed interface and the current of the processor both rise. After receiving the SSB, the signal is stored in the T5 time period, and only the processor current is available at this time. When the time interval between the time period of receiving SSB and the time period of receiving paging message in the idle state is less than the first threshold, keep supplying power to the first storage module and the first processing module in the radio frequency processing chip during the T6 time period , there is still processor current at this time, but the processor current is lower at this time. Therefore, before the time period for receiving the paging message, that is, in the subsequent T3 time period, only a simple initialization operation is required without reloading the firmware of the radio frequency processing chip. At this time, the processor current rises, and the high-speed interface current remains is 0. In the time period T7, the radio frequency processing chip receives the paging message, and at this time, the current of the high-speed interface and the current of the processor both rise. After the time period T7, the received signal is stored, at this time the high-speed interface current is 0, but the processor current still exists. After the storage is completed, the power supply to the radio frequency processing chip is stopped.

The second case: the RF processing chip is in an idle state and stops supplying power after receiving SSB:

Referring to FIG. 16 , the time period T1 is the time from the start of power supply to the radio frequency processing chip and the preparation for the high-speed interface. During the time period T1, the current of the processor rises. In the T2 time period, the high-speed interface prepares and loads the firmware of the RF processing chip, and the current of the high-speed interface rises. In the time period T3, the initialization operation is performed, and at this time, the current of the high-speed interface drops to 0, but the current of the processor still exists. In the T4 time period, the radio frequency processing chip receives the SSB, and at this time, the current of the high-speed interface and the current of the processor both rise. After receiving the SSB, the signal is stored in the T5 time period, and only the processor current is available at this time. When the time interval between the time period of receiving the SSB and the time period of receiving the paging message in the idle state is not less than the second threshold, the first storage module and the first processing module in the radio frequency processing chip are stopped in the T6 time period Therefore, before the time period of receiving the paging message, that is, in the time period T2, the firmware of the radio frequency processing chip needs to be reloaded. At this time, both the processor current and the high-speed interface current rise. In the time period T3, the initialization operation is performed, and at this time, the current of the high-speed interface drops to 0, but the current of the processor still exists. In the time period T7, the radio frequency processing chip receives the paging message, and at this time, the current of the high-speed interface and the current of the processor both rise. After the time period T7, the power supply to the first storage module and the first processing module in the radio frequency processing chip is stopped.

The third case: the RF processing chip is in the connected state and keeps power supply after receiving the SSB:

Referring to FIG. 17 , the time period T1 is the time from the start of power supply to the radio frequency processing chip and the preparation for the high-speed interface. During the time period T1, the current of the processor rises. In the T2 time period, the high-speed interface prepares and loads the firmware of the RF processing chip, and the current of the high-speed interface rises. In the time period T3, the initialization operation is performed, and at this time, the current of the high-speed interface drops to 0, but the current of the processor still exists. In the T4 time period, the radio frequency processing chip receives the SSB, and at this time, the current of the high-speed interface and the current of the processor both rise. After receiving the SSB, the signal is stored in the T5 time period, and only the processor current is available at this time. When the time interval between the time period of receiving SSB in the connected state and the time period of switching from the sleep state to the wake-up state is less than the first threshold, the first memory module and the first memory module in the radio frequency processing chip remain in the T6 time period. The processing module supplies power, and there is still processor current at this time, but the processor current is low at this time. Therefore, before switching from the dormant state to the wake-up state, that is, during the T3 time period, only a simple initialization operation is required without reloading the firmware of the RF processing chip. At this time, the processor current rises, and the high-speed interface current remains the same. is 0. In the T7 time period, the radio frequency processing chip switches from the sleep state to the wake-up state, and starts to monitor the PDCCH subframe, at this time, the current of the high-speed interface and the current of the processor both rise. After the time period T7, the received signal is stored, at this time the high-speed interface current is 0, but the processor current still exists. After the storage is completed, the power supply to the first storage module and the first processing module in the radio frequency processing chip is stopped.

The fourth case: the RF processing chip is in the connected state, and the power supply is stopped after receiving the SSB:

Referring to FIG. 18 , the time period T1 is the time from the start of power supply to the radio frequency processing chip and the preparation for the high-speed interface. During the time period T1, the current of the processor rises. In the T2 time period, the high-speed interface prepares and loads the firmware of the RF processing chip, and the current of the high-speed interface rises. In the time period T3, the initialization operation is performed, and at this time, the current of the high-speed interface drops to 0, but the current of the processor still exists. In the T4 time period, the radio frequency processing chip receives the SSB, and at this time, the current of the high-speed interface and the current of the processor both rise. After receiving the SSB, the signal is stored in the T5 time period, and only the processor current is available at this time. When the time interval between the time period for receiving SSB in the connected state and the time period for switching from the dormant state to the wake-up state is not less than the second threshold, the first memory module and the second memory module in the radio frequency processing chip are stopped in the T6 time period. A processing module supplies power. Therefore, before switching from the dormant state to the wake-up state, that is, during the T2 time period, the firmware of the radio frequency processing chip needs to be reloaded. At this time, both the processor current and the high-speed interface current increase. In the time period T3, the initialization operation is performed, and at this time, the current of the high-speed interface drops to 0, but the current of the processor still exists. In the T7 time period, the radio frequency processing chip switches from the sleep state to the wake-up state, and starts to monitor the PDCCH subframe, and at this time, the high-speed interface current and the processor current both rise. After the time period T7, the power supply to the first storage module and the first processing module in the radio frequency processing chip is stopped.

Using the method of the embodiment of the present application, when the radio frequency processing chip is in an idle state, experiments are carried out on the two power supply modes of maintaining power supply and stopping power supply respectively, and the amount of power consumption caused by the two power supply modes can be obtained. On the basis of Figure 15 and Figure 16, when the above two power supply methods are used respectively, the power consumption of the radio frequency processing chip in the T5, T6 and T2 time periods is shown in Table 1.

Table 1

Power supply T5 T6 T2 stay powered 15 6 0 stop power supply 15 0 15

See Table 1. In the case of maintaining the power supply, the power consumption in the T5 time period is 15, and in the T6 time period, the power consumption caused by maintaining the power supply is 6. In the case of maintaining the power supply, there is no need to reload the RF processing chip. firmware, so the power consumption in the T2 time period is 0. When the power supply is stopped, the power consumption in the T5 time period is 15, and in the T6 time period when the power supply is stopped, the power consumption in the T6 time period is 0. In the T2 time period, the power consumption caused by reloading the firmware of the RF processing chip is 15. T5 is 3ms, T6 is the specific power supply or stop power supply time period, T6 is represented by x, T2 is 2.5ms, therefore, in the time period of T5, T6 and T2, the power consumption caused by stopping power supply is the same as that caused by maintaining power supply If the power consumption difference is 37.5-6x, the power supply to the radio frequency processing chip can be controlled according to the total time length of the T5, T6 and T2 time periods, thereby optimizing the power consumption of the radio frequency processing chip to the greatest extent.

The above-mentioned embodiments are only described by taking the radio frequency processing chip as an example, and for the baseband processing chip or other related chips, the method provided by the above-mentioned embodiment can also be used for power supply control, and the specific process will not be repeated.

It should be noted that, when the target chip is a baseband processing chip, the baseband processing chip further includes a control module. The control module can adopt the methods provided in the above embodiments to respectively control the power supply of the first processing module and the first storage module in the baseband processing chip according to the time interval between the first time period and the second time period.

Optionally, the first time period is the time period when the baseband processing chip processes the SSB sent by the radio frequency processing chip, and the second time period is the time period when the baseband processing chip processes the paging message sent by the radio frequency processing chip.

Optionally, the first storage module in the baseband processing chip is used to store firmware of the radio frequency processing chip, and the second storage module is used to store firmware of the baseband processing chip. If power is supplied to the first storage module, power may be consumed, resulting in a certain power consumption. If the power supply is stopped for the first storage module, after the power supply is restored again, the baseband processing chip needs to reload the firmware of the radio frequency processing chip to the first storage module, so that the radio frequency processing chip loads the firmware of the radio frequency processing chip from the first storage module and Perform initialization operations. Therefore, when the time interval between the first time period and the second time period is not less than the second threshold, after the control module loads the data stored in the first storage module to the second storage module, it stops storing Module power supply. After restoring the power supply to the first storage module, the control module loads the data of the second storage module to the first storage module, so that the radio frequency processing chip loads the firmware of the radio frequency processing chip from the first storage module, and performs an initialization operation.

It should be noted that, during the process of the control module respectively controlling the power supply of the first processing module and the first storage module in the baseband processing chip according to the time interval between the first time period and the second time period, the power management chip remains as the baseband The processing chip supplies power, but the baseband processing chip can be controlled to stop supplying power to the first storage module and the first processing module.

The following are device embodiments of the present application, which can be used to implement the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

Please refer to FIG. 19 , which shows a structural block diagram of a power supply control device provided by an exemplary embodiment of the present application. The power supply control device includes:

The control module 1901 is configured to respectively control the power supply of the first processing module and the first storage module in the target chip according to the time interval between the first time period and the second time period, wherein the first time period is the period for executing the first task The second time period is the time period for executing the second task, the first storage module is used to store the firmware of the target chip, and the first processing module is used to execute the first task and the second task by accessing the first storage module.

In a possible implementation manner, the target chip includes a radio frequency processing chip.

In a possible implementation, the first task is to receive the synchronization signal block SSB, and when the radio frequency processing chip is in an idle state, the second task is to receive a paging message; or, when the radio frequency processing chip is in a connected state Next, the second task is to switch from the sleep state to the wake-up state.

In a possible implementation manner, the control module 1901 is a baseband processing chip.

In a possible implementation manner, the target chip includes a baseband processing chip.

In a possible implementation manner, the baseband processing chip includes a control module 1901 .

In a possible implementation manner, the control module 1901 includes:

A first control unit, configured to keep power supply to the first processing module and the first storage module when the time interval is less than the first threshold;

Alternatively, the second control unit is configured to stop power supply to the first processing module and keep power supply to the first storage module when the time interval is not less than the first threshold and is less than the second threshold;

Alternatively, the third control unit is configured to stop supplying power to the first processing module and the first storage module when the time interval is not less than the second threshold.

In a possible implementation manner, the first threshold is 20 milliseconds, and the second threshold is 40 milliseconds.

In a possible implementation manner, the third control unit is configured to:

When the time interval is not less than the second threshold, after the data stored in the first storage module is loaded to the second storage module, power supply to the first storage module is stopped.

In a possible implementation manner, the device further includes:

The loading module is configured to load the data of the second storage module to the first storage module after the power supply to the first storage module is resumed.

It should be noted that, when the power supply control device provided by the above-mentioned embodiments realizes its functions, it only uses the division of the above-mentioned functional modules for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional modules according to needs , that is, divide the internal structure of the terminal into different functional modules, so as to complete all or part of the functions described above. In addition, the power supply control device and the power supply control method embodiments provided in the above embodiments belong to the same idea, and the specific implementation process thereof is detailed in the method embodiments, and will not be repeated here.

The present application also provides a power supply control system, including a control module, a first processing module of the target chip, and a first storage module of the target chip:

A control module, configured to respectively control the power supply of the first processing module and the first storage module in the target chip according to the time interval between the first time period and the second time period, wherein the first time period is the time for executing the first task The second time period is a time period for executing the second task, the first storage module is used to store the firmware of the target chip, and the first processing module is used to execute the first task and the second task by accessing the first storage module.

Optionally, the power supply control system further includes a power management chip.

Optionally, the control module is configured to control the power supply of the first processing module of the target chip and the first storage module of the target chip by controlling the power management chip.

Optionally, the target chip includes a radio frequency processing chip.

Optionally, the first task is to receive a synchronization signal block SSB, and when the radio frequency processing chip is in an idle state, the second task is to receive a paging message;

Alternatively, when the radio frequency processing chip is in the connection state, the second task is to switch from the sleep state to the wake-up state.

Optionally, the control module is a baseband processing chip.

Optionally, the target chip includes a baseband processing chip.

Optionally, the baseband processing chip includes a control module.

Wherein, the specific functions of the control module, the target chip and the power management chip are as shown in the embodiment of the above-mentioned power supply control method, and will not be repeated here.

The present application also provides a control module, the control module includes a processor, and the processor is configured to implement the power supply control method shown in the above embodiments.

The present application also provides a terminal, which includes the control module shown in the above embodiments.

The serial numbers of the above embodiments of the present application are for description only, and do not represent the advantages and disadvantages of the embodiments.

Those of ordinary skill in the art can understand that all or part of the steps in the method for implementing the above-mentioned embodiments can be completed by hardware, and can also be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium , the storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, and the like. The above are only optional embodiments of the application, and are not intended to limit the application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the application shall be included in the protection of the application. within range.

Claims (21)

1. A power supply control method, characterized in that the method comprises:

the method comprises the steps of respectively controlling power supply of a first processing module and a first storage module in a target chip according to a time interval between a first time period and a second time period, wherein the first time period is a time period for executing a first task, the second time period is a time period for executing a second task, the first storage module is used for storing firmware of the target chip, and the first processing module is used for executing the first task and the second task by accessing the first storage module.

2. The method of claim 1, wherein the target chip comprises a radio frequency processing chip.

3. The method of claim 2, wherein the first task is receiving a Synchronization Signal Block (SSB);

under the condition that the radio frequency processing chip is in an idle state, the second task is to receive a paging message;

or, the second task is switched from a sleep state to an awake state when the radio frequency processing chip is in a connected state.

4. The method of claim 2, wherein controlling the power supply of the first processing module and the first storage module in the target chip according to the time interval between the first time period and the second time period comprises:

and the baseband processing chip respectively controls the power supply of the first processing module and the first storage module in the radio frequency processing chip according to the time interval.

5. The method of claim 1, wherein the target chip comprises a baseband processing chip.

6. The method of claim 5, wherein the baseband processing chip comprises a control module, and wherein the controlling the power supply of the first processing module and the first storage module in the target chip according to the time interval between the first time period and the second time period comprises:

and the control module respectively controls the power supply of the first processing module and the first storage module in the baseband processing chip according to the time interval.

7. The method of claim 1, wherein the controlling the power supply of the first processing module and the first storage module in the target chip according to the time interval between the first time period and the second time period comprises:

in the event that the time interval is less than a first threshold, maintaining power to the first processing module and the first storage module;

or, when the time interval is not less than the first threshold and less than a second threshold, stopping supplying power to the first processing module and keeping supplying power to the first storage module;

or, when the time interval is not less than the second threshold, stopping supplying power to the first processing module and the first storage module.

8. The method of claim 7, wherein the first threshold is 20 milliseconds and the second threshold is 40 milliseconds.

9. The method of claim 7, wherein in the event that the time interval is not less than the second threshold, ceasing to power the first storage module comprises:

and under the condition that the time interval is not smaller than the second threshold, after the data stored in the first storage module is loaded to the second storage module, stopping supplying power to the first storage module.

10. The method of claim 9, further comprising:

and after the power supply to the first storage module is recovered, loading the data of the second storage module to the first storage module.

11. A power supply control apparatus, characterized in that the apparatus comprises:

the control module is used for respectively controlling power supply of a first processing module and a first storage module in a target chip according to a time interval between a first time period and a second time period, wherein the first time period is a time period for executing a first task, the second time period is a time period for executing a second task, the first storage module is used for storing firmware of the target chip, and the first processing module is used for executing the first task and the second task by accessing the first storage module.

12. A power supply control system is characterized by comprising a control module, a first processing module of a target chip and a first storage module of the target chip:

the control module is configured to respectively control power supplies of the first processing module and the first storage module according to a time interval between a first time period and a second time period, where the first time period is a time period for executing a first task, the second time period is a time period for executing a second task, the first storage module is configured to store firmware of the target chip, and the first processing module is configured to execute the first task and the second task by accessing the first storage module.

13. The power supply control system of claim 12, further comprising a power management chip.

14. The power supply control system of claim 13, wherein the control module is configured to control the power supply of the first processing module of the target chip and the first storage module of the target chip by controlling the power management chip.

15. The power supply control system of claim 12 wherein the target chip comprises a radio frequency processing chip.

16. The power supply control system of claim 15, wherein the first task is receiving a synchronization signal block SSB;

under the condition that the radio frequency processing chip is in an idle state, the second task is to receive a paging message;

or, the second task is switched from a sleep state to an awake state when the radio frequency processing chip is in a connected state.

17. The power supply control system of claim 15 wherein the control module is a baseband processing chip.

18. The power supply control system of claim 12, wherein the target chip comprises a baseband processing chip.

19. The power supply control system of claim 18, wherein the baseband processing chip comprises the control module.

20. A control module, characterized in that the control module comprises a processor for implementing the power supply control method according to any one of claims 1 to 10.

21. A terminal characterized in that it comprises a control module according to claim 20.

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