CN115547814B - Semiconductor structure, manufacturing method thereof and chip - Google Patents
Semiconductor structure, manufacturing method thereof and chip Download PDFInfo
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- CN115547814B CN115547814B CN202211486965.7A CN202211486965A CN115547814B CN 115547814 B CN115547814 B CN 115547814B CN 202211486965 A CN202211486965 A CN 202211486965A CN 115547814 B CN115547814 B CN 115547814B
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- material layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 49
- 238000005530 etching Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000003647 oxidation Effects 0.000 claims abstract description 12
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000010410 layer Substances 0.000 claims 25
- 239000011229 interlayer Substances 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- -1 silicon dioxide Chemical compound 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Optical Integrated Circuits (AREA)
Abstract
The invention relates to the field of semiconductors, and provides a semiconductor structure, a manufacturing method thereof and a chip. The manufacturing method of the semiconductor structure comprises the following steps: providing a multilayer structure comprising a support substrate, an intermediate layer disposed on the support substrate, and a waveguide material layer disposed on the intermediate layer; etching the waveguide material layer to form a waveguide; after the waveguide material layer is etched, carrying out thermal oxidation on the side wall of the waveguide to form a thermal oxidation layer; and removing at least a portion of the thermal oxidation layer.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor structure, a manufacturing method thereof and a chip.
Background
Semiconductor manufacturing technology is the basis of chip technology. Semiconductor manufacturing techniques are widely used in the manufacture of electronic devices and in the manufacture of integrated circuits. In addition, semiconductor fabrication techniques have been tried for many years for the integration of waveguides and photonic devices. Conventional processes in semiconductor manufacturing include photolithography, etching, material deposition, ion implantation, and the like.
The inventors have found that during the formation of the waveguide, the etching process may cause the material layer near the waveguide to have a recess, which may cause the recess to close to form a void in some subsequent process steps, which may have a negative effect on the performance of the waveguide or the characteristics of the semiconductor structure.
Disclosure of Invention
In an exemplary embodiment of the present invention, a method of fabricating a semiconductor structure is provided, comprising: providing a multilayer structure comprising a support substrate, an intermediate layer disposed on the support substrate, and a waveguide material layer disposed on the intermediate layer; etching the waveguide material layer to form a waveguide; after the waveguide material layer is etched, carrying out thermal oxidation on the side wall of the waveguide to form a thermal oxidation layer; and removing at least a portion of the thermal oxidation layer.
In some embodiments, the intermediate layer in the vicinity of the waveguide forms a groove during etching of the waveguide material layer.
In some embodiments, after said removing at least a portion of said thermal oxide layer, a capping layer is formed, said capping layer covering said waveguide.
In some embodiments, the removing at least a portion of the thermal oxide layer comprises etching the thermal oxide layer.
In some embodiments, a hard mask pattern is formed on the waveguide material layer before the etching of the waveguide material layer; wherein the etching the waveguide material layer includes etching the waveguide material layer with the hard mask pattern as a mask.
In some embodiments, the capping layer comprises a silicon dioxide layer.
In some embodiments, the intermediate layer comprises an insulating layer.
In some embodiments, the waveguide material layer is silicon or silicon nitride.
In some embodiments, the method comprises the following steps: etching a hard mask pattern corresponding to the appearance of the target waveguide on the hard mask layer, wherein the hard mask pattern has three or more preset different etching depths; and etching the waveguide material layer by using the hard mask pattern as an etching mask through a one-step etching process to form a plurality of waveguides, wherein the plurality of waveguides have three or more different preset etching depths.
In some embodiments of the present invention, a semiconductor structure is provided that can be fabricated by the methods of fabricating a semiconductor structure described herein.
In some embodiments of the present invention, a chip is provided that may include the semiconductor structure described in embodiments of the present invention.
According to the embodiment of the invention, the grooves in the material layer near the waveguide can be prevented from being closed, the formation of larger gaps is reduced and avoided, and the performance of the waveguide and the characteristics of the semiconductor structure are optimized.
Various aspects, features, advantages, etc. of embodiments of the invention are described in detail below with reference to the accompanying drawings. The above aspects, features, advantages, etc. of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other embodiments based on the drawings without creative efforts.
Fig. 1 to 5 are schematic diagrams showing a plurality of states of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.
FIG. 6 is a schematic diagram illustrating a method of fabricating a semiconductor structure to form a hard mask.
Fig. 7 shows that the grooves of the intermediate layer near the waveguide have voids.
Detailed Description
To facilitate an understanding of the various aspects, features and advantages of the present inventive subject matter, reference is made to the following detailed description taken in conjunction with the accompanying drawings. It should be understood that the various embodiments described below are illustrative only and are not intended to limit the scope of the invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. A chip in this context may include a bare chip. The sequence illustrated herein represents an exemplary scenario when referring to method steps, but does not represent a limitation of the sequence. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The inventors have found that during the formation of the waveguide, the etching process may cause the material layer in the vicinity of the waveguide to have a recess, which may cause the recess to close and form a void in some subsequent process steps, which may have a negative effect on the performance of the waveguide or the characteristics of the semiconductor structure.
In one exemplary embodiment of the present invention, a method of fabricating a semiconductor structure is presented. The method comprises the following steps:
s110 providing a multilayer structure including a support substrate, an intermediate layer disposed on the support substrate, and a waveguide material layer disposed on the intermediate layer;
s130, etching the waveguide material layer to form a waveguide;
s150, after the waveguide material layer is etched, carrying out thermal oxidation on the side wall of the waveguide to form a thermal oxidation layer; and
s170 removing at least a portion of the thermal oxidation layer.
Referring to fig. 1, in step S110, a multi-layer structure 100 is provided, where the multi-layer structure 100 includes a supporting substrate 101, an intermediate layer 102 disposed on the supporting substrate, and a waveguide material layer 103 disposed on the intermediate layer 102.
Wherein the supporting substrate 101 material in the multilayer structure 100 may be: silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, or the like may be a compound semiconductor, an alloy semiconductor, or the like, or a combination of the above materials. The support substrate may be a wafer of the above materials. Illustratively, the intermediate layer 102 may be an insulating layer, such as silicon dioxide, and the waveguide material layer 103 may be silicon, silicon nitride. Illustratively, the multilayer structure 100 may be a semiconductor layer On an Insulator, such as a Silicon-On-Insulator (SOI) wafer, the support substrate 101 is a Silicon substrate, the intermediate layer 102 is a buried oxide layer, and the waveguide material layer 103 is a top Silicon layer. The multilayer structure may also be, for example, a silicon germanium on insulator (S-SiGeOI) wafer or the like.
As shown in fig. 2, the waveguide material layer 103 (see fig. 1) is etched to form a waveguide 104. In an exemplary embodiment, during the etching of the waveguide material layer 103, the intermediate layer 102 near the waveguide 104 forms a groove 105. Illustratively, the process of etching the waveguide material layer 103 may include plasma etching.
As shown in fig. 3, after the etching of the waveguide material layer 103, the sidewalls of the waveguide 104 are thermally oxidized to form a thermal oxide layer 106. By the thermal oxidation process, the roughness of the surface of the waveguide 104 can be reduced, so that it has excellent characteristics. Illustratively, the waveguide 104 is a silicon waveguide, which may also be a silicon nitride waveguide.
Due to the presence of the thermal oxide layer 106 (sidewall capping layer), which causes the exposed opening of the groove 105 to become small, it may cause that the groove 105 cannot be filled when other material layers are formed subsequently, referring to fig. 7, during the process of forming the capping layer 107, the exposed opening of the groove 105 may be blocked, and the capping layer 107 cannot continue to enter or fill the groove 105, and the groove 105 may remain a void (referring to fig. 7), which may affect the optical loss of the waveguide or affect the performance of the photonic device associated with the waveguide.
As shown in fig. 4, at least a portion of the thermal oxide layer 106 is removed. Thereby, the recess 105 may be made to expose a larger opening, thereby allowing subsequently deposited material to enter and fill the recess 105.
As shown in fig. 5, after removing at least a portion of the thermal oxide layer 106, a covering layer 107 is formed, and the covering layer 107 covers the waveguide 104. The capping layer 107 may comprise, for example, an oxide layer of silicon, such as silicon dioxide, among others. In fig. 5, since the thermal oxide layer 106 is partially removed so that the groove 105 has a suitable exposed area, the capping layer 107 continues to fill or enter the groove 105, so that the groove 105 can also be filled with the capping layer 107, thereby avoiding the existence of voids in the groove 105 or reducing the voids to a suitable size.
In some embodiments, for etching to form the waveguide, before etching the waveguide material layer 103, as shown in fig. 6, further comprising forming a hard mask pattern 108 on the waveguide material layer 103; wherein the etching the waveguide material layer 103 includes etching the waveguide material layer 103 by using the hard mask pattern 108 as a mask, so as to form a waveguide 104 (see fig. 2). The hard mask pattern 108 may include silicon nitride and may also include an oxide layer of silicon, such as silicon dioxide, and in some embodiments, the hard mask pattern 108 may include multiple material layers.
In some embodiments, the method comprises the steps of etching a hard mask pattern corresponding to the morphology of the target waveguide on a hard mask layer by three or more photoetching steps, wherein the hard mask pattern has three or more preset different etching depths; and etching the waveguide material layer by using the hard mask pattern as an etching mask through a one-step etching process to form a plurality of waveguides, wherein the plurality of waveguides have three or more different preset etching depths.
In an exemplary embodiment of the present invention, as shown in fig. 5, a semiconductor structure 500 is provided, which can be manufactured by the method for manufacturing a semiconductor structure in the embodiment of the present invention. The semiconductor structure 500 includes: a support substrate 101, an intermediate layer 102 arranged on the support substrate, and a waveguide 104 arranged on the intermediate layer 102, and a cladding layer 107, wherein the intermediate layer 104 has a recess 105.
In one exemplary embodiment of the present invention, a chip is provided that includes a semiconductor structure fabricated by the fabrication method of the present invention.
It will be understood by those skilled in the art that the foregoing is only illustrative of the embodiments of the present invention, and is not intended to limit the scope of the invention as claimed.
Claims (9)
1. A method of fabricating a semiconductor structure, comprising:
providing a multilayer structure comprising a support substrate, an intermediate layer disposed on the support substrate, and a waveguide material layer disposed on the intermediate layer;
etching the waveguide material layer to form a waveguide, wherein in the process of etching the waveguide material layer, a groove is formed in the middle layer near the waveguide;
after the waveguide material layer is etched, carrying out thermal oxidation on the side wall of the waveguide to form a thermal oxidation layer;
removing at least a portion of the thermal oxide layer to enable subsequently deposited material to enter and fill the recess; and
after said removing at least a portion of said thermal oxide layer, forming a capping layer covering said waveguide, wherein said recess has a suitable exposed area due to the removal of at least a portion of said thermal oxide layer, said capping layer continuing to fill or enter the recess.
2. The method of claim 1, wherein said removing at least a portion of said thermal oxide layer comprises etching said thermal oxide layer.
3. The method of fabricating a semiconductor structure according to claim 2, further comprising: forming a hard mask pattern on the waveguide material layer before etching the waveguide material layer;
wherein the etching the waveguide material layer includes etching the waveguide material layer with the hard mask pattern as a mask.
4. The method of fabricating a semiconductor structure according to claim 1, wherein the capping layer comprises a silicon dioxide layer.
5. The method of fabricating a semiconductor structure according to claim 1, wherein the interlayer comprises an insulating layer.
6. The method of claim 1, wherein the waveguide material layer is silicon or silicon nitride.
7. A method of fabricating a semiconductor structure as claimed in claim 1, comprising: etching a hard mask pattern corresponding to the appearance of the target waveguide on the hard mask layer, wherein the hard mask pattern has three or more preset different etching depths; and etching the waveguide material layer by using the hard mask pattern as an etching mask through a one-step etching process to form a plurality of waveguides, wherein the plurality of waveguides have three or more different preset etching depths.
8. A semiconductor structure manufactured by the method of manufacturing a semiconductor structure according to any one of claims 1 to 7.
9. A semiconductor chip comprising the semiconductor structure of claim 8.
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| CN202211486965.7A CN115547814B (en) | 2022-11-25 | 2022-11-25 | Semiconductor structure, manufacturing method thereof and chip |
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| CN202211486965.7A CN115547814B (en) | 2022-11-25 | 2022-11-25 | Semiconductor structure, manufacturing method thereof and chip |
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| CN115547814B true CN115547814B (en) | 2023-03-28 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000340891A (en) * | 1999-03-19 | 2000-12-08 | Mitsubishi Chemicals Corp | Semiconductor optical device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10223989A (en) * | 1997-02-12 | 1998-08-21 | Hitachi Ltd | Waveguide type optical device |
| GB2343293B (en) * | 1998-10-23 | 2003-05-14 | Bookham Technology Ltd | Manufacture of a silicon waveguide structure |
| KR100341483B1 (en) * | 1999-12-03 | 2002-06-21 | 윤종용 | Method of filling gap by using high density plasma oxide |
| US7123805B2 (en) * | 2003-06-16 | 2006-10-17 | Massachusetts Institute Of Technology | Multiple oxidation smoothing method for reducing silicon waveguide roughness |
| WO2007048110A2 (en) * | 2005-10-19 | 2007-04-26 | University Of Notre Dame Du Lac | High-index-contrast waveguide |
| JP4142084B2 (en) * | 2006-10-16 | 2008-08-27 | 三菱電機株式会社 | Semiconductor optical device manufacturing method |
| CN101325171B (en) * | 2007-06-13 | 2010-07-28 | 中国科学院半导体研究所 | A method of manufacturing nanometer-sized triangular air slots |
| US9810843B2 (en) * | 2013-06-10 | 2017-11-07 | Nxp Usa, Inc. | Optical backplane mirror |
| CN103399378B (en) * | 2013-08-05 | 2015-09-16 | 东南大学 | A kind of based on cascading Mach-Zehnder interferometer reconfigurable comb filter and preparation method thereof |
| CN112444912A (en) * | 2020-10-22 | 2021-03-05 | 中国电子科技集团公司第五十五研究所 | High-speed integrated adjustable light delay line and preparation method thereof |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000340891A (en) * | 1999-03-19 | 2000-12-08 | Mitsubishi Chemicals Corp | Semiconductor optical device |
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