CN115525490B - A memory eye diagram testing method, hardware debugging equipment and storage medium - Google Patents
A memory eye diagram testing method, hardware debugging equipment and storage medium Download PDFInfo
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Abstract
本申请实施例提供了一种内存眼图测试方法、硬件调试设备及存储介质，所述方法包括：响应被测试服务器对硬件调试设备的接入指令，通过网络模组获取硬件调试设备的网段信息，向被测试服务器分配硬件调试设备的网段信息，将被测试服务器与硬件调试设备进行网络互联；响应对内存眼图测试项的选择指令，通过测试模组对进行网络互联后的被测试服务器进行内存眼图测试；通过存储模组获取被测试服务器以及内存眼图测试项的数据标识；通过存储模组根据数据标识与映射关系生成针对被测试服务器的存储路径，基于所生成的存储路径存储内存眼图测试结果，减少测试环境的搭建，还可基于直接响应操作提高内存眼图测试可操作性，提升测试效率。
The embodiment of the present application provides a memory eye diagram test method, a hardware debugging device and a storage medium, the method comprising: responding to an access instruction of a tested server to a hardware debugging device, obtaining network segment information of the hardware debugging device through a network module, allocating the network segment information of the hardware debugging device to the tested server, and interconnecting the tested server and the hardware debugging device through a network; responding to a selection instruction for a memory eye diagram test item, performing a memory eye diagram test on the tested server after the network interconnection through a test module; obtaining data identifiers of the tested server and the memory eye diagram test items through a storage module; generating a storage path for the tested server according to the data identifier and a mapping relationship through the storage module, storing the memory eye diagram test result based on the generated storage path, reducing the construction of the test environment, and improving the operability of the memory eye diagram test based on a direct response operation, thereby improving the test efficiency.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a memory eye diagram testing method, a hardware debugging device, and a corresponding computer storage medium.
Background
Typically, during the server development phase and when new memory is introduced into the project, a memory test is performed, where one memory test may be a memory eye test, which is mainly used to test the signal integrity between the memory and the CPU (Central Processing Unit ), and is an important item in the memory test.
However, in the related technology of the memory eye diagram test, the existing test equipment has a relatively high test difficulty, so that the test environment is relatively difficult to build, the test steps are relatively complicated, and the test efficiency is greatly affected.
Disclosure of Invention
In view of the foregoing, embodiments of the present application are directed to providing a memory eye testing method, a hardware debug device, and a corresponding computer storage medium, which overcome or at least partially solve the foregoing problems.
The embodiment of the application discloses a memory eye diagram test method, which relates to hardware debugging equipment, wherein the hardware debugging equipment is used for testing a memory eye diagram of a tested server and comprises a network module, a test module and a storage module, and the method comprises the following steps:
Responding to an access instruction of the tested server to the hardware debugging equipment, acquiring network segment information of the hardware debugging equipment through a network module, distributing the network segment information of the hardware debugging equipment to the tested server, and carrying out network interconnection on the tested server and the hardware debugging equipment;
Responding to a selection instruction of the memory eye diagram test item, and performing memory eye diagram test on the tested server after network interconnection through the test module;
acquiring data identifiers of a tested server and a memory eye pattern test item through a storage module, wherein the data identifiers and storage positions of hardware debugging equipment have a pre-established mapping relation;
And generating a storage path for the tested server according to the data identification and the mapping relation by the storage module, and storing a memory eye diagram test result based on the generated storage path.
Optionally, the network module is provided with a static gateway address and/or a dynamic gateway address, and the network module is used for acquiring the network segment information of the hardware debugging equipment and distributing the network segment information of the hardware debugging equipment to the tested server, wherein the network segment information comprises:
And under the condition that the network module is in the setting of the static gateway address, responding to a gateway switching instruction of the static gateway address and/or the dynamic gateway address set in the network module, acquiring the dynamic gateway network segment information of the hardware debugging equipment through the network module, and distributing the dynamic gateway network segment information of the hardware debugging equipment to the tested server.
Optionally, the network module is provided with a static gateway address and/or a dynamic gateway address, and the network module is used for acquiring the network segment information of the hardware debugging equipment and distributing the network segment information of the hardware debugging equipment to the tested server, wherein the network segment information comprises:
And under the condition that the network module is in the setting of the dynamic gateway address, responding to the gateway switching instruction of the static gateway address and/or the dynamic gateway address set in the network module, acquiring the static gateway network segment information of the hardware debugging equipment through the network module, and distributing the static gateway network segment information of the hardware debugging equipment to the tested server.
Optionally, the testing module tests the tested server which performs network interconnection according to the memory eye diagram test item to obtain a memory eye diagram test result, and the method further includes:
In the process of performing memory eye diagram test on the tested server after network interconnection, displaying current real-time test information and test abnormality prompts on a display screen of the hardware debugging equipment through a test module, wherein the real-time test information comprises any one or more of test residual time, test speed and test progress, and the test abnormality prompts are used for informing the hardware debugging equipment of module abnormality in the process of performing memory eye diagram test on the tested server.
Optionally, the hardware debugging device further includes a debugging module, after responding to the access instruction of the tested server to the hardware debugging device, further includes:
Responding to a startup and shutdown instruction of the hardware debugging equipment, detecting whether the accessed tested server presents corresponding operation with the startup and shutdown instruction through the debugging module to obtain a test environment building result, wherein the test environment building result is used for informing the hardware debugging equipment whether the test environment requirement for the tested server is met in the test environment building.
Optionally, the hardware debugging device further includes an extension module, and performs a memory eye diagram test on the tested server after the network interconnection through the test module, and further includes:
And obtaining a test log obtained by the test module through performing memory eye diagram test on the tested server subjected to network interconnection through the expansion module, and performing log analysis on the test log to obtain a memory eye diagram test result.
In some embodiments of the present application, the present application also discloses a method for implementing any memory eye diagram test when a hardware debug device of a hardware debug device is executed, where the hardware debug device is configured to perform a memory eye diagram test on a tested server, and the method includes a network module, a test module, and a storage module;
The network module is used for responding to an access instruction of the tested server to the hardware debugging equipment, acquiring network segment information of the hardware debugging equipment, distributing the network segment information of the hardware debugging equipment to the tested server, and interconnecting the tested server and the hardware debugging equipment through a network;
The test module is used for responding to the selection instruction of the memory eye diagram test item and carrying out memory eye diagram test on the tested server after network interconnection;
the storage module is used for acquiring the data identification of the tested server and the memory eye diagram test item, generating a storage path aiming at the tested server according to the data identification and the mapping relation, and storing a memory eye diagram test result based on the generated storage path.
Optionally, the hardware debugging device further includes an expansion module, and the expansion module is used for obtaining a test log obtained by the test module through performing the memory eye diagram test on the tested server after the network interconnection, and performing log analysis on the test log to obtain a memory eye diagram test result.
Optionally, the hardware debugging device further comprises a debugging module, wherein the debugging module is used for responding to a startup and shutdown instruction of the hardware debugging device, detecting whether the accessed tested server presents corresponding operation with the startup and shutdown instruction to obtain a test environment building result, and the test environment building result is used for informing whether the hardware debugging device meets the test environment requirement for the tested server in the test environment building.
In some embodiments of the present application, a computer-readable storage medium is further disclosed, on which a computer program is stored, which when executed by a processor implements any one of the memory eye test methods.
The embodiment of the application has the following advantages:
In the embodiment of the application, the hardware debugging equipment for performing the memory eye diagram test on the tested server can comprise a network module, a test module and a storage module, at the moment, the network module can respond to the access instruction of the tested server to the hardware debugging equipment, the network segment information of the hardware debugging equipment is distributed to the tested server to perform network interconnection on the tested server and the hardware debugging equipment, then the test module can respond to the selection instruction of the memory eye diagram test item, the memory eye diagram test is performed on the tested server after the network interconnection, the storage path for the tested server can be generated through the storage module according to the data identification and the mapping relation, the memory eye diagram test result is stored based on the generated storage path, namely, the automatic distribution of the same network segment is realized when the tested server is accessed, the environment such as a connecting external network and a network eye diagram configuration is reduced, the control machine in the test environment is canceled, the environment time is shortened, the memory eye diagram test operability is improved, and the test efficiency is improved on the basis of the direct response operation on the hardware debugging equipment. Furthermore, the memory eye diagram test result of the tested server can be stored based on the designated storage path, so that the management of the tested server is facilitated, and the test efficiency is further improved.
Drawings
FIG. 1 is a diagram illustrating a memory eye diagram test in the related art;
FIG. 2 is a schematic diagram of a hardware debug apparatus according to an embodiment of the present application;
FIG. 3 is a flowchart illustrating steps of a memory eye diagram test method according to an embodiment of the present application;
FIG. 4 is a block diagram illustrating an embodiment of a memory eye diagram test apparatus according to the present application;
Fig. 5 is a schematic diagram of a non-volatile computer readable storage medium for implementing a network card stability test method according to an embodiment of the present application.
Detailed Description
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description.
The memory eye diagram test is an important term in memory testing, and is mainly used for testing signal integrity between a memory and a CPU. The eye diagram refers to a series of graphs displayed by accumulating digital signals on an oscilloscope, contains rich information, can observe the influence of inter-code crosstalk and noise from the eye diagram generally, and reflects the integral characteristics of the digital signals, so that the system quality degree is estimated, and the method is a core of signal integrity analysis of a high-speed interconnection system.
Referring to fig. 1, an implementation schematic diagram of a memory eye test in the related art is shown, where a device for performing a memory eye test on a server under test 111 (System Under Test, abbreviated as SUT) is denoted as an HDT device 110 (Hardware Debug Tool, hardware debug device), where during the test, not only the HDT device needs to be configured, but also a cold reset interface needs to be added to the server under test for configuring the test, and further, since the HDT device 110 cannot perform a network connection, a server needs to be configured to implement an external network connection between the HDT device 110 and the server under test 111, where the configured server may also be used as a controller 112, or may be a test management station (TEST MANAGEMENT, abbreviated as TMS), and the HDT control software is installed under the system and the memory eye test software is performed, so that the controller 112 performs the memory eye test on the server under test 111 when executing the software.
In a specific implementation, during the memory eye diagram test by using the HDT device, access to the functional network corresponding to the HDT device is required, at this time, the notebook may be connected to the external network, and then, through network sharing, both the control machine and the tested server may access to the external network, and it is required to ensure the network port of the HDT device, the network card network port of the tested server with the memory, the network card network port of the control machine, and the network port of the external network notebook, where networks of these network ports may be mutually communicated, so that network interconnection before each device needs to be implemented by means of a switch.
In the process of performing the memory eye diagram test, the HDT device also needs to implement test data collection by means of a JTAG (Joint Test Action Group, joint test working group) interface of the motherboard, that is, by connecting JTAG wires from the motherboard to the HDT device. And because the HDT control software and the test software related to the memory eye diagram test are installed on the controller 112, in the process of performing the test, the test item and the test machine can be selected in memeye test software (Memeye is a lightweight NodeJS process monitoring tool) installed on the controller, so that the test process and the analysis test result can be conveniently checked. The test result is stored in a designated path of the controller, after the test based on the HDT software executed by the controller and the software related to the memory eye test is completed, the memory eye test result for the tested service section is also required to be collected from the controller, and in the process of testing the built test environment, whether the instruction such as on-off is effective or not needs to be tested by the HDT remote sending.
As can be seen from the above, in the method of testing the memory eye pattern in the related art, the external network, the network of the testing machine, the control machine and the HDT device are required to be configured to implement the network interconnection between the devices, and the problem in the process of setting up the environment needs to be repeatedly checked because the setting up of the testing environment needs to be performed based on the device with the required configuration, which easily results in the problem that the testing is easy to locate and is unclear, and the problem that the testing operation is difficult because the setting up of the testing environment is required, which has high requirements on the professionals.
One of the core ideas of the embodiment of the application is to modularize the functions realized by the related equipment built with the test environment, integrate the modularized related modules into the HDT equipment, improve the HDT equipment shown in fig. 1, realize the automatic allocation of the same network segment based on the functional modules related to the built test environment of the hardware debugging equipment, reduce the environments of connecting external networks, configuring networks and the like required to be set for the test when the tested server is accessed, cancel the controller in the test environment, reduce the time for building the environment, and also can improve the test operability of the memory eye diagram and improve the test efficiency based on the direct response operation of the hardware debugging equipment. And because the functional modules realized by the equipment related to the construction of the test environment are integrated in the HDT equipment, the construction of the test environment based on the equipment with required configuration is not performed, so that the problem in the construction process of the repeated investigation environment is not existed, and the problem that the positioning is unclear easily when the problem occurs in the test is solved. Furthermore, the memory eye diagram test result of the tested server can be stored based on the designated storage path, so that the management of the tested server is facilitated, and the test efficiency is further improved.
Referring to fig. 2, a schematic diagram of a hardware debug apparatus provided by an embodiment of the present application is shown, where a hardware debug apparatus 21 is used for performing a memory eye test, and the hardware debug apparatus 21 may be mainly represented as an HDT apparatus 21 modified from the HDT apparatus 110 shown in fig. 1. The improvement of the HDT equipment is characterized in that functions realized by constructing related equipment with a test environment are modularized, and the modularized related modules are integrated in the HDT equipment so as to avoid configuration of other equipment for constructing the test environment based on the function modules of the improved HDT equipment, and the problem that the test is unclear in positioning due to the need of repeatedly checking the problem in the environment construction process can be solved while the test efficiency is improved.
Specifically, the improved HDT device 21 may include a network module 210, a debug module 211, a test module 212, a storage module 213, and an expansion module 214.
The network module 210 is mainly used for ensuring that the improved HDT device 21 can be connected to an external network through a wired or wireless mode, and automatically distributes the same network segment IP for the tested server when the tested server accesses the HDT device, so that the network interconnection between the tested server and the hardware debugging device is realized while the HDT device 21 has the function of accessing the external network. The method specifically comprises the steps of responding to an access instruction of a tested server to hardware debugging equipment, acquiring network segment information of the hardware debugging equipment, and distributing the network segment information of the hardware debugging equipment to the tested server so as to carry out network interconnection between the tested server and the hardware debugging equipment.
The debug module 211 mainly can judge whether the test environment requirement is met in advance so as to locate the problem in advance, is mainly responsible for responding to the on-off instruction of the hardware debug equipment, detects whether the accessed tested server presents corresponding operation with the on-off instruction, and obtains a test environment construction result, and the obtained test environment construction result can be used for informing the hardware debug equipment whether the test environment requirement for the tested server is met in the test environment construction.
The test module 212 is mainly responsible for performing a memory eye test on the tested server, and is specifically configured to perform a memory eye test on the tested server after network interconnection in response to a selection instruction of a memory eye test item, so as to obtain a related test log. In the process of performing the memory eye diagram test on the tested server after the network interconnection, the method can also be used for displaying current real-time test information and test abnormality prompts on a display screen of the hardware debugging equipment, wherein the displayed real-time test information can specifically comprise any one or more of test remaining time, test speed and test progress, and the displayed test abnormality prompts are mainly used for informing the hardware debugging equipment of module abnormality in the process of performing the memory eye diagram test on the tested server.
The storage module 213 is mainly responsible for storing the obtained test log and/or the test result of the memory eye diagram, so as to ensure the data storage function of the HDT device 21, so that the system can be normally installed in the HDT device and the test log can also be stored in the HDT device 21. When the storage module 213 performs storage, the data identifier of the tested server and the memory eye diagram test item may be specifically obtained, where the data identifier and the storage location of the hardware debug device have a pre-established mapping relationship, and at this time, a storage path for the tested server may be generated according to the data identifier and the mapping relationship, and the memory eye diagram test result is stored based on the generated storage path, so as to store the test log or the test result in the designated path, thereby facilitating management of the tested server and further improving the test efficiency. In addition, the storage module 213 may further reserve a USB interface, so that the test log may be copied by the USB disk.
The expansion module 214 is mainly responsible for providing an autonomous analysis test log for the HDT device 21 and processing test data, that is, the HDT device 21 may obtain, through the expansion module 214, a test log obtained by performing a memory eye test on a tested server after network interconnection by the test module, and perform log analysis on the test log to obtain a memory eye test result, so as to determine whether the test passes based on the memory eye test result. In addition, the expansion module 214 may also reserve a VGA (Video GRAPHICS ARRAY ) interface so that an incoming system may be selected after power-on based on the reserved VGA interface when an external system disk is present.
In the embodiment of the application, the functions realized by the related equipment built with the test environment can be modularized, and the modularized related module is integrated in the HDT equipment, so that the HDT equipment shown in the figure 1 is improved, the function modules related to the building of the test environment based on the hardware debugging equipment are realized, the automatic allocation of the same network segment is realized when the tested server is accessed, the environments such as an external network and a configuration network which are required to be set for testing are reduced, a controller in the test environment is canceled, the environment building time is shortened, the direct response operation to the hardware debugging equipment can be further based, the test operability of a memory eye diagram is improved, and the test efficiency is improved.
Referring to fig. 3, a flowchart illustrating steps of an embodiment of a memory eye test method according to the present application relates to a hardware debug device for performing a memory eye test as shown in fig. 2, and may specifically include the following steps:
step 301, responding to an access instruction of a tested server to the hardware debugging equipment, acquiring network segment information of the hardware debugging equipment through a network module, distributing the network segment information of the hardware debugging equipment to the tested server, and interconnecting the tested server and the hardware debugging equipment through a network;
In the memory eye diagram test mode in the related art, the used HDT equipment is not only required to configure an external network, configure a network of a tester, a controller and the HDT equipment to realize network interconnection among the equipment, but also is required to repeatedly check the problem in the process of setting up the environment because of the requirement of setting up the test environment based on the equipment with required configuration, so that the problem of the test is easy to locate and unclear is easily caused, and the problem that the requirement of professionals is high because of the requirement of setting up the test environment, so that the test operation is difficult.
In the embodiment of the application, the HDT equipment used in the related technology is mainly improved, the functions realized by building related equipment with the testing environment are modularized, and the modularized related modules are integrated in the HDT equipment, namely, the test execution process, the error reporting mechanism and the test log storage are integrated in the HDT equipment, so that the configuration of other equipment for building the testing environment is avoided based on the functional modules of the improved HDT equipment, and the problem of unclear positioning of the testing caused by the need of repeatedly checking the problems in the environment building process can be solved while the testing efficiency is improved.
Specifically, a network module can be added to the HDT device, a wired or wireless mode is provided for the HDT device used in the related technology to connect to an external network, and the same network segment IP can be automatically allocated to the tested server when the tested server accesses the HDT device, so that the network interconnection between the tested server and the hardware debugging device is realized while the HDT device is ensured to have the function of accessing the external network.
In practical application, when the HDT device responds to an access instruction of the tested server to the hardware debugging device, that is, when the tested server is detected to be accessed to the HDT device, network segment information of the hardware debugging device can be obtained through a network module of the HDT device, the network segment information of the hardware debugging device is distributed to the tested server, setting of automatic network interconnection is achieved, and the tested server and the hardware debugging device are subjected to network interconnection.
The network module is provided with a static gateway address (i.e. static IP) and/or a dynamic gateway address (dynamic IP), and the setting of the static IP can be mainly represented by realizing IP distribution of the HDT device based on the switch, and the setting of the dynamic IP can be mainly represented by configuring the reserved network interface into a DHPC (Dynamic Host Configuration Protocol ) mode when the network module reserves the network interface for the HDT device.
Specifically, a gateway switching instruction for a static gateway address and/or a dynamic gateway address may be set on the HDT device, and at this time, the static gateway network segment information and/or the dynamic gateway network segment information of the hardware debugging device may be acquired through the network module in response to the gateway switching instruction for the static gateway address and/or the dynamic gateway address set in the network module, and the static gateway network segment information and/or the dynamic gateway network segment information of the hardware debugging device may be allocated to the tested server.
Under the condition that the network module is in the setting of the static gateway address, the HDT equipment can acquire the dynamic gateway network segment information of the hardware debugging equipment through the network module when responding to the gateway switching instruction of the static gateway address and/or the dynamic gateway address set in the network module, and the dynamic gateway network segment information of the hardware debugging equipment is distributed to the tested server.
In another case, under the condition that the network module is in the setting of the dynamic gateway address, when the HDT device responds to the gateway switching instruction of the static gateway address and/or the dynamic gateway address set in the network module, the static gateway network segment information of the hardware debugging device can be obtained through the network module, and the static gateway network segment information of the hardware debugging device is distributed to the tested server.
Based on a network interface (network port for short) reserved by the network module in the HDT equipment, the access of the tested server to the external network is realized.
In some embodiments of the present application, the improved HDT device further includes adding a debug module to the HDT device, so as to realize early judgment of whether the test environment requirement is met, so as to locate the problem in advance, that is, the debug module may test the test environment built by the HDT device, specifically may be represented by responding to a startup and shutdown instruction of the hardware debug device, detecting, by the debug module, whether the accessed tested server presents a corresponding operation with the startup and shutdown instruction, so as to obtain a test environment building result, where the obtained test environment building result may be used to inform the hardware debug device whether the test environment requirement for the tested server is met in the test environment building.
In practical application, the debug module added in the HDT device may be implemented through a display screen reserved in the HDT device and a debug key, where the reserved key may be set in a touch screen form, and when testing, the BMC (Baseboard Management Controller, executing a remote management controller of the server, which is a baseboard management controller) of the tested server may be mainly accessed to the HDT device based on a specific interface, and then a basic on-off instruction is sent through the key, so as to observe whether the tested server can normally operate according to the key instruction, that is, detect whether the accessed tested server presents a corresponding operation with the on-off instruction. And the method for starting and closing the server is realized by pulling through hardware resources and canceling the signal acquisition from the server main board.
Step 302, responding to a selection instruction of a memory eye diagram test item, and performing memory eye diagram test on a tested server subjected to network interconnection through a test module;
After the network interconnection is carried out on the tested server and the hardware debugging equipment based on the automatic distribution of the network segment information and the hardware debugging equipment meets the requirement of the tested server on the testing environment in the construction of the testing environment, namely under the condition of eliminating the abnormal error of the construction of the testing environment, the HDT equipment is used for carrying out the memory eye diagram test on the tested server.
In the process of testing the memory eye pattern, the memory eye pattern is mainly realized by a test module added in the HDT equipment. In practical applications, the control machine for executing the HDT software and the software related to the memory eye diagram test in fig. 1 is mainly omitted, and related functions of the software to be run are given to the improved HDT device in the form of a test module.
Then, for the test module, the capability of introducing test software into the HDT device in advance can be realized, so that the memory eye diagram test can be performed on the tested server after the network interconnection in the configured test environment.
Specifically, the HDT device may respond to a selection instruction for a test item of a memory eye pattern, and then perform a memory eye pattern test on the tested server after network interconnection through the test module, which is shown as directly selecting the test item and performing the test.
In some embodiments of the present application, in the process of performing a memory eye diagram test on a server to be tested after network interconnection, the current real-time test information and a test abnormality prompt may also be displayed on a display screen of the hardware debug device through the test module, and a specific storage path of the test log stored in the HDT device may also be displayed. The displayed real-time test information may include any one or more of test remaining time, test speed and test progress, and the displayed test abnormality prompt may be used to inform the hardware debugging device of module abnormality in the process of performing the memory eye diagram test on the tested server.
In a specific implementation, the test module is only responsible for performing a memory eye diagram test on the tested server after network interconnection to obtain a related test log, and in order to obtain a memory eye diagram test result, log analysis is required to be performed on the test log obtained by the test module through an expansion module added in the HDT equipment.
Step 303, obtaining the data identification of the tested server and the memory eye diagram test item through the storage module;
After the log analysis is performed on the test log obtained by the test module through the expansion module to obtain the memory eye diagram test result, the memory eye diagram test result can be stored.
Specifically, a storage module can be added in the HDT device, and the storage module is mainly responsible for storing the obtained test log and/or memory eye diagram test result, so that the data storage function of the HDT device can be ensured, the system can be normally installed in the HDT device, and the test log can be stored in the HDT device.
In practical application, the memory module can store the memory eye diagram test result of the tested server based on the designated memory path, so that the management of the tested server is facilitated, and the test efficiency is further improved. According to the storage performed by the designated storage path, since the data identifier and the storage position of the hardware debugging device have a pre-established mapping relationship, the method can be expressed as acquiring the data identifier of the tested server and the memory eye diagram test item so as to determine the storage position with the mapping relationship.
And step 304, generating a storage path for the tested server according to the data identification and the mapping relation through the storage module, and storing a memory eye diagram test result based on the generated storage path.
After determining the storage position with the mapping relation, the storage module can specifically generate a storage path aiming at the tested server according to the data identification and the mapping relation, namely, the determined storage position, store the memory eye diagram test result into the storage module, and judge whether the test passes or not based on the memory eye diagram test result.
For example, assuming that the data identifier of the tested server is fuwuqi1 and the data identifier of the memory eye test item performed by the tested server is 0, the data identifier may be formed into a form of "fuwuqi1+0", and the data identifier corresponds to the storage location s0, then a corresponding storage path may be generated based on the storage location s0, and assuming that the path is "// fuwuqi1+0, s0", the memory eye test log and/or the memory eye test result for fuwuqi1 are stored into "// fuwuqi1+0, s0", so that the management of the tested server is facilitated, and the test efficiency is further improved.
In a preferred embodiment of the present application, the storage module may further reserve a USB interface, so that the test log may be copied by the USB disk, and the stored memory eye diagram test result may be obtained. After the memory eye diagram test result under a certain memory path is exported, in order to ensure the memory space of the HDT device, the memory eye diagram test result stored under the memory path can be automatically deleted, or after the memory eye diagram test result is exported, the memory eye diagram test result stored under the corresponding memory path can be formatted according to a preset time interval. The embodiments of the present application are not limited in this regard.
In the embodiment of the application, the hardware debugging equipment for performing the memory eye diagram test on the tested server can comprise a network module, a test module and a storage module, at the moment, the network module can respond to the access instruction of the tested server to the hardware debugging equipment, the network segment information of the hardware debugging equipment is distributed to the tested server to perform network interconnection on the tested server and the hardware debugging equipment, then the test module can respond to the selection instruction of the memory eye diagram test item, the memory eye diagram test is performed on the tested server after the network interconnection, the storage path for the tested server can be generated through the storage module according to the data identification and the mapping relation, the memory eye diagram test result is stored based on the generated storage path, namely, the automatic distribution of the same network segment is realized when the tested server is accessed, the environment such as a connecting external network and a network eye diagram configuration is reduced, the control machine in the test environment is canceled, the environment time is shortened, the memory eye diagram test operability is improved, and the test efficiency is improved on the basis of the direct response operation on the hardware debugging equipment. Furthermore, the memory eye diagram test result of the tested server can be stored based on the designated storage path, so that the management of the tested server is facilitated, and the test efficiency is further improved.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the application.
Referring to fig. 4, a block diagram of an embodiment of a memory eye test device of the present application is shown, which relates to a hardware debug device, and the hardware debug device shown in fig. 2 is used for performing a memory eye test on a server to be tested, and includes a network module, a test module and a storage module, and may specifically include the following modules:
The network interconnection module 401 is located in the network module and is configured to respond to an access instruction of the tested server to the hardware debugging device, obtain network segment information of the hardware debugging device, distribute the network segment information of the hardware debugging device to the tested server, and perform network interconnection between the tested server and the hardware debugging device;
The memory eye diagram test module 402 is located in the test module and is used for responding to the selection instruction of the memory eye diagram test item and performing memory eye diagram test on the tested server after network interconnection;
The data identifier obtaining module 403 is located in the storage module and is configured to obtain a data identifier of the tested server and a memory eye pattern test item, where the data identifier has a pre-established mapping relationship with a storage location of the hardware debugging device;
And the test result storage module 404 is located in the storage module and is used for generating a storage path for the tested server according to the data identification and the mapping relation, and storing the memory eye pattern test result based on the generated storage path.
In one embodiment of the present application, the network module is provided with a static gateway address and/or a dynamic gateway address, and the network interconnection module 401 may include the following sub-modules:
The first network segment allocation submodule is used for responding to a gateway switching instruction of a static gateway address and/or a dynamic gateway address set in the network module under the condition that the network module is in the setting of the static gateway address, acquiring the dynamic gateway segment information of the hardware debugging equipment, and allocating the dynamic gateway segment information of the hardware debugging equipment to the tested server.
In one embodiment of the present application, the network module is provided with a static gateway address and/or a dynamic gateway address, and the network interconnection module 401 may include the following sub-modules:
The second network segment allocation submodule is used for responding to a gateway switching instruction of a static gateway address and/or a dynamic gateway address set in the network module under the condition that the network module is in the setting of the dynamic gateway address, acquiring static gateway segment information of the hardware debugging equipment, and allocating the static gateway segment information of the hardware debugging equipment to the tested server.
In an embodiment of the present application, the hardware debugging device further includes an expansion module, and the apparatus provided in the embodiment of the present application may further include the following modules:
The system comprises a real-time test information display module, a hardware debugging device and a test program module, wherein the real-time test information display module is positioned in the test module and used for displaying current real-time test information and test abnormality prompts on a display screen of the hardware debugging device in the process of performing memory eye diagram test on a tested server after network interconnection, and the real-time test information comprises any one or more of test residual time, test speed and test progress, and the test abnormality prompts are used for informing the hardware debugging device of abnormal modules in the process of performing memory eye diagram test on the tested server.
In one embodiment of the present application, the hardware debugging device further includes a debugging module, and after responding to an access instruction of the tested server to the hardware debugging device, the apparatus provided in the embodiment of the present application may further include the following modules:
The test environment construction detection module is positioned on the debugging module and used for responding to the on-off instruction of the hardware debugging equipment, detecting whether the accessed tested server presents corresponding operation with the on-off instruction to obtain a test environment construction result, and informing the hardware debugging equipment whether the test environment requirement for the tested server is met in the test environment construction.
In an embodiment of the present application, the hardware debugging device further includes an expansion module, and the apparatus provided in the embodiment of the present application may further include the following modules:
The test result generation module is positioned on the expansion module and used for acquiring a test log obtained by the test module for performing the memory eye diagram test on the tested server after the network interconnection, and performing log analysis on the test log to obtain a memory eye diagram test result.
In the memory eye diagram testing device provided by the embodiment of the application, network segment information of the hardware debugging equipment can be distributed to the tested server through the network module in response to the access instruction of the tested server to the hardware debugging equipment so as to carry out network interconnection between the tested server and the hardware debugging equipment, then the tested server after network interconnection can be subjected to memory eye diagram testing through the testing module in response to the selection instruction of the memory eye diagram testing item, a storage path aiming at the tested server can be generated through the storage module according to the data identification and the mapping relation, the memory eye diagram testing result is stored based on the generated storage path, namely, the automatic distribution of the same network segment during the access of the tested server is realized based on the functional module which is related to the establishment of the testing environment and is provided by the hardware debugging equipment, the environment such as a connecting external network and a configuration network is omitted, the control machine in the testing environment is omitted, the environment establishment time is shortened, the memory eye diagram testing operability is improved based on the direct response operation of the hardware debugging equipment, and the testing efficiency is improved. Furthermore, the memory eye diagram test result of the tested server can be stored based on the designated storage path, so that the management of the tested server is facilitated, and the test efficiency is further improved.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
In some embodiments of the present application, a non-volatile computer readable storage medium is further provided in the embodiments of the present application, as shown in fig. 5, a computer program 51 is stored on the non-volatile computer readable storage medium 5, and when the computer program 51 is executed by a processor, the processes of the above-mentioned embodiments of the network card stability test method are implemented, and the same technical effects can be achieved, so that repetition is avoided, and no further description is given here.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the application may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the application.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of additional like elements in a process, method, article, or terminal device comprising the element.
The foregoing describes in detail a memory eye diagram testing method, a hardware debugging device and a corresponding computer storage medium, wherein specific examples are provided to illustrate the principles and embodiments of the present application, and the above examples are provided to assist in understanding the method and core ideas of the present application, and meanwhile, for those skilled in the art, according to the ideas of the present application, there are variations in the specific embodiments and application scope, and in summary, the present disclosure should not be construed as limiting the present application.
Claims (8)
1. The method is characterized by involving hardware debugging equipment, wherein the hardware debugging equipment is used for testing the memory eye diagram of a tested server and comprises a network module, a testing module and a storage module, and the method comprises the following steps:
responding to an access instruction of the tested server to the hardware debugging equipment, acquiring network segment information of the hardware debugging equipment through the network module, distributing the network segment information of the hardware debugging equipment to the tested server, and carrying out network interconnection on the tested server and the hardware debugging equipment;
Responding to a selection instruction of the memory eye diagram test item, and performing memory eye diagram test on the tested server subjected to network interconnection through the test module;
Acquiring data identifiers of the tested server and the memory eye pattern test item through the storage module, wherein the data identifiers and the storage position of the hardware debugging equipment have a pre-established mapping relation;
Generating a storage path for the tested server according to the data identification and the mapping relation through the storage module, and storing a memory eye diagram test result based on the generated storage path;
the network module is provided with a static gateway address and/or a dynamic gateway address, the network module is used for acquiring the network segment information of the hardware debugging equipment, and distributing the network segment information of the hardware debugging equipment to the tested server, and the network segment information comprises the following components:
Under the condition that the network module is in the setting of a static gateway address, responding to a gateway switching instruction of the static gateway address and/or the dynamic gateway address set in the network module, acquiring the dynamic gateway network segment information of the hardware debugging equipment through the network module, and distributing the dynamic gateway network segment information of the hardware debugging equipment to the tested server;
the network module is provided with a static gateway address and/or a dynamic gateway address, the network module is used for acquiring the network segment information of the hardware debugging equipment, and distributing the network segment information of the hardware debugging equipment to the tested server, and the network segment information comprises the following components:
and under the condition that the network module is in the setting of the dynamic gateway address, responding to the gateway switching instruction of the static gateway address and/or the dynamic gateway address set in the network module, acquiring the static gateway network segment information of the hardware debugging equipment through the network module, and distributing the static gateway network segment information of the hardware debugging equipment to the tested server.
2. The method of claim 1, wherein the testing, by the testing module, the tested server that performs network interconnection according to the memory eye diagram test item, obtains a memory eye diagram test result, further comprising:
Displaying current real-time test information and test abnormality prompts on a display screen of the hardware debugging equipment through the test module in the process of performing memory eye diagram test on the tested server after network interconnection, wherein the real-time test information comprises any one or more of test remaining time, test speed and test progress, and the test abnormality prompts are used for informing the hardware debugging equipment of abnormal modules in the process of performing memory eye diagram test on the tested server.
3. The method of claim 1 or 2, wherein the hardware debug apparatus further comprises a debug module that, after responding to the access instruction of the tested server to the hardware debug apparatus, further comprises:
Responding to a startup and shutdown instruction of the hardware debugging equipment, detecting whether an accessed tested server presents corresponding operation with the startup and shutdown instruction through the debugging module to obtain a test environment construction result, wherein the test environment construction result is used for informing whether the hardware debugging equipment meets the test environment requirement for the tested server in the test environment construction.
4. The method of claim 1, wherein the hardware debug apparatus further comprises an expansion module, and the performing, by the test module, a memory eye test on the tested server after the network interconnection, further comprises:
And obtaining a test log obtained by the test module through performing memory eye diagram test on the tested server subjected to network interconnection through the expansion module, and performing log analysis on the test log to obtain a memory eye diagram test result.
5. A hardware debugging device, wherein the hardware debugging device is executed to implement the memory eye diagram testing method according to any one of claims 1 to 4, and the hardware debugging device is used for performing memory eye diagram testing on a tested server, and comprises a network module, a testing module and a storage module;
The network module is used for responding to an access instruction of the tested server to the hardware debugging equipment, acquiring network segment information of the hardware debugging equipment, distributing the network segment information of the hardware debugging equipment to the tested server, and carrying out network interconnection on the tested server and the hardware debugging equipment;
the test module is used for responding to a selection instruction of the memory eye diagram test item and performing memory eye diagram test on the tested server after network interconnection;
the storage module is used for acquiring the data identifications of the tested server and the memory eye diagram test item, generating a storage path aiming at the tested server according to the data identifications and the mapping relation, and storing a memory eye diagram test result based on the generated storage path;
The network module is provided with a static gateway address and/or a dynamic gateway address, and the network interconnection module comprises the following sub-modules:
The first network segment allocation submodule is used for responding to a gateway switching instruction of a static gateway address and/or a dynamic gateway address set in the network module under the condition that the network module is in the setting of the static gateway address, acquiring the dynamic gateway segment information of the hardware debugging equipment, and allocating the dynamic gateway segment information of the hardware debugging equipment to the tested server;
The second network segment allocation submodule is used for responding to a gateway switching instruction of a static gateway address and/or a dynamic gateway address set in the network module under the condition that the network module is in the setting of the dynamic gateway address, acquiring static gateway segment information of the hardware debugging equipment, and allocating the static gateway segment information of the hardware debugging equipment to the tested server.
6. The hardware debugging device according to claim 5, further comprising an expansion module, wherein the expansion module is configured to obtain a test log obtained by the test module performing a memory eye diagram test on the tested server after the network interconnection, and perform log analysis on the test log to obtain a memory eye diagram test result.
7. The hardware debugging device according to claim 5 or 6, further comprising a debugging module, wherein the debugging module is used for responding to a startup and shutdown instruction of the hardware debugging device, detecting whether an accessed tested server presents corresponding operation with the startup and shutdown instruction to obtain a test environment construction result, and the test environment construction result is used for informing whether the hardware debugging device meets the test environment requirement for the tested server in the test environment construction.
8. A computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, which when executed by a processor implements the memory eye test method according to any of claims 1 to 4.
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| CN116319431A (en) * | 2023-03-17 | 2023-06-23 | 苏州浪潮智能科技有限公司 | Network test method, device and medium for memory eye diagram |
| CN116013401B (en) * | 2023-03-24 | 2023-08-11 | 长鑫存储技术有限公司 | Memory debugging method, device, equipment and storage medium |
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| CN112328305A (en) * | 2020-10-30 | 2021-02-05 | 歌尔光学科技有限公司 | Eye pattern testing method and device, electronic equipment and readable storage medium |
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