CN1155160A - Method for making of self alignment silicide structural semiconductor device - Google Patents

Abstract

A method for making a semiconductor device, comprising the steps of: a. forming a metal film on a semiconductor substrate; b. using heat treatment to process the substrate so that the metal film and silicon react to form metal silicide on the gate electrode and the source/drain region Thin film; c. Etch the part that has not been silicided in the metal film; . The method is suitable for semiconductor devices with a self-aligned silicide structure, and it is possible to completely remove the metal film or metal silicide film formed on the side wall by virtue of the plasma enhanced chemical vapor deposition method.

Description

Method for preparing self-aligned silicide structure semiconductor device

The present invention relates to a method for preparing a semiconductor device, in particular to a method for preparing a semiconductor transistor with a silicide film, and the source/drain regions and gate electrodes of the silicide film of the transistor are self-aligned, that is, the The transistor has a self-aligned silicide structure.

In order to meet the requirements of high integration and small size of semiconductor devices, the gate electrode is required to be smaller in size and thinner in thickness. The source and drain regions must also be made into a thinner junction depth. This results in an increase in the resistance of the gate line. The source and drain regions will have a larger sheet resistance. In addition, the high integration of semiconductor devices will also lead to an increase in lead length, and on the other hand, semiconductors are required to have higher operating speeds. Therefore, it is no longer possible to fabricate semiconductor devices with conventional polysilicon gate electrodes to obtain desired performance.

In order to solve this problem, it has been proposed to use a self-aligned silicide (Salicide) structure. In this structure, a self-aligned metal silicide layer, such as titanium silicide, is formed on the polysilicon gate electrode and the source/drain region of the transistor, thereby reducing the resistance of the gate electrode and the source/drain region.

However, the above-mentioned salicide structure has another problem, that is, the silicon dioxide film reacts with titanium on the side wall to form titanium, although the amount is very small, but still makes the gap between the gate electrode and the source/drain region produce a short circuit current.

One measure to solve this problem is to remove the portion where the short-circuit current occurs by wet etching as suggested in Japanese Patent (Unexamined) Publication No. 4-34933. Corresponding steps in this method will be described below with reference to the cross-sectional views of FIGS. 1A to 1D .

As shown in FIG. 1A, a gate polysilicon film 3 is prepared on a silicon substrate 1, and a gate insulating film layer 2 is sandwiched between these two layers. The edge of the surface of the gate polysilicon film 3 is surrounded by a sidewall 5, and the sidewall 5 is made of insulating material. Part of the source/drain region on the silicon substrate 1 is exposed to the air. The entire product is covered with a titanium thin film 6 by sputtering or vapor deposition.

After the semiconductor substrate 1 is heat-treated, a titanium silicide film 7 is formed on the gate polysilicon film 3 and the source/drain region 4, as shown in FIG. 1B .

Then use a mixed solution of sulfuric acid and hydrogen peroxide as an etchant to remove the unreacted part 6a of the titanium film 6 by etching, although this method of removing titanium in titanium silicide has a good etching effect. Eclipse selectivity. However, there is still part 7a of the titanium silicide film 7, although the amount is very small, it still remains on the side wall 5 and has not been etched away. As shown in Figure 1C.

Thereafter, the remaining portion 7a of the titanium silicide film 7 is removed by using a mixed solution of NH ₄ OH and H ₂ O ₂ as an etchant. This solution has relatively poor etch selectivity for removing titanium from titanium silicide. Thus, the titanium silicide formed on the side wall is removed. It is thus possible to prevent a short circuit from being generated between the gate electrode 3 and the source/drain region 4 .

However, there are still two problems in the proposed scheme of the above-mentioned Japanese Patent Publication (Unexamined) No. 4-34933: the one is that while etching the titanium silicide film remaining on the side wall, the gate electrode film The titanium silicide film on the upper and source/drain regions is also etched and lost, causing the resistance of the gate electrode and the source/drain region to increase; Edge etching at the interface between the silicon substrates will also cause a further continuation of the resistance of the gate electrode and source/drain regions.

Another example is a method of manufacturing a MOS transistor proposed in Japanese Patent Laid-Open Publication No. (Unexamined) 7-99171, which can reduce sheet resistance without bridging. The method includes the following steps: making a gate electrode on a silicon substrate, making a source/drain diffusion layer, depositing a titanium film as a whole, and heat-treating the whole to form a TiSi ₂ layer, and then selectively using a mixed solution of H ₂ O ₂ and H ₂ SO ₄ Non-reactive titanium and titanium compounds are selectively etched away without removing _TiSi2 .

However, this method also has the same two problems as the above-mentioned existing first method.

An object of the present invention is to provide a method which can completely eliminate the titanium film or titanium silicide film on the side wall without increasing the resistance of the gate electrode and source/drain regions.

The invention provides a method for preparing a semiconductor device, comprising the steps of:

(1) form a metal thin film 6 on a substrate 1 whose surface includes a gate electrode 3 and the insulating spacer 5 on the side surface of the gate electrode 3 and where the source and drain regions 4 are active;

(2) make metal thin film 6 and silicon react with the method for thermally treating semiconductor substrate 1 and form a metal silicide thin film 7 on gate electrode 3 and source/drain region 4;

(3) The unsilicided part in the metal film 6 is peeled off, which is characterized in that: there is also a step (4), utilizing plasma-enhanced chemical vapor deposition (CVD) to remove the unetched part remaining on the side wall 5 The unsiliconized part is removed, and this step is carried out after step (3).

The present invention further provides a manufacturing method of a semiconductor device, including: (1) comprising a gate electrode 3 and an insulating spacer 5 on the side surface of the gate electrode 4 on one of its surfaces, and wherein the active and drain regions 4 Form metal thin film 6 on substrate 1; (2) make metal thin film 6 and silicon react with the method for thermally treating semiconductor substrate 1 and form a metal silicide thin film 7 on gate electrode 3 and source and drain region 4; It is characterized in that ( 3) The metal film 6 or the metal silicide 7 on the side wall 5 is partially removed by plasma enhanced chemical vapor deposition, and this first step (3) can be placed between steps (1) and (2), It can also be carried out after step (2).

The step of etching away the part of the metal film that has not been silicided can be performed after step (3).

For example, titanium (Ti), tantalum (Ta), molybdenum (Mo), and tungsten (W) are used for the metal thin film.

When the plasma-enhanced chemical vapor deposition method is used, a silicon dioxide film is formed on the gate electrode and the source/drain region.

When using the plasma enhanced chemical vapor deposition method, it is preferable to apply a high frequency electric field on the semiconductor substrate. Due to the plasma-enhanced chemical vapor deposition method, electron feedback resonance chemical vapor deposition (ECR-CVD) can be performed to apply microwaves to the semiconductor substrate.

The processing gas used in chemical vapor deposition is preferably an inert gas such as fluorine (Ar) gas.

According to the present invention, conductive thin films such as titanium thin films and titanium silicide thin films are removed due to the etching properties of plasma enhanced chemical vapor deposition on the inclined surface, so it is possible to prevent generation of a gap between the gate electrode and the source/drain region. short-circuit current, and will not reduce the thickness of the silicide film, and will not cause edge etching on the silicide film layer on the gate polysilicon film and the source/drain diffusion region.

In addition, when polysilicon is grown on the metal film, the gate polysilicon film and the source/drain region diffusion layer can also be prevented from disorderly changes in impurity distribution during the silicidation process.

The advantages and above or other objects of the present invention will be described in detail below with reference to the accompanying drawings, and the same reference numerals in the drawings indicate the same or similar parts.

The sectional views of Fig. 1A to 1D semiconductor device, represent each step of existing semiconductor device manufacturing method;

2A to 2D show cross-sectional views of the semiconductor device in each step of the semiconductor device manufacturing method in the first embodiment of the present invention;

The cross-sectional view of partial ECR-CVD device adopted in the embodiment of the present invention of Fig. 3;

Fig. 4 represents the graph of growth rate and etch rate and substrate incident angle interrelationship in partial ECR-CVD device;

Fig. 5 shows the graph of growth rate and etch rate and substrate incident angle interrelationship in partial ECR-CVD device;

6A to 6D show cross-sectional views of the semiconductor device in each step of the semiconductor device manufacturing method in the second embodiment of the present invention;

7A and 7B show a cross-sectional view of a semiconductor device in each step of a modified semiconductor device manufacturing method according to the second embodiment of the present invention;

8A to 8D show cross-sectional views of the semiconductor device in each step of the manufacturing method of the semiconductor device according to the third embodiment of the present invention;

9A to 9C show cross-sectional views of a semiconductor device at steps of a method according to a fourth embodiment of the present invention.

A first embodiment will be described below with reference to FIGS. 2A to 2D.

First, a gate polysilicon film 3 is formed on a silicon substrate 1 with a gate insulating film 2 sandwiched between the two layers. Then, a small dose of n-type impurities is implanted on the silicon substrate 1 by ion doping to form a diffusion layer with a low impurity concentration. Then, a silicon dioxide film is deposited on the entire substrate 1 by chemical vapor deposition (hereinafter abbreviated as CVD). The side wall 5 is formed around the edge of one surface of the gate polysilicon film 3 by back etching the silicon dioxide film by anisotropic reactive ion etching (RIE). Then, the entire substrate 1 is ion-infiltrated into n-type impurities so that the diffusion layer has a high concentration of impurities. The diffusion layer formed this time and the diffusion layer formed last time serve as the source and drain diffusion layers 4 . The side wall 5 electrically insulates the source and drain diffusion layer 4 from the gate polysilicon film 3 .

Then, a layer of titanium film 6 is deposited on the entire product by sputtering or CVD, and then heat-treated at about 750°C so as to selectively form a titanium silicide film only on the gate polysilicon film 3 and the source/drain diffusion layer 4 7, as shown in Figure 2.

Then, wet etching is used again, using a mixed solution of H ₂ SO ₄ and H ₂ O ₂ as an etchant to etch away the excess titanium that has not yet been turned into titanium silicide. However, after wet etching, the titanium silicide film 7a, as shown in FIG. 2B, still has unetched parts on the surface of the side wall 5, although the amount is very small.

At this time, a method belonging to plasma enhanced CVD, that is, electron cyclotron resonance type chemical vapor deposition (hereinafter abbreviated as ECR-CVD), is used to partially remove the titanium silicide 7a remaining on the side wall 5. .

Fig. 3 is a schematic diagram of a partial EVR=CVD device. Among them, a high-frequency bias is added to the base. As shown in the figure, the partial ECR-CVD device includes a plasma chamber 11 and a microwave inlet 12 arranged on the upper part of the plasma chamber 11 . There are also gas inlets 13 a and 13 b and a gas outlet 14 in the plasma chamber 11 . The processing gas enters the plasma chamber 11 through the gas inlets 13 a and 13 b and is discharged through the gas outlet 14 . In the plasma chamber 11 there is also a vertical substrate 15 on which the silicon substrate 1 to be processed is placed.

A high-frequency power supply 18 is connected to the substrate 15, and a high-frequency bias is applied to the substrate 15. A main coil 16 is wound around the periphery of the plasma chamber 11 . An auxiliary coil 17 is also arranged immediately under the substrate 15 . These two coils 16 and 17 establish a magnetic field in the plasma chamber 11 .

When oxygen (O ₂ ) enters the plasma chamber 11 through the gas inlet 13b, microwaves are also input into the plasma chamber 11 to generate plasma. Then, argon (Ar) and silane gas also enter the plasma chamber 11 from the gas inlet 13 a, so that a silicon dioxide film is deposited on the substrate 1 . At the same time, a high-frequency electric field is applied to the substrate 1, so that the silicon substrate 1 is etched with plasma by argon gas.

4 and 5 show the curves of film deposition rate and etching rate in partial ECR-CVD apparatus. Wherein, FIG. 4 is a graph independently showing the film deposition rate and etching rate in the partial EVR-CVD device. In fact, the net growth rate is obtained by subtracting the etch rate from the back area rate of the film, as shown in Figure 5. In Fig. 4 and Fig. 5, the silicon substrate is in a flat position, that is, the incident angle is 0°. One surface of each gate polysilicon 3 and source/drain diffusion layer 4 is upward. In the first embodiment, the film deposition rate when the silicon substrate 1 is placed flat is equal to or slightly greater than the etching rate. In FIG. 4, curve A indicates that when the silicon substrate is placed in a flat position, the film deposition rate is equal to or slightly greater than the etching rate, and the etching rate is indicated by the dotted line B.

According to the curve A ₁ in FIG. 5 , it can be understood that etching never occurs under the condition that the silicon substrate 1 is in a flat position (incident angle is 0°), so silicon dioxide is never deposited or only a small amount is deposited.

In the first embodiment, when the incident angle is 45°, that is, for the sidewall, the etch rate is greater than the film deposition rate. Therefore, the titanium silicide film 7a remaining on the side wall 5 is etched away. The specific film deposition conditions of partial ECR-CVD method are:

Silane flow: 15-30sccm

Oxygen flow: 23-45sccm

Argon flow: 70-100sccm

Microwave output power: 2000 kW

High frequency bias output power: 1400 kW

Film deposition temperature: 300-350° C. Under these conditions, the net deposition rate of the film on the flat portion of the substrate 1 was about 3000-0 angstroms/min.

Therefore, after a small amount of film deposition by the partial ECR-CVD method, when the film deposition is high enough, the etching on the side wall is very weak, and the silicon dioxide is formed at the flat position of the silicon substrate 1 by the partial ECR-CVD method. Film 8, as shown in Figure 2C. On the other hand, when the deposition rate of the film is equal to zero, the etching on the side wall 5 is relatively intensified, so the silicon dioxide film on the side wall 5 is etched away, as shown in FIG. 2D . This is because the titanium silicide film 7a remaining on the side wall 5 can be etched away during the above two processes. Thus, short-circuit current between the gate polysilicon film 3 and the source/drain diffusion layer 4 can be prevented.

Next, a second embodiment of the present invention will be described with reference to FIGS. 6A to 6D.

Similar to the first embodiment, as shown in FIG. 6A , firstly, a gate polysilicon film 3 is formed on a silicon substrate 1 with an insulating layer 2 interposed therebetween. Then, a small amount of n-type impurities is implanted onto the silicon substrate 1 by ion doping to form a diffusion layer with low impurity concentration. Then, a silicon dioxide film is deposited on the entire substrate 1 by CVD. The silicon dioxide film is then etched back by anisotropic RIE to form sidewalls 5 on the side surfaces of the gate polysilicon. Then, n-type impurities are implanted into the silicon substrate 1 by ion method to form a diffusion layer with high impurity concentration. The diffusion layer formed by this method and the diffusion layer formed by the aforementioned method will serve as the source and drain diffusion layers 4 . The side wall 5 electrically insulates the gate polysilicon film 3 and the source/drain diffusion layer 4 .

Then, a titanium film 6 is deposited on the entire product by sputtering or CVD, as shown in Fig. 6B.

Then, the titanium film 6 deposited on the side wall 5 is removed by partial ECR-CVD. This method belongs to the class of plasma-enhanced CVD methods in which a high-frequency bias is applied to the substrate 1 . The conditions for depositing a thin film using the partial ECR-CVD method are the same as those described in the first embodiment. Similar to the first embodiment, when the deposition rate of the film is increased, the silicon dioxide film 8 is deposited on the flat portion of the silicon substrate 1, as shown in FIG. 6C. On the other hand, when the film deposition rate is small, the silicon dioxide film 8 is not deposited, but the walls 5 are etched in a slope shape, as shown in FIG. 7A.

Then, the entire product is subjected to heat treatment at 750° so that the titanium silicide film 7 is formed only on the gate polysilicon film 3 and the source/drain diffusion layer 4, as shown in FIGS. 6D and 7B. Since no titanium is present on the side wall 5 in any case (FIGS. 6C and 7A), no titanium silicide film is deposited on the side wall 5 any more. Thus, there is a possibility of preventing a short-circuit current from being generated between the gate electrode 3 and the source/drain region 4 .

If part of the titanium film 6 remains unreacted on the side wall 5, they can be removed by wet etching.

Next, a third embodiment will be described with reference to Figs. 8A to 8D.

Similar to the first embodiment, as shown in FIG. 8A , a gate polysilicon film 3 is first formed on a silicon substrate 1 with a layer of gate insulating film 2 interposed therebetween. Then, a small dose of ions is used to implant n-type impurities on the substrate 1 to form a diffusion layer with low impurity concentration. Then, a silicon dioxide film is deposited on the entire silicon substrate 1 by CVD. The silicon dioxide film is etched back by the anisotropic RIE method to form side walls 5 on the side surfaces of the gate polysilicon film 3 . Then, the n-type impurity is implanted on the silicon substrate 1 by ions to form a diffusion layer with an impurity concentration. The diffusion layer thus formed and the previously formed diffusion layer serve as the source and drain diffusion layer 4 . The side wall 5 electrically insulates the gate polysilicon film 3 and the source and drain diffusion layer 4 . Then, a layer of titanium is deposited on the entire product by sputtering or CVD, as shown in FIG. 8B.

Then, the titanium film 6 deposited on the side wall 5 is removed by partial ECR-CVD. When the partial ECR-CVD method is used, a polysilicon film 9 is deposited on the gate polysilicon film 3 and the source/drain diffusion layer 4, as shown in FIG. 8 . The conditions for depositing thin films using the partial ECR-CVD method are as follows:

Silane flow: 15-25sccm

Oxygen flow: 0sccm

Argon flow: 70-100sccm

Microwave output power: 2000 kW

High frequency bias output power: 1400 kW

Film deposition temperature: 300-350°C

Then, the silicon substrate 1 is subjected to heat treatment. The titanium on the gate polysilicon film 3 and the source/drain diffusion layer 4 reacts with silicon to form a titanium silicide film 7, as shown in FIG. 8D. However, the titanium silicide film 7 is not deposited on the side wall 5 because there is no titanium on the side wall 5 . In addition, when the titanium silicide film 7 is deposited on the gate polysilicon film 3 and the source/drain diffusion layer 4, silicon in titanium diffuses into titanium to form titanium silicide. Thus, silicon already contained in the gate polysilicon film 3 and the source/drain diffusion layer 4 cannot be re-diffused into titanium. Variation of the impurity concentration in the gate polysilicon film 3 and disordering of the impurity distribution in the source/drain diffusion layer 4 are thus prevented.

If some titanium films remain unreacted on the side wall 5, they can be removed by wet etching. If some polysilicon film remains unreacted on the side wall, it can be removed by chemical dry etching.

Next, a fourth embodiment of the present invention will be described with reference to Figs. 9A to 9C.

Similar to the first embodiment, as shown in Fig. 9A. Both the gate polysilicon film 3 and the sidewall 5 are prepared on the silicon substrate 1 . A source/drain diffusion layer 4 is also prepared on the substrate 1 . The side wall 5 electrically insulates the gate polysilicon film 3 from the source/drain diffusion layer 4, and then, the titanium thin film 6 is deposited on the entire product by sputtering or CVD, and then heat-treated at 750° C. A titanium silicide film 7 is selectively formed on the polysilicon film 3 and the source/drain diffusion layer 4, as shown in FIG. 9A.

Then, the titanium film 6 is removed by using the partial ECR-CVD method under the same conditions as in the first embodiment, and there is still a very small amount of titanium silicide under the titanium film 6 .

In the partial ECR-CVD process, the silicon dioxide film 8 is deposited on the gate polysilicon film 3 and the source/drain diffusion layer 4 at a sufficiently high film deposition rate, as shown in FIG. 9B. On the other hand, when the deposition rate of the film is equal to zero, no silicon dioxide film 8 is deposited, and the side walls 5 are etched, as shown in FIG. 9C.

The present invention has been illustrated using several preferred embodiments, and it is obvious that the subject matter of the present invention is not limited to these specific embodiments. On the contrary, the subject matter of the present invention may include various types of modifications and other equivalents within the scope and meaning of the following claims.

For example, in the foregoing embodiments, although titanium is used for deposition, refractory metals such as tungsten (W), tantalum (Ta), molybdenum (Mo) and the like can replace titanium (Ti) as the metal film for deposition, thereby Corresponding metal silicide films can be made.

Furthermore, it has to be noted that the invention is also applicable to the fabrication of transistors with a single-drain structure, such as transistors with an LDD-structure.

Claims (10)

1. methods of making semiconductor devices comprises that step is:

(a) at formation one metal film (6) above the semiconductor-based end (1) once, said substrate (1) includes a gate electrode (3) in its surface, insulation abutment wall (5) that is covered with on the surface, limit of said gate electrode (3) and established therein source and drain region (4);

(b) handling the said semiconductor-based end (1) with heat treatment method reacts said metal film (6) and silicon and all form a metal silicide film (7) on said gate electrode (3) and said source and drain region (4);

(c) with in the said metal film (b) as yet not the partial etching of silication fall; It is characterized in that: step

(d) chemical vapor deposition method strengthened of using plasma is removed said abutment wall (5) in the step (c) and is gone up the residual said part of silication (7a) not as yet that does not etch away as yet, and said step (d) is being carried out after step (c).

2. one kind as the said method of claim 1, it is characterized in that: said plasma fortified chemical vapor deposition method is to be added to electron cyclotron resonace process for chemical vapor deposition of materials with via at the said semiconductor-based end (1) with microwave.

3. one kind as claim 1 or 2 said methods, it is characterized in that:

In said plasma fortified chemical vapor deposition process, there is high-frequency electric field to be added at the said semiconductor-based end (1).

4. one kind as claim 1 or 2 said methods, it is characterized in that:

With said plasma fortified chemical vapor deposition method in the said step (d), on said gate electrode (3) and said source and drain region (4), all form silica membrane (8).

5. methods of making semiconductor devices comprises step:

(a) formation one metal film (6) on a semiconductor-based end (1), said substrate (1) includes a gate electrode (3) in its surface, insulation abutment wall (5) that is covered with on the surface, limit of said gate electrode (3) and established therein source and drain region (4);

(b) handle the said semiconductor-based end (1) with heat treatment method, said metal film (6) and silicon are reacted, and on said gate electrode (3) and said source and drain region (4), all form a metal silicide film (7);

It is characterized in that: step

(c) chemical vapor deposition method of using plasma reinforcement is removed the last said metal film (6) that forms of said abutment wall (5) or the part of metal silicide film (7), said step (c) is can be arranged between step (a) and the step (b), also can be arranged in step (b) afterwards.

6. one kind as the said method of claim 5, it is characterized in that also comprising step

(d) if necessary, etch away in the said metal film (6) as yet the not part of silication (7a), said step (d) is the back that is arranged in said step (c).

7. one kind as claim 5 or 6 said methods, it is characterized in that:

Adopt said plasma fortified process for chemical vapor deposition of materials with via in the step (d), on said gate electrode (3) and said source and drain region (4), all form silica membrane (8).

8. one kind as claim 5 or 6 said methods, it is characterized in that:

When carrying out said plasma fortified chemical vapor deposition when handling, on the said semiconductor-based end (1), apply high-frequency electric field.

9. one kind as claim 5 or 6 said methods, it is characterized in that:

Wherein said plasma fortified chemical vapor deposition method is the electron cyclotron resonace chemical vapor deposition method that applies on the said semiconductor-based end (1) with microwave.

10. one kind as claim 5 or 6 said methods, it is characterized in that: wherein said metal film is with titanium (Ti), tantalum (Ta), and molybdenum (Mo), and a kind of in the tungsten (W) makes.

Images