CN115454199B - Current selection circuit - Google Patents
Current selection circuit Download PDFInfo
- Publication number
- CN115454199B CN115454199B CN202211148653.5A CN202211148653A CN115454199B CN 115454199 B CN115454199 B CN 115454199B CN 202211148653 A CN202211148653 A CN 202211148653A CN 115454199 B CN115454199 B CN 115454199B
- Authority
- CN
- China
- Prior art keywords
- current
- transistor
- input
- terminal
- bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is DC
- G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
Abstract
The invention discloses a current selection circuit, which comprises a first current source, a second current source and a first bias current source, wherein the first current source outputs a first bias current; a second current source outputting a second bias current; the first current branch is connected between the output end of the first current source and the ground, and is provided with a first current input end for receiving a first input current; the second current branch is connected between the output end of the second current source and the ground, and is provided with a second current input end for receiving a second input current; the third current branch circuit obtains a first mirror current through mirroring the first input current and the first bias current flowing through the first current branch circuit, obtains a second mirror current through mirroring the second input current and the second bias current flowing through the second current branch circuit, and comprises a current output end, wherein the current output end provides an output current which is smaller than the first mirror current and the second mirror current, so that the power consumption is reduced while the input voltage range of the current input end is effectively increased.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a current selection circuit.
Background
In integrated circuit designs, it is often necessary to compare the magnitudes of two currents, such as selecting the larger of the two currents as the output current, or the smaller of the two currents as the output current. The current selection circuit commonly used at present needs to be converted by a current mirror for several times, and the voltage range of the input voltage of the current input terminal is smaller.
Fig. 1 shows a schematic diagram of a current selection circuit according to the prior art. As shown in fig. 1, the conventional current selection circuit includes transistors M1-M9, an input current I1 is input to the control terminal and the first terminal of the transistor M1 and the control terminal of the transistor M2, an input current I2 is input to the control terminal and the first terminal of the transistor M8 and the control terminal of the transistor M9, and an output current Imin is provided from an intermediate node of the transistor M4 connected to the first terminal of the transistor M7, and is a smaller value of the input current I1 and the input current I2. Wherein, the width-to-length ratio of the transistors M1-M9 is 1:1, when the input current I1 is greater than the input current I2, the first terminal current of the transistor M3 is equal to the difference between the input current I2 and the input current I1, the first terminal voltage of the transistor M3 is approximately equal to the ground terminal voltage GND, and the output current Imin is equal to the first terminal current of the transistor M7 and is equal to the input current I2; when the input current I1 is smaller than the input current I2, the first terminal currents of the transistor M3 and the transistor M4 are equal to the difference between the input current I2 and the input current I1, the output current Imin is equal to the difference between the first terminal current of the transistor M7 and the first terminal current of the transistor M4 is equal to the input current I1, and thus the minimum current selection is achieved.
Under normal conditions, the minimum voltage of the input voltage Vin at the current input end of the current selection circuit shown in fig. 1 needs to be greater than the threshold voltage of the MOS transistor, i.e. the minimum voltage of the input voltage Vin is about equal to 0.7V. If the direction of the input current is reversed, the highest voltage of the input voltage Vin at the current input terminal is approximately equal to VDD-0.7V. The input current of the current selection circuit can be mirrored for multiple times to output the output current Imin, so that the power consumption is high. Therefore, a new current selection circuit has to be proposed to solve the above-mentioned problems.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a current selection circuit, whereby power consumption can be reduced while effectively increasing the voltage range of the input voltage of the current input terminal.
According to an aspect of the present invention, there is provided a current selection circuit including: the input end of the first current source is connected with the power supply, and the output end of the first current source is used for outputting a first bias current; the input end of the second current source is connected with the power supply, and the output end of the second current source is used for outputting second bias current; a first current branch connected between an output of the first current source and ground, the first current branch having a first current input for receiving a first input current; a second current branch connected between the output of the second current source and ground, the second current branch having a second current input for receiving a second input current; and a third current branch, wherein a first mirror current is obtained by mirroring the first input current flowing through the first current branch and the first bias current, and a second mirror current is obtained by mirroring the second input current flowing through the second current branch and the second bias current, and the third current branch further comprises a current output end for providing an output current, and the output current is a smaller value of the first mirror current and the second mirror current.
Optionally, the first current branch includes: and a third transistor and a first transistor sequentially connected between an output terminal of the first current source and ground, wherein a common node of the third transistor and the first transistor is used as the first current input terminal to receive the first input current, a control terminal of the third transistor is used for receiving a bias voltage, and a control terminal of the first transistor is connected with a first terminal of the third transistor.
Optionally, the second current branch includes: and a sixth transistor and a fifth transistor sequentially connected between the output terminal of the second current source and ground, wherein a common node of the sixth transistor and the fifth transistor is used as the second current input terminal to receive the second input current, a control terminal of the sixth transistor is used for receiving a bias voltage, and a control terminal of the fifth transistor is connected with the first terminal of the sixth transistor.
Optionally, the third current branch includes: the control end of the second transistor is connected with the control end of the first transistor, the first end of the second transistor is connected with the second end of the fourth transistor, the control end of the fourth transistor is connected with the control end of the fifth transistor, and the first end of the fourth transistor is used as the current output end.
Optionally, the first to sixth transistors are NMOS transistors.
Optionally, the first transistor, the second transistor, the fourth transistor, and the fifth transistor have equal width-length dimensions.
Optionally, the first bias current is equal to the second bias current, the first bias current is substantially less than the first input current, and the second bias current is substantially less than the second input current.
Optionally, the current selection circuit is configured to: when the first input current is larger than the second input current, the first end current of the second transistor is larger than the first end current of the fourth transistor, so that the first end voltage of the second transistor is equal to the ground end voltage, the second transistor enters a linear region, and the current output end outputs the second input current; when the first input current is smaller than the second input current, the first end current of the second transistor is smaller than the first end current of the fourth transistor, so that the current output end outputs the first input current.
Optionally, the size ratio of the first transistor and the second transistor is equal to the size ratio of the fifth transistor and the fourth transistor.
Optionally, a current value ratio of the first bias current to the second bias current is equal to a size ratio of the first transistor and the fifth transistor.
According to the current selection circuit provided by the embodiment of the invention, the first input current and the first bias current of the third current branch mirror image flow through the first current branch to obtain the first mirror current, the second input current and the second bias current of the mirror image flow through the second current branch to obtain the second mirror current, and the current output end provides the output current which is smaller value of the first mirror current and the second mirror current, the first input current and the second input current can realize minimum current selection only by one mirror image, the circuit structure is simple, the current mirror image times are less, and the power consumption is lower.
In a preferred embodiment, the first input current is input only by the first end of the first transistor, and the second input current is input only by the first end of the fifth transistor, so that the voltage range of the input voltage of the current input end is enlarged, and the current selection circuit provided by the embodiment of the invention can be suitable for an integrated circuit with higher requirement on the input voltage of the current input end.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 shows a schematic diagram of a current selection circuit according to the prior art;
fig. 2 shows a schematic diagram of a structure of a current selection circuit according to an embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. The same elements or modules are denoted by the same or similar reference numerals in the various figures. For clarity, the various features of the drawings are not drawn to scale.
It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" another element or circuit is "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.
Also, certain terms are used throughout the description and claims to refer to particular components. It will be appreciated by those of ordinary skill in the art that a hardware manufacturer may refer to the same component by different names. The present patent specification and claims do not take the form of an element or components as a functional element or components as a rule.
It should also be noted that in this document relational terms such as first and second are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Fig. 2 shows a schematic diagram of a structure of a current selection circuit according to an embodiment of the present invention. As shown in fig. 2, the current selection circuit 100 includes a first current source 111, a second current source 112, a first current branch 113, a second current branch 114, and a third current branch 115.
The first current source 111 has an input terminal connected to the power supply VDD and an output terminal for providing the bias current I3.
The second current source 112 has an input terminal connected to the power supply VDD and an output terminal for providing the bias current I4.
The first current branch 113 is connected between the output terminal of the first current source 111 and the ground GND, and has a first current input terminal a for receiving the input current I1.
The second current branch 114 is connected between the output terminal of the second current source 112 and the ground GND, and has a second current input terminal B for receiving the input current I2.
The third current branch 115 obtains a first mirror current by mirroring the input current I1 and the bias current I3 flowing through the first current branch 113, and obtains a second mirror current by mirroring the input current I2 and the bias current I4 flowing through the second current branch 114. The third current branch 115 further includes a current output terminal for providing an output current Imin, which is a smaller value of the first mirror current and the second mirror current.
The first current branch 113 includes a transistor M3 and a transistor M1 sequentially connected between an output terminal of the first current source 111 and the ground terminal GND, a common node of the transistor M3 and the transistor M1 is used as a first current input terminal a to receive the input current I1, a control terminal of the transistor M3 is used to receive an externally provided bias voltage Vb, so that the transistor M3 and the transistor M1 operate in a saturation region, and a control terminal of the transistor M1 is connected to the first terminal of the transistor M3.
The second current branch 114 includes a transistor M6 and a transistor M5 sequentially connected between an output terminal of the second current source 112 and the ground terminal GND, a common node of the transistor M6 and the transistor M5 is used as a second current input terminal B to receive the input current I2, a control terminal of the transistor M6 is used to receive an externally provided bias voltage Vb, so that the transistor M6 and the transistor M5 operate in a saturation region, and a control terminal of the transistor M5 is connected to a first terminal of the transistor M6.
The third current branch 115 includes a transistor M2 and a transistor M4 sequentially connected between the current output terminal and the ground terminal GND, where the control terminal of the transistor M2 is connected to the control terminal of the transistor M1, the first terminal of the transistor M2 is connected to the second terminal of the transistor M4, the control terminal of the transistor M4 is connected to the control terminal of the transistor M5, and the first terminal of the transistor M4 is used as the current output terminal.
Since the control terminal voltage of the transistor M1 is provided by the output terminal of the first current source 111, the input current I1 is only input by the first terminal of the transistor M1, so that the input voltage Vin of the first current input terminal a only needs to provide the voltage difference Vds1 between the first terminal and the second terminal of the transistor M1, i.e. the lowest voltage of the input voltage Vin of the first current input terminal a is Vds1, and if the direction of the input current I1 is reversed, the highest voltage of the input voltage Vin of the first current input terminal a is VDD-Vds1. Similarly, the lowest voltage of the input voltage Vin of the second current input terminal B is Vds5, and when the direction of the input current I2 is reversed, the highest voltage of the input voltage Vin of the second current input terminal B is equal to VDD-Vds5.
The voltage difference Vds between the first terminal and the second terminal is generally about 200mV when the transistor operates in the saturation region, and because the transistor M1 and the transistor M5 of the present application operate in the saturation region under the bias voltage Vb, the minimum voltage of the input voltage Vin required by the first current input terminal a and the second current input terminal B of the present application is about 200mV, and the maximum voltage of the input voltage Vin of the first current input terminal a and the second current input terminal B is about VDD-200mV when the directions of the input current I1 and the input current I2 are reversed. Therefore, the voltage range of the input voltage Vin of the first current input terminal a and the second current input terminal B of the current selection circuit 100 provided in the present embodiment is about 200mV to VDD-200mV, and compared with the prior art of 0.7V to VDD-0.7V, the voltage range of the input voltage Vin is larger, which can be applied to an integrated circuit with higher requirements on the input voltage Vin of the current input terminal.
When the width and length dimensions of the transistor M1, the transistor M2, the transistor M4 and the transistor M5 are equal, the current values of the bias current I3 and the bias current I4 are equal, the bias current I3 is far smaller than the input current I1, and the bias current I4 is far smaller than the input current I2, the first mirror current mirrored by the transistor M2 is equal to the sum of the input current I1 and the bias current I3, and the second mirror current mirrored by the transistor M4 is equal to the sum of the input current I2 and the bias current I4.
When the input current I1 is greater than the input current I2, the first mirror current, i.e., the first end current of the transistor M2, is greater than the second mirror current, i.e., the first end current of the transistor M4, such that the second end voltage of the transistor M4, i.e., the first end voltage of the transistor M2, is approximately equal to the ground end voltage GND, the transistor M2 enters a linear region, the output current Imin is equal to the sum of the input current I2 and the bias current I4, and since the bias current I4 is far less than the input current I2, it can be ignored, and therefore the output current Imin is equal to the input current I2; when the input current I2 is greater than the input current I1, the first terminal current of the transistor M2 is smaller than the first terminal current of the transistor M4, so that the output current Imin is equal to the sum of the input current I1 and the bias current I3, and since the bias current I3 is far smaller than the input current I1 and can be ignored, the output current Imin is equal to the input current I1, thereby realizing the minimum current selection.
Further, the transistors M1-M6 are of the same type and are all N-channel MOSFE (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-Oxide semiconductor field effect transistor), simply NMOS.
Further, the transistors M1-M6 are of the same type and are P-channel MOSFE (Metal-Oxide-Semiconductor Field-Effect Transistor, PMOS for short).
Further, the transistors M1-M6 may be partly NMOS transistors and partly PMOS transistors.
Further, the first ends of the transistors M1-M6 are drain ends, the second ends are source ends, and vice versa.
In this embodiment, the ratio of the width to the length of the transistors M1, M2, M4 and M5 is 1:1, the current value ratio of the bias current I3 to the bias current I4 is 1:1 is described as an example, but the present invention is not limited to the ratio of the width to the length of the transistors M1, M2, M4, and M5 and the ratio of the current values of the bias current I3 and the bias current I4, and for example, m1:m2=m5:m4, i3:i4=m1:m5 may be satisfied, and the circuit may output a current proportional to a small input current.
According to the current selection circuit provided by the embodiment of the invention, the third current branch 115 mirrors the input current I1 and the bias current I3 flowing through the first current branch 113 to obtain the first mirror current, the input current I2 and the bias current I4 mirror the input current flowing through the second current branch 114 to obtain the second mirror current, and the current output end provides the output current Imin, wherein the output current Imin is a smaller value in the first mirror current and the second mirror current, the minimum current selection can be realized by only one mirror image of the input current I1 and the input current I2, the circuit structure is simple, the input current mirror frequency is less, and the power consumption is lower.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The scope of the invention should be determined by the appended claims and their equivalents.
Claims (8)
1. A current selection circuit, comprising:
the input end of the first current source is connected with the power supply, and the output end of the first current source is used for outputting a first bias current;
the input end of the second current source is connected with the power supply, and the output end of the second current source is used for outputting second bias current;
a first current branch connected between an output of the first current source and ground, the first current branch having a first current input for receiving a first input current;
a second current branch connected between the output of the second current source and ground, the second current branch having a second current input for receiving a second input current; and
a third current branch for obtaining a first mirror current by mirroring the first input current and the first bias current flowing through the first current branch, and for obtaining a second mirror current by mirroring the second input current and the second bias current flowing through the second current branch,
wherein the third current branch further comprises a current output terminal for providing an output current, the output current being the smaller of the first and second mirrored currents,
the first current branch includes: a third transistor and a first transistor sequentially connected between an output terminal of the first current source and ground, wherein a common node of the third transistor and the first transistor is used as the first current input terminal to receive the first input current, a control terminal of the third transistor is used for receiving a bias voltage, a control terminal of the first transistor is connected with a first terminal of the third transistor,
the second current branch includes: and a sixth transistor and a fifth transistor sequentially connected between the output terminal of the second current source and ground, wherein a common node of the sixth transistor and the fifth transistor is used as the second current input terminal to receive the second input current, a control terminal of the sixth transistor is used for receiving a bias voltage, and a control terminal of the fifth transistor is connected with the first terminal of the sixth transistor.
2. The current selection circuit of claim 1, wherein the third current branch comprises:
a second transistor and a fourth transistor connected in turn between the current output terminal and ground,
the control end of the second transistor is connected with the control end of the first transistor, the first end of the second transistor is connected with the second end of the fourth transistor, the control end of the fourth transistor is connected with the control end of the fifth transistor, and the first end of the fourth transistor serves as the current output end.
3. The current selection circuit of claim 2, wherein the first to sixth transistors are NMOS transistors.
4. The current selection circuit of claim 3, wherein the first transistor, the second transistor, the fourth transistor, and the fifth transistor are equal in width-length dimension.
5. The current selection circuit of claim 4, wherein the first bias current is equal to the second bias current, the first bias current being substantially less than the first input current, the second bias current being substantially less than the second input current.
6. The current selection circuit of claim 5, wherein the current selection circuit is configured to:
when the first input current is larger than the second input current, the first end current of the second transistor is larger than the first end current of the fourth transistor, so that the first end voltage of the second transistor is equal to the ground end voltage, the second transistor enters a linear region, and the current output end outputs the second input current;
when the first input current is smaller than the second input current, the first end current of the second transistor is smaller than the first end current of the fourth transistor, and the current output end outputs the first input current.
7. The current selection circuit of claim 3, wherein a size ratio of the first transistor and the second transistor is equal to a size ratio of the fifth transistor and the fourth transistor.
8. The current selection circuit of claim 7, wherein a current value ratio of the first bias current to the second bias current is equal to a size ratio of the first transistor and the fifth transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211148653.5A CN115454199B (en) | 2022-09-20 | 2022-09-20 | Current selection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211148653.5A CN115454199B (en) | 2022-09-20 | 2022-09-20 | Current selection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115454199A CN115454199A (en) | 2022-12-09 |
| CN115454199B true CN115454199B (en) | 2024-02-06 |
Family
ID=84305250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211148653.5A Active CN115454199B (en) | 2022-09-20 | 2022-09-20 | Current selection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115454199B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101067753A (en) * | 2007-06-01 | 2007-11-07 | 华中科技大学 | Electric power bias circuit with negative feedback |
| CN102654828A (en) * | 2011-06-30 | 2012-09-05 | 上海新进半导体制造有限公司 | Method for increasing response speed of analog adder, analog adder and transformer |
| CN105739586A (en) * | 2016-04-01 | 2016-07-06 | 深圳还是威健康科技有限公司 | Current reference source circuit |
| CN106774584A (en) * | 2017-02-14 | 2017-05-31 | 上海华虹宏力半导体制造有限公司 | A kind of current-mode current minimum circuit |
| CN110045779A (en) * | 2019-03-27 | 2019-07-23 | 华中科技大学 | A kind of voltage selecting circuit and method |
| CN111897390A (en) * | 2020-08-13 | 2020-11-06 | 上海南芯半导体科技有限公司 | Current selection circuit and method thereof |
| CN112448379A (en) * | 2019-09-04 | 2021-03-05 | 圣邦微电子（北京）股份有限公司 | Surge protection circuit |
| CN112886931A (en) * | 2021-01-28 | 2021-06-01 | 深圳市万微半导体有限公司 | Digital weighted current source circuit for eliminating offset error of operational amplifier |
| CN112904931A (en) * | 2021-01-15 | 2021-06-04 | 北京智芯微电子科技有限公司 | Voltage-current conversion circuit and integrated circuit chip |
| CN216670106U (en) * | 2021-09-16 | 2022-06-03 | 南京沁恒微电子股份有限公司 | Power switch overcurrent detection circuit and current detection circuit |
| CN114690842A (en) * | 2020-12-29 | 2022-07-01 | 圣邦微电子（北京）股份有限公司 | Current source circuit for biasing bipolar transistor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109062317B (en) * | 2018-09-07 | 2020-08-07 | 无锡华润矽科微电子有限公司 | Constant current driving circuit and corresponding photoelectric smoke alarm circuit |
-
2022
- 2022-09-20 CN CN202211148653.5A patent/CN115454199B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101067753A (en) * | 2007-06-01 | 2007-11-07 | 华中科技大学 | Electric power bias circuit with negative feedback |
| CN102654828A (en) * | 2011-06-30 | 2012-09-05 | 上海新进半导体制造有限公司 | Method for increasing response speed of analog adder, analog adder and transformer |
| CN105739586A (en) * | 2016-04-01 | 2016-07-06 | 深圳还是威健康科技有限公司 | Current reference source circuit |
| CN106774584A (en) * | 2017-02-14 | 2017-05-31 | 上海华虹宏力半导体制造有限公司 | A kind of current-mode current minimum circuit |
| CN110045779A (en) * | 2019-03-27 | 2019-07-23 | 华中科技大学 | A kind of voltage selecting circuit and method |
| CN112448379A (en) * | 2019-09-04 | 2021-03-05 | 圣邦微电子（北京）股份有限公司 | Surge protection circuit |
| CN111897390A (en) * | 2020-08-13 | 2020-11-06 | 上海南芯半导体科技有限公司 | Current selection circuit and method thereof |
| CN114690842A (en) * | 2020-12-29 | 2022-07-01 | 圣邦微电子（北京）股份有限公司 | Current source circuit for biasing bipolar transistor |
| CN112904931A (en) * | 2021-01-15 | 2021-06-04 | 北京智芯微电子科技有限公司 | Voltage-current conversion circuit and integrated circuit chip |
| CN112886931A (en) * | 2021-01-28 | 2021-06-01 | 深圳市万微半导体有限公司 | Digital weighted current source circuit for eliminating offset error of operational amplifier |
| CN216670106U (en) * | 2021-09-16 | 2022-06-03 | 南京沁恒微电子股份有限公司 | Power switch overcurrent detection circuit and current detection circuit |
Non-Patent Citations (1)
| Title |
|---|
| 董昕.数模电路应用基础.北京理工大学出版社 ,2016,51-54. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115454199A (en) | 2022-12-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5470128B2 (en) | Constant voltage circuit, comparator and voltage monitoring circuit using them | |
| KR100393226B1 (en) | Internal reference voltage generator capable of controlling value of internal reference voltage according to temperature variation and internal power supply voltage generator including the same | |
| US10707757B2 (en) | Reference voltage generator with adaptive voltage and power circuit | |
| US5959446A (en) | High swing current efficient CMOS cascode current mirror | |
| JP4800781B2 (en) | Voltage level shift circuit and semiconductor integrated circuit | |
| US20170139435A1 (en) | Low voltage current mode bandgap circuit and method | |
| JP2008015925A (en) | Reference voltage generation circuit | |
| KR100967365B1 (en) | Semiconductor integrated circuit device | |
| JP2005018783A (en) | Current source for generating a constant reference current | |
| US6630818B1 (en) | Current mirror circuits | |
| CN115454199B (en) | Current selection circuit | |
| JP2000278053A (en) | Bias circuit | |
| US20040041623A1 (en) | Process-compensated CMOS current reference | |
| US7522003B2 (en) | Constant margin CMOS biasing circuit | |
| JP5974998B2 (en) | Operational amplifier | |
| CN115437454B (en) | Current mirror circuit | |
| US5847606A (en) | Low voltage CMOS amplifier output stage | |
| CN108628379B (en) | Bias circuit | |
| EP0367578A1 (en) | CMOS compatible bandgap voltage reference | |
| US20030231050A1 (en) | Method of forming a reference voltage from a J-fet | |
| JP2985673B2 (en) | Delay circuit | |
| CN116243750B (en) | Voltage stabilizer circuit, chip and electronic equipment | |
| US11320851B1 (en) | All-MOSFET voltage reference circuit with stable bias current and reduced error | |
| JP2020136716A (en) | Load current detection circuit | |
| US7233175B2 (en) | Amplitude limiting circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |