CN115442848B - Base station interface module and base station - Google Patents
Base station interface module and base station Download PDFInfo
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- CN115442848B CN115442848B CN202110610842.9A CN202110610842A CN115442848B CN 115442848 B CN115442848 B CN 115442848B CN 202110610842 A CN202110610842 A CN 202110610842A CN 115442848 B CN115442848 B CN 115442848B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W28/00—Network traffic management; Network resource management
- H04W28/02—Traffic management, e.g. flow control or congestion control
- H04W28/04—Error control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
- H04W88/08—Access point devices
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Abstract
本申请实施例提供一种基站接口模块及基站，所述基站接口模块包括：通用公共无线电接口、高速串行接口、第一加扰模块和前向纠错编码模块；通用公共无线电接口的第一输出端与第一加扰模块的输入端连接；第一加扰模块的输出端与前向纠错编码模块的输入端连接；前向纠错编码模块的输出端与高速串行接口的输入端连接；其中，第一加扰模块用于对S码、T码和被加扰数据进行加扰。本申请实施例提供的基站接口模块及基站，在加扰模块和高速串行接口之间增加前向纠错编码模块，降低了线速率较高的应用场景下的误码率，提高了AAU与BBU数据交互的稳定性。
The embodiment of the present application provides a base station interface module and a base station, the base station interface module includes: a universal public radio interface, a high-speed serial interface, a first scrambling module and a forward error correction coding module; the first output end of the universal public radio interface is connected to the input end of the first scrambling module; the output end of the first scrambling module is connected to the input end of the forward error correction coding module; the output end of the forward error correction coding module is connected to the input end of the high-speed serial interface; wherein the first scrambling module is used to scramble the S code, T code and scrambled data. The base station interface module and the base station provided by the embodiment of the present application add a forward error correction coding module between the scrambling module and the high-speed serial interface, which reduces the bit error rate in application scenarios with high line rates and improves the stability of data interaction between the AAU and the BBU.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a base station interface module and a base station.
Background
The active antenna Unit (ACTIVE ANTENNA Unit, AAU) is connected with the indoor baseband Unit (Building Baseband Unite, BBU) through optical fibers, uplink data are sent to the BBU through the AAU, and downlink data are sent to the AAU through the BBU.
Existing base station interface schemes typically pack data according to the common public radio interface (Common Public Radio Interface, CPRI) protocol.
However, in the existing base station interface scheme, for an application scene with higher linear velocity, the base station can generate error codes, and long-term stable operation of the base station is affected.
Disclosure of Invention
The embodiment of the application provides a base station interface module and a base station, which are used for solving the technical problem of poor stability of the base station in the prior art.
In a first aspect, an embodiment of the present application provides a base station interface module, including:
a common public radio interface, a high-speed serial interface, a first scrambling module and a forward error correction coding module;
a first output end of the universal public radio interface is connected with an input end of the first scrambling module;
The output end of the first scrambling module is connected with the input end of the forward error correction coding module;
The output end of the forward error correction coding module is connected with the input end of the high-speed serial interface;
The first scrambling module is used for scrambling S codes, T codes and scrambled data.
Optionally, the system further comprises a second scrambling module and a first selector;
A second output end of the universal public radio interface is connected with an input end of the second scrambling module;
the output end of the forward error correction coding module is connected with the input end of the high-speed serial interface through the first selector;
The output end of the forward error correction coding module is connected with the first input end of the first selector;
the output end of the second scrambling module is connected with the second input end of the first selector;
the output end of the first selector is connected with the input end of the high-speed serial interface;
When the enabling end of the first selector is in a first state, the output end of the forward error correction coding module is conducted with the input end of the high-speed serial interface;
when the enabling end of the first selector is in a second state, the output end of the second scrambling module is conducted with the input end of the high-speed serial interface;
The second scrambling module is used for scrambling the scrambled data.
Optionally, the system further comprises a first descrambling module and a forward error correction decoding module;
The first output end of the high-speed serial interface is connected with the input end of the forward error correction decoding module;
The output end of the forward error correction decoding module is connected with the input end of the first descrambling module;
the output end of the first descrambling module is connected with the input end of the universal public radio interface;
the first descrambling module is used for descrambling S codes, T codes and descrambled data.
Optionally, the system further comprises a second descrambling module and a second selector;
The second output end of the high-speed serial interface is connected with the input end of the second descrambling module;
The output end of the first descrambling module is connected with the input end of the universal public radio interface through the second selector;
the output end of the second selector is connected with the input end of the universal public radio interface;
when the enabling end of the second selector is in a first state, the output end of the first descrambling module is conducted with the input end of the universal public radio interface;
when the enabling end of the second selector is in a second state, the output end of the second descrambling module is conducted with the input end of the universal public radio interface;
the second descrambling module is used for descrambling the descrambled data.
Optionally, the forward error correction coding module is a reed-solomon code coding module.
Optionally, the forward error correction decoding module is a reed-solomon code decoding module.
Optionally, the forward error correction coding module is implemented by a soft core.
Optionally, the forward error correction decoding module is implemented by a hard core.
Optionally, the forward error correction decoding module comprises a frequency conversion sub-module;
the frequency conversion submodule is used for carrying out frequency conversion processing on the differential input clock so as to generate the clock of the forward error correction decoding module.
In a second aspect, an embodiment of the present application provides a base station, including the base station interface module described in the first aspect.
According to the base station interface module and the base station, the forward error correction coding module is added between the scrambling module and the high-speed serial interface, so that the error rate in an application scene with higher linear rate is reduced, and the stability of AAU and BBU data interaction is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of AAU to BBU connections;
fig. 2 is a schematic diagram of a CPRI frame structure;
FIG. 3 is a schematic diagram of a BBU interface framework;
fig. 4 is a schematic diagram of an overall framework of a base station interface module according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a clock module provided by an embodiment of the present application;
fig. 6 is a comparison chart of bit error rates provided by an embodiment of the present application.
Detailed Description
FIG. 1 is a schematic diagram of the connection of an AAU to a BBU, as shown in FIG. 1, the AAU and BBU are connected by optical fibers. Uplink data is sent to the BBU through the AAU, and downlink data is sent to the AAU through the BBU. The stability of the optical port is important for the operation of the base station, and the existing scheme also adopts a series of measures to improve the stability of the optical port and monitor the state of the optical port.
Fig. 2 is a schematic diagram of a CPRI frame structure, and as shown in fig. 2, the conventional base station interface scheme generally packages data according to a common public radio interface (Common Public Radio Interface, CPRI) protocol.
The optical port rate is relatively high, and in order to improve the utilization rate of the line rate, 64/66B coding is generally adopted, and the AAU and the BBU adopt the same scrambling and descrambling polynomials and scrambling and descrambling initial values.
And monitoring the state of the optical port by detecting a control word in the data. Fig. 3 is a schematic diagram of a BBU interface framework, as shown in fig. 3, that is a BBU interface general framework, with the AAU interface framework being mirror symmetrical to the BBU interface framework. TRANSCEIVER IP cores are transceiver intellectual property cores, asy_gecarbox is an asynchronous transmission, which is one of the modules in TRANSCEIVER IP that implements the encoding function.
In the existing interface scheme, the base station interface is very stable and reliable under the application scene with low line speed, such as 10G optical port line speed, but for the application scene with higher line speed, the base station can generate error codes, and the long-term stable operation of the base station is affected, such as the 25G optical port commonly used by the existing base station.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Fig. 4 is a schematic diagram of an overall frame of a base station interface module according to an embodiment of the present application, and as shown in fig. 4, the base station interface module according to an embodiment of the present application includes:
A common public radio interface 401, a high-speed serial interface 402, a first scrambling module 403 and a forward error correction coding module 404;
a first output of the common public radio interface 401 is connected to an input of the first scrambling module 403;
The output end of the first scrambling module 403 is connected with the input end of the forward error correction coding module 404;
An output of the forward error correction encoding module 404 is connected to an input of the high-speed serial interface 402;
Wherein, the first scrambling module 403 is configured to scramble the S code, the T code, and the scrambled data.
Specifically, the first scrambling module 403 performs scrambling using a standard protocol, and the forward error correction coding module 404 may be a Reed-Solomon (RS) code coding module. The forward error correction coding module 404 is implemented by a soft core.
The scrambling and descrambling module of the existing base station interface uses a scrambling polynomial consistent with a standard protocol. The scrambling and descrambling module of the existing base station interface does not adopt the self-synchronous scrambling of the standard protocol.
In the embodiment of the application, scrambling processing is carried out on the data to be scrambled, scrambling processing is carried out on the S code and the T code, and the application is a self-synchronizing scrambling code structure, namely, the scrambling code is generated by the scrambled data and polynomials together.
Optionally, a second scrambling module 405 and a first selector 406 are also included;
A second output of the common public radio interface 401 is connected to an input of the second scrambling module 405;
an output of the forward error correction encoding module 404 is connected to an input of the high-speed serial interface 402 through the first selector 406;
an output of the forward error correction encoding module 404 is coupled to a first input of the first selector 406;
An output terminal of the second scrambling module 405 is connected to a second input terminal of the first selector 406;
an output of the first selector 406 is connected to an input of the high-speed serial interface 402;
When the enable end of the first selector 406 is in the first state, the output end of the fec encoding module 404 is connected to the input end of the high-speed serial interface 402;
When the enable end of the first selector 406 is in the second state, the output end of the second scrambling module 405 is connected to the input end of the high-speed serial interface 402;
Wherein the second scrambling module 405 is configured to scramble the scrambled data.
Specifically, as shown in fig. 4, the base station interface module in the embodiment of the present application further includes a second scrambling module 405, where the second scrambling module 405 scrambles by adopting an original scrambling manner in the existing scheme, that is, only scrambles the scrambled data.
When the enable terminal of the first selector 406 is in the first state, the output terminal of the fec encoding module 404 is connected to the input terminal of the high-speed serial interface 402, and scrambling is performed using standard protocol.
When the enabling end of the first selector 406 is in the second state, the output end of the second scrambling module 405 is connected to the input end of the high-speed serial interface 402, and the original scrambling mode in the existing scheme is adopted for scrambling.
For example, a switching register is employed as the first selector 406. A switching register is provided for the drop port to control forward error correction (Forward Error Correction, FEC) (meaning that RS coding is added, i.e. forward error correction is introduced) and non-forward error correction code (non-FEC) switching.
On the encoding side, FEC encoded data and non-FEC encoded data are output simultaneously, and a field programmable gate array (Field Programmable GATE ARRAY, FPGA) for Gigabit (Gigabit) application of a GTY (high-speed serial interface), commonly referred to as Gigabit transceiver Gigabit Transceiver (GTx), includes a GTP, GTR, GTX, GTH, GTZ, GTY, GTM (increasing transmission rate) portal, is basically integrated with some high-speed serial interfaces, and performs data source switching according to a switching register configuration.
Optionally, a first descrambling module 407 and a forward error correction decoding module 408 are also included;
A first output of the high-speed serial interface 402 is coupled to an input of the forward error correction decoding module 408;
An output end of the forward error correction decoding module 408 is connected with an input end of the first descrambling module 407;
An output of the first descrambling module 407 is connected to an input of the common public radio interface 401;
the first descrambling module 407 is configured to descramble the S code, the T code, and the descrambled data.
Specifically, as shown in fig. 4, the first descrambling module 407 in the base station interface module in the embodiment of the present application adopts a standard protocol for descrambling, and the forward error correction decoding module 408 may be a reed-solomon (RS) code decoding module. The forward error correction decoding module 408 is implemented by a hard core.
Optionally, a second descrambling module 409 and a second selector 410 are also included;
A second output terminal of the high-speed serial interface 402 is connected to an input terminal of the second descrambling module 409;
An output of the first descrambling module 407 is connected to an input of the common public radio interface 401 through the second selector 410;
An output of the second selector 410 is connected to an input of the common public radio interface 401;
When the enable terminal of the second selector 410 is in the first state, the output terminal of the first descrambling module 407 is conducted with the input terminal of the common public radio interface 401;
When the enable terminal of the second selector 410 is in the second state, the output terminal of the second descrambling module 409 is conducted with the input terminal of the common public radio interface 401;
wherein, the second descrambling module 409 is configured to descramble the descrambled data.
Specifically, as shown in fig. 4, in the embodiment of the present application, the second descrambling module 409 in the base station interface module descrambles by adopting the original descrambling manner in the existing scheme, that is, only descrambled data.
When the enable terminal of the second selector 410 is in the first state, the output terminal of the first descrambling module 407 is conducted with the input terminal of the common public radio interface 401, and descrambling is performed using a standard protocol.
When the enabling terminal of the second selector 410 is in the second state, the output terminal of the second descrambling module 409 is connected to the input terminal of the common public radio interface 401, and the original descrambling mode in the existing scheme is adopted for descrambling.
For example, a switching register is employed as the second selector 410. A switching register is provided for the drop ports to control FEC and non-FEC switching.
The decoding side, the hard core outputs FEC coding and non-FEC coding data under the same clock domain, the non-FEC is descrambled and then is subjected to data source switching according to the configuration type of a register, and the gecarbox sliding code signal is switched (the signal fed back to the TRANSCEIVER IP core is used for informing a transmitter sliding code, and when FEC is enabled, the used sliding code signals are different and are switched).
Optionally, the forward error correction decoding module 408 includes a frequency conversion sub-module;
the frequency conversion sub-module is configured to perform frequency conversion processing on the differential input clock to generate a clock of the fec decoding module 408.
Specifically, fig. 5 is a schematic diagram of a clock module provided in the embodiment of the present application, and as shown in fig. 5, an existing base station interface is 2 clock domains, and in the embodiment of the present application, 3 clock domains of a data channel are adopted. The encoding side, each channel and before the same only one clock domain (gt_tx_clk refers to TX_CLK_OUT_CHX (clock domain name)); on the decode side, one hard core output is added as rx_fast_clk clock domain (clock domain for added feed forward section).
FEC/non-FEC switching requires the use of hard core output transitions into the gt tx clk clock domain because it is required to be in the same clock domain.
The decoding core in the FEC hard core requires a clock not less than 380M and is uncorrelated with the GTY reference clock, which can be obtained using clock multiplication in fig. 5.
RX_FAST_CLK@368M (clock domain name, "@368M" means the frequency of the clock domain is 368M) and RSFEC _CLK@294M (clock domain name, "@294M" means the frequency of the clock domain is 294M), which require that the clock phases be kept related, can be output by the same phase-locked loop (Phase Locked Loop, PLL), and these two clocks cannot add the pseudo-path (FALSEPATH) constraint (the timing does not meet the requirement after the addition, which belongs to the content related to the FPGA constraint).
In fig. 5, differential input clocks (names GTREFCLKP and GTREFCLKN respectively) are input to a clock frequency doubling module (names MMCM (ddr) and MMCM (sys) respectively) through a high-speed serial interface input buffer (ibuf_gte4, differential clock input primitive module names), the MMCM is an IP core name, and the clock after the frequency doubling is input to an IP hard core (decoding) through the input buffer. The clocks (fec_fast_ CLK@368.64M) after the multiplication process and the protocol side clocks (tx_clk_out_ch0, tx_clk_outch1, tx_clk_outch2, and tx_clk_outch4) are input to an asynchronous data conversion device (named FIFO). The protocol side receiving module (named IR (RX)) decodes the data according to the protocol, and the protocol side transmitting module (named IR (TX)) packs according to the protocol. Triangles in the figure represent input buffers.
In fig. 5, CLK represents a clock domain, e.g., rx_clk_out_ CH0@368.64M represents the name rx_clk_outjch0, frequency 368.64M.
The base station interface module in the above embodiment is further described below with a specific example:
The RS-FEC function is verified by xlinx IP, the coding rate is 0.97, and the ip core supports maximum per-channel 28.05Gbps line speed processing. There are two implementations of the IP core, where a single optical port is verified by a soft core to be resource optimal, and two or more optical ports are realized by a hard core to be resource optimal.
1) The functions of the receiving and transmitting sides of the RS-FEC function are realized by soft cores, and each 32GFC RS-FEC (IP core name) soft core can realize single-channel transmission coding and scrambling processing and single-channel receiving codeword synchronization, descrambling and decoding processing.
2) The receiving side of the RS-FEC function is implemented by a hard core, but the transmitting side still needs to be implemented with soft cores, and each hard core of 100G FEC RX (IP core name) can implement a 4-channel IR receiving process. The 100G FEC RX IP hard core resource only uses the decoder as the hard core, and other synchronous/descrambling/de-rate matching/decoding block combination is realized by non-hard core, and still needs logic resources.
The current maximum RS-FEC function of 6 paths of optical ports of the BBU is increased by the following resources, and the RS-FEC hard core scheme is half less than the Look-Up Table (LUT) resources of the soft core scheme, namely 2 100G FEC RX hard cores and 6 32GFC RS-FEC TX soft cores are realized, and the method is specifically shown in a Table 1.
Table 1 scheme comparison table
Fig. 6 is a comparison chart of bit error rates in two modes, i.e., FEC and non-FEC, provided in the embodiment of the present application, as shown in fig. 6, where it can be seen from the chart that adding FEC in the engineering, and after recoding the base station interface, the system bit error rate can be obviously reduced.
Table 2 shows the signal-to-noise ratios (Signal to Noise Ratio, SNR) of various test points of the base station, and it can be seen in combination with table 2 and fig. 6 that the error rates are not very different for the two modes of the difference point and the middle point, but FEC can greatly reduce the base station error rate for the good point and the very good point.
TABLE 2 SNR for each test point of base station
| Base station test point | SNR |
| Excellent point | >22dB |
| Good point | 15~20dB |
| Midpoint (midpoint) | 5dB~10dB |
| Difference point | -5dB~0dB |
The embodiment of the application improves the stability of the data interaction between the AAU and the BBU through RS coding, is compatible with a non-FEC mode, enables the base station to have greater flexibility through switching selection of the register according to actual conditions, and demonstrates a scheme for saving on-chip resources more and cost on the premise of meeting functions.
Optionally, the embodiment of the present application further provides a base station, which includes the base station interface module described in the foregoing embodiment.
The base station provided by the embodiment of the application improves the stability of data interaction between the AAU and the BBU through the base station interface module, is compatible with a non-FEC mode, and can switch and select through the register according to actual conditions so that the base station has greater flexibility.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
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| US20080195918A1 (en) * | 2007-02-13 | 2008-08-14 | Lewis Adams | Preferential transmission of non-coded data over forward error correction code data for efficient power management of a remote device |
| CN101557277B (en) * | 2008-04-10 | 2013-08-28 | 华为技术有限公司 | Method and equipment for data transmission between base station and network node based on loading network |
| US10411832B2 (en) * | 2016-10-28 | 2019-09-10 | Globalfoundries Inc. | Ethernet physical layer device having integrated physical coding and forward error correction sub-layers |
| CN110460368B (en) * | 2019-07-23 | 2022-06-14 | 西安航天恒星科技实业(集团)有限公司 | Low-orbit communication satellite signal transmitting method for swan geese |
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| CN102480333A (en) * | 2010-11-22 | 2012-05-30 | 华为技术有限公司 | Line coding method, and processing method and device for synchronizing coded data blocks |
| CN111049865A (en) * | 2018-10-12 | 2020-04-21 | 中兴通讯股份有限公司 | Link establishment method, device and system |
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