CN115440818A - Semiconductor structures and methods of forming them - Google Patents

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, on which an initial fin protruding from the substrate and an isolation layer located on the substrate and covering part of the sidewall of the initial fin are formed, The substrate includes a first device region for forming a first device, and along the extending direction of the initial fin, the initial fin includes a channel region; in the first device region, part of the height of the channel region exposed to the isolation layer is removed the initial fin portion, retain the remaining initial fin portion as the first fin portion; form the first gate oxide layer, and the first gate oxide layer covers the top and sidewall of the first fin portion of the channel region; after forming the first gate oxide layer , forming a gate structure across the first fin of the channel region on the isolation layer, the gate structure includes a high-k dielectric layer covering the first gate oxide layer, and a gate electrode layer located on the high-k dielectric layer. The invention reduces the aspect ratio of the gap between the adjacent first fins in the channel region, and improves the fillability of the gate structure between the adjacent first fins.

Description

Semiconductor structures and methods of forming them

technical field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. Transistors are currently being widely used as one of the basic semiconductor devices. Therefore, with the increase in the density and integration of semiconductor devices, the gate size of planar transistors is getting shorter and shorter. The control ability of traditional planar transistors on the channel current becomes weaker, and the short channel effect occurs, causing the leakage current to increase. affect the electrical performance of semiconductor devices.

In order to better adapt to the reduction of feature size, the semiconductor process has gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as Fin Field Effect Transistors (FinFETs). However, it is difficult to further improve the performance of the FinFET under the condition that the feature size is further reduced.

Contents of the invention

The problem to be solved by the embodiments of the present invention is to provide a semiconductor structure and a forming method thereof, so as to improve the working performance of the semiconductor structure.

In order to solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a first device region for forming a first device; a fin protruding from the substrate, and the fin includes a The first fin of the first device region, along the extending direction of the fin, the fin includes a channel region; the isolation layer is located on the substrate and covers part of the side wall of the fin , the top of the isolation layer is lower than the top of the fin of the channel region, and the part of the first fin higher than the isolation layer is used as the first effective fin; the first gate oxide layer covers the The top and sidewalls of the first effective fin portion of the channel region; a gate structure, located on the substrate and across the first fin portion, the gate structure includes covering the first gate oxide layer The high-k dielectric layer, and the gate electrode layer located on the high-k dielectric layer; the source-drain doped layer, located in the fins on both sides of the gate structure, in the first device region, the The top of the source-drain doped layer is higher than the top of the first fin of the channel region.

Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, on which an initial fin protruding from the substrate is formed, and on the substrate and an isolation layer covering part of the sidewall of the initial fin, the substrate includes a first device region for forming a first device, and along the extending direction of the initial fin, the initial fin includes a channel region ; in the first device region, removing the initial fin part of the channel region exposed to the part of the height of the isolation layer, and retaining the remaining initial fin part as the first fin part; forming a first gate oxide layer, the The first gate oxide layer covers the top and sidewalls of the first fin portion of the channel region; after forming the first gate oxide layer, a first fin across the channel region is formed on the isolation layer. The gate structure of the fin portion, the gate structure includes a high-k dielectric layer covering the first gate oxide layer, and a gate electrode layer located on the high-k dielectric layer.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following advantages:

In the semiconductor structure provided by the embodiment of the present invention, under the trend of increasingly compact semiconductor structures, in the first device region, the top of the source-drain doped layer is higher than that of the first fin of the channel region The top, that is, the height of the first fins of the channel region is reduced, which reduces the aspect ratio of the gap between adjacent first fins in the channel region, which is beneficial to the formation of the gate structure, Improve the fillability of the gate structure between adjacent first fins in the channel region, and at the same time reduce the filling depth between adjacent first fins in the channel region when forming the gate structure The probability of void defect (void defect) is too large, and the top of the first fin in the channel region is lower, which is conducive to the formation of a thicker first gate oxide layer, thereby increasing the first device. In summary, all of the above are beneficial to improving the working performance of the semiconductor structure.

In the method for forming a semiconductor structure provided by an embodiment of the present invention, under the trend of increasingly compact semiconductor structures, in the first device region, part of the height of the initial fins in the channel region exposed to the isolation layer is removed part, retaining the remaining initial fins as the first fins, which reduces the aspect ratio of the gap between adjacent first fins in the channel region, which is beneficial to the formation of the gate structure and improves the gate structure. The fillability between adjacent first fins in the channel region, and at the same time, when forming the gate structure, voids are generated due to excessive filling depth between adjacent first fins in the channel region The probability of defect (void defect), and the top of the first fin in the channel region is relatively low, which is conducive to the formation of a thicker first gate oxide layer according to device performance requirements, thereby increasing the first In summary, the high-voltage resistance performance of the device is beneficial to improving the working performance of the semiconductor structure.

Description of drawings

1 to 5 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure;

6 to 9 are structural schematic diagrams of an embodiment of the semiconductor structure of the present invention;

10 to 22 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

detailed description

The performance of current semiconductor structures still needs to be improved. Combining with a method of forming a semiconductor structure, the reason why the working performance of the semiconductor structure still needs to be improved is analyzed.

1 to 5 are structural schematic diagrams corresponding to each step in a method for forming a semiconductor structure.

Referring to FIG. 1 and FIG. 2 in conjunction, FIG. 1 is a top view, and FIG. 2 is a sectional view based on the AA direction of FIG. A first device region 10I for forming a first device and a second device region 10C for forming a second device, the operating voltage of the first device is greater than the operating voltage of the second device, and a layer is formed on the substrate 10 An interlayer dielectric layer 13 (as shown in FIG. 1 ), and a gate opening 15 (as shown in FIG. 1 ) is formed in the interlayer dielectric layer 13. The gate opening 15 crosses the fin portion 20 and extends along the fin portion 20 direction, the area of the fin 20 exposed by the gate opening 15 is used as the channel region 20c, and a dummy gate oxide layer 30 is also formed on the fin 20, and the dummy gate oxide layer 30 covers the top and sides of the fin 20 of the channel region 20c. wall.

Referring to FIG. 3 , the dummy gate oxide layer 30 is removed to expose the surface of the fin portion 20 of the channel region 20c.

Referring to FIG. 4, after removing the dummy gate oxide layer 30, a gate oxide layer (not shown) is formed on the fin portion 20, the gate oxide layer covers the top and sidewalls of the fin portion 20 of the channel region 20c, and the gate oxide layer includes The first gate oxide layer 31 located in the first device region 10I, and the second gate oxide layer 32 located in the second device region 10C.

Since the operating voltage of the first device is greater than that of the second device, generally, the thickness of the first gate oxide layer 31 in the first device region 10I is greater than the thickness of the second gate oxide layer 32 in the second device region 10C.

Referring to FIG. 5, after forming the gate oxide layer, a gate structure 50 is formed in the gate opening 15 across the fin 20 of the channel region 20c, and the gate structure 50 includes A high-k dielectric layer 51 of an oxide layer, and a gate electrode layer 52 located on the high-k dielectric layer 51 .

With the improvement of the density and integration of semiconductor devices, the distance between adjacent fins 20 is continuously reduced, that is, the aspect ratio between adjacent fins 20 is continuously increased, and the gate structure 50 is The filling property between adjacent fins 20 is getting worse, especially for the first device region 10I, the first gate oxide layer 31 is usually thicker, and after the gate oxide layer is formed, the first gate oxide layer 31 is further reduced. The distance between adjacent fins 20 in a device region 10I, that is, the aspect ratio between adjacent fins 20 in the first device region 10I is further increased, thereby further increasing the gate structure 50 The difficulty of filling between adjacent fins 20 in the first device region 10I also increases the probability of void defects in the gate structure 50 due to poor filling performance, which affects the operation of the semiconductor structure performance.

In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, on which an initial fin protruding from the substrate is formed; an isolation layer on the bottom and covering a part of the sidewall of the initial fin, the substrate includes a first device region for forming a first device, and along the extending direction of the initial fin, the initial fin includes channel region; in the first device region, removing the initial fin part of the channel region exposed to the height of the isolation layer, and retaining the remaining initial fin part as the first fin part; forming a first gate oxide layer, the first gate oxide layer covers the top and sidewalls of the first fin of the channel region; after forming the first gate oxide layer, a A gate structure of the first fin portion, the gate structure includes a high-k dielectric layer covering the first gate oxide layer, and a gate electrode layer located on the high-k dielectric layer.

In the method for forming a semiconductor structure provided by an embodiment of the present invention, under the trend of increasingly compact semiconductor structures, in the first device region, part of the height of the initial fins in the channel region exposed to the isolation layer is removed part, retaining the remaining initial fins as the first fins, which reduces the aspect ratio of the gap between adjacent first fins in the channel region, which is beneficial to the formation of the gate structure and improves the gate structure. The fillability between adjacent first fins in the channel region, and at the same time, when forming the gate structure, voids are generated due to excessive filling depth between adjacent first fins in the channel region The probability of defect (void defect), and the top of the first fin in the channel region is relatively low, which is conducive to the formation of a thicker first gate oxide layer according to device performance requirements, thereby increasing the first In summary, the high-voltage resistance performance of the device is beneficial to improving the working performance of the semiconductor structure.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 6 to FIG. 9 , they are structural schematic diagrams of an embodiment of the semiconductor structure of the present invention. 6 is a top view, FIG. 7 is a cross-sectional view of FIG. 6 based on the AA direction, FIG. 8 is a cross-sectional view of FIG. 6 based on the BB direction, and FIG. 9 is a cross-sectional view of FIG. 6 based on the CC direction.

The semiconductor structure includes: a substrate 101, including a first device region 101I for forming a first device; a fin (not marked), protruding from the substrate 101, and the fin includes a The first fin portion 211 of the device region 101I, along the extending direction of the fin portion, the fin portion includes a channel region 201c (as shown in FIG. 11 ); the isolation layer 121 is located on the substrate 101, and Covering part of the sidewall of the fin, the top of the isolation layer 121 is lower than the top of the fin of the channel region 201c, and the part of the first fin 211 higher than the isolation layer 121 is used as the second An effective fin portion 231; a first gate oxide layer 311 covering the top and sidewalls of the first effective fin portion 231 of the channel region 201c; a gate structure 501 located on the substrate 101 and across the The first fin portion 211, the gate structure 501 includes a high-k dielectric layer 511 covering the first gate oxide layer 311, and a gate electrode layer 521 located on the high-k dielectric layer 511; a source-drain doped layer 161, located in the fins on both sides of the gate structure 501, in the first device region 101I, the top of the source-drain doped layer 161 is higher than the first fin 211 of the channel region 201c the top of.

The substrate 101 provides a process operation basis for the formation process of the semiconductor structure. Wherein, the semiconductor structure includes a fin field effect transistor.

In this embodiment, the material of the substrate 101 is silicon, and in other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or gallium indium. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other types of substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

In this embodiment, the substrate 101 includes a first device region 101I for forming a first device and a second device region 101C for forming a second device, and the working voltage of the first device is higher than that of the second device.

In this embodiment, the first device is an input-output (IO) device, and the second device is a core (core) device. The core device is used to realize the main functions of the integrated circuit. The input and output devices are used to provide corresponding input signals for the core device or output corresponding signals of the core device. The working voltage of the input and output devices is higher than that of the core device. For example, the operating voltage of the core device is 0.4V to 1.2V, and the operating voltage of the input and output devices is 1.0V to 3.5V.

It should be noted that the first device region 101I and the second device region 101C may or may not be adjacent.

In this embodiment, taking the semiconductor structure as an example of a FinFET, the semiconductor structure includes a fin protruding from the substrate 101 , and the fin is used to provide a channel of the FinFET.

In this embodiment, the fins are integrated with the substrate 101 . In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.

In this embodiment, the fins include a first fin 211 located in the first device region 101I and a second fin 221 located in the second device region 101C, and the first fin 211 is used for The channel of the first device is provided, and the second fin 221 is used to provide the channel of the second device.

Referring to FIG. 6 , along the extending direction of the fin (shown as the X direction in FIG. 6 ), the fin includes a channel region 201c. The fin portion of the channel region 201c is used as a channel of a transistor.

In this embodiment, in the channel region 201c, the top of the first fin 211 is lower than the top of the second fin 221 .

The operating voltage of the first device is greater than the operating voltage of the second device, then the top of the first fin 211 in the channel region 201c is lower, which reduces the The aspect ratio of the gap between the fins 211 is conducive to the formation of a thicker first gate oxide layer 311 , thereby increasing the high-voltage resistance performance of the first device, which in turn is beneficial to improving the working performance of the semiconductor structure.

In this embodiment, the material of the first fin portion 211 includes silicon, germanium, silicon germanium or III-V group semiconductor material; the material of the second fin portion 221 includes silicon, germanium, silicon germanium or III-V group semiconductor material; Group V semiconductor materials.

Specifically, the material of the first fin 211 is determined according to the performance of the first device, and the material of the second fin 221 is determined according to the performance of the second device.

In this embodiment, the material of the fin is the same as that of the substrate 101 , the material of the first fin 211 is silicon, and the material of the second fin 221 is also silicon.

The isolation layer 121 serves as a shallow trench isolation (STI) for isolating adjacent transistors.

The material of the isolation layer 121 is insulating material. In this embodiment, the material of the isolation layer 121 is silicon oxide.

In this embodiment, the isolation layer 121 covers part of the sidewall of the fin, and the top of the isolation layer 121 is lower than the top of the fin of the channel region 201c, so that the channel region 201c Part-height fins can serve as channels for transistors.

Specifically, the part of the first fin 211 higher than the isolation layer 121 is used as the first effective fin 231, and the part of the second fin 221 higher than the isolation layer 121 is used as the second effective fin 241. , so that the transistor only uses the first effective fin portion 231 and the second effective fin portion 241 as a channel.

In the channel region 201c, the top of the first fin 211 is lower than the top of the second fin 221, and the top of the first effective fin 231 is lower than the second effective fin. 241 top.

In this embodiment, in the channel region 201c, the ratio of the height d1 of the first effective fin portion 231 to the height d2 of the second effective fin portion 241 should not be too large, nor should it be too small. If the ratio of the height d1 of the first effective fin portion 231 to the height d2 of the second effective fin portion 241 is too large, the height d1 of the first effective fin portion 231 is too large, making it difficult to reduce the height of the adjacent second fin portion in the first device region 101I. The width-to-depth ratio of the gap between the effective fins 231 makes it difficult to form a thicker first gate oxide layer 311, thereby making it difficult to increase the high-voltage resistance of the first device. At the same time, when forming the gate structure 501, due to the trench The filling depth between adjacent first effective fins 231 in the channel region 201c is too large to easily generate void defects, which affects the fillability of the gate structure 501 and thus affects the working performance of the semiconductor structure; if the first effective fins 231 If the ratio of the height d1 to the height d2 of the second effective fin 241 is too small, the height d1 of the first effective fin 231 is too small, making it difficult to have the first effective fin 231 of sufficient height as the channel of the first device. Thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, in the channel region 201c, the height d1 of the first effective fin portion 231 is 5% to 95% of the height d2 of the second effective fin portion 241 . For example, the height d1 of the first effective fin portion 231 is 30%, 50% or 70% of the height d2 of the second effective fin portion 241 .

The first gate oxide layer 311 is used to isolate the gate structure 501 from the first effective fin 231 , and the second gate oxide layer 321 is used to isolate the gate structure 501 from the second effective fin 241 .

In this embodiment, the operating voltage of the first device is greater than the operating voltage of the second device, so the thickness of the second gate oxide layer 321 is smaller than the thickness of the first gate oxide layer 311 . The larger thickness of the first gate oxide layer 311 improves the breakdown resistance performance between the gate structure 501 and the first effective fin 231 in the first device region 101I, so that the first A device is capable of operating at higher voltages.

The first gate oxide layer 311 and the second gate oxide layer 321 require better isolation performance, so in this embodiment, the material of the first gate oxide layer 311 includes one of SiO ₂ and La ₂ O ₃ or both; the material of the second gate oxide layer 321 includes one or both of SiO ₂ and La ₂ O ₃ .

The gate structure 501 is used to control the on and off of the channel of the transistor. In this embodiment, the gate structure 501 is a metal gate structure.

The high-k dielectric layer 511 is used to isolate the gate electrode layer 521 from the first effective fin portion 231 and the second effective fin portion 241 , and reduce the leakage probability of the semiconductor structure.

In this embodiment, the material of the high-k dielectric layer 511 includes a high-k dielectric material. Wherein, the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k dielectric layer 511 includes one or more of HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al ₂ O ₃ .

In this embodiment, the material of the gate electrode layer 521 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN and TiAlC. The gate electrode layer 521 includes a work function layer (not marked), and an electrode layer (not marked) on the work function layer. Wherein, the work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to extract the electricity of the metal gate structure.

In some other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

In this embodiment, the semiconductor structure further includes: sidewalls 141 covering the sidewalls of the gate structure 501 .

The sidewalls 141 are used to protect the sidewalls of the gate structure 501 . The sidewall 141 can be a single-layer structure or a laminated structure, and the material of the sidewall 141 includes silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide, boron nitride and one or more of boron carbonitride. In this embodiment, the sidewall 141 is a single-layer structure, and the material of the sidewall 141 is silicon nitride.

In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 131 located on the isolation layer 121 , the interlayer dielectric layer 131 covers the sidewalls of the sidewalls 141 and exposes the top of the gate structure 501 .

The interlayer dielectric layer 131 is used to isolate adjacent devices, and the interlayer dielectric layer 131 is also used to provide a process basis for forming the gate structure 501 .

The material of the interlayer dielectric layer 131 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbonitride.

During the formation of the semiconductor structure, after the first source-drain doped layer 161 is formed in the first fin portion 211 on both sides of the gate structure 501, an interlayer dielectric layer 131 is formed, and the interlayer dielectric layer 131 covers the source-drain doped layer 161, and exposes the first fin portion 211 of the channel region 201c; removes the part of the height of the first fin portion in the channel region 201c exposed by the interlayer dielectric layer 131. fins 211 . Therefore, the top of the source-drain doped layer 161 is higher than the top of the first fin portion 211 of the channel region 201c.

Under the trend of increasingly compact semiconductor structures, in the first device region 101I, the top of the source-drain doped layer 161 is higher than the top of the first fin 211 of the channel region 201c, that is, The height of the first fins 211 of the channel region 201c is reduced, which reduces the aspect ratio of the gap between adjacent first fins 211 in the channel region 201c, which facilitates the formation of the gate structure 501 and improves The fillability of the gate structure 501 between the adjacent first fins 211 in the channel region 201c is reduced, and at the same time, when the gate structure 501 is formed, due to the filling between the adjacent first fins 211 in the channel region 201c If the depth is too large, the probability of void defects will be generated. Moreover, the top of the first fin 211 in the channel region 201c is relatively low, which is conducive to the formation of a thicker first gate oxide layer 311, thereby increasing the first In summary, the high-voltage resistance performance of the device is beneficial to improving the working performance of the semiconductor structure.

The source-drain doped layer 161 is used as a source region or a drain region of the formed FinFET. Specifically, the doping type of the source-drain doped layer 161 is the same as the channel conductivity type of the corresponding transistor. For an NMOS transistor, the doped ions in the source-drain doped layer 161 are N-type ions, so The N-type ions include P ions, As ions or Sb ions; for PMOS transistors, the dopant ions in the source-drain doped layer 161 are P-type ions, and the P-type ions include B ions, Ga ions or In ions .

10 to 22 are structural schematic diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

Referring to FIGS. 10 to 12 in combination, FIG. 10 is a top view, FIG. 11 is a sectional view of FIG. 10 based on the AA direction, and FIG. 12 is a sectional view of FIG. 10 based on the BB direction. A substrate 100 is provided. The initial fin portion 200 of the bottom 100, and the isolation layer 120 located on the substrate 100 and covering part of the sidewall of the initial fin portion 200, the substrate 100 includes a first device region 100I for forming a first device, along the initial fin portion 200 , the initial fin includes a channel region 200c (as shown in FIG. 10 ).

The substrate 100 provides a process operation basis for the formation process of the semiconductor structure. Wherein, the semiconductor structure includes a fin field effect transistor.

In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or gallium indium. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other types of substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

In this embodiment, the substrate 100 includes a first device region 100I for forming a first device, and also includes a second device region 100C for forming a second device, the working voltage of the first device is higher than the The operating voltage of the second device.

In this embodiment, the first device is an input-output (IO) device, and the second device is a core (core) device. The core device is used to realize the main functions of the integrated circuit. The input and output devices are used to provide corresponding input signals for the core device or output corresponding signals of the core device. The working voltage of the input and output devices is higher than that of the core device. For example, the operating voltage of the core device is 0.4V to 1.2V, and the operating voltage of the input and output devices is 1.0V to 3.5V.

It should be noted that the first device region 100I and the second device region 100C may or may not be adjacent.

In this embodiment, taking the semiconductor structure as a fin field effect transistor as an example, an initial fin 200 protruding from the substrate 100 is formed on the substrate 100, and the initial fin 200 is used to provide a fin field effect transistor. The channel of a field effect transistor.

In this embodiment, the initial fin portion 200 is integrated with the substrate 100 . In other embodiments, the initial fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the initial fin.

Referring to FIG. 10 , along the extension direction of the initial fin portion 200 (shown as the X direction in FIG. 10 ), the initial fin portion 200 includes a channel region 200c. The initial fin 200 of the channel region 200c serves as the channel of the transistor.

In this embodiment, the material of the initial fin portion 200 includes silicon, germanium, silicon germanium or III-V group semiconductor materials. In this embodiment, the material of the initial fin portion 200 is the same as that of the substrate 100 , and the material of the initial fin portion 200 is silicon.

In this embodiment, the initial fin 200 on the substrate 100 of the second device region 100C is used as the second fin 220 , and the second fin 220 is used to provide a channel of the second device.

In this embodiment, the material of the second fin portion 220 is silicon.

The isolation layer 120 serves as a shallow trench isolation structure for isolating adjacent transistors.

The material of the isolation layer 120 is insulating material. In this embodiment, the material of the isolation layer 120 is silicon oxide.

In this embodiment, the isolation layer 120 covers part of the sidewall of the initial fin 200, and the top of the isolation layer 120 is lower than the top of the initial fin 200 in the channel region 200c, so that the The portion of the initial fin 200 higher than the isolation layer 120 is used to provide a channel.

In this embodiment, the height at which the initial fin exposes the isolation layer is a first height d2.

In this embodiment, in the step of providing the substrate 100 , a dummy gate oxide layer 300 is formed on the top and sidewall of the initial fin portion 200 exposed on the isolation layer 120 .

As an example, the material of the dummy gate oxide layer 300 is silicon oxide.

In this embodiment, an interlayer dielectric layer 130 is formed on the isolation layer 120, and a gate opening 150 is formed in the interlayer dielectric layer 130. The gate opening 150 crosses the initial fin portion 200 and exposes the initial fin portion of the channel region 200c. The source and drain doped layers 160 are formed in the initial fin portion 200 on both sides of the gate opening 150 on the top and sidewalls of the gate opening 150 .

The interlayer dielectric layer 130 is used to isolate adjacent devices, and the interlayer dielectric layer 130 is also used to provide a process basis for forming the gate opening 150 .

The material of the interlayer dielectric layer 130 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

The gate opening 150 is used to provide a space position for subsequent formation of a gate structure.

The source-drain doped layer 160 is used as a source region or a drain region of the formed FinFET. Specifically, the doping type of the source-drain doped layer 160 is the same as the channel conductivity type of the corresponding transistor. For an NMOS transistor, the doped ions in the source-drain doped layer 160 are N-type ions, so The N-type ions include P ions, As ions or Sb ions; for PMOS transistors, the dopant ions in the source-drain doped layer 160 are P-type ions, and the P-type ions include B ions, Ga ions or In ions .

In this embodiment, sidewalls 140 are further formed on the sidewalls of the gate opening 150 , and the interlayer dielectric layer 130 covers the sidewalls of the sidewalls 140 .

The sidewalls 140 are used to protect the sidewalls of the subsequently formed gate structure. The sidewall 140 can be a single-layer structure or a laminated structure, and the material of the sidewall 140 includes silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide, boron nitride and one or more of boron carbonitride. In this embodiment, the sidewall 140 is a single-layer structure, and the material of the sidewall 140 is silicon nitride.

In this embodiment, before forming the interlayer dielectric layer 130, it further includes: forming a dummy gate layer (not shown) on the isolation layer 120, the dummy gate layer straddles the initial fin portion 200, and The top and sidewalls of the initial fin 200 covering the channel region 200c.

The dummy gate layer is used to occupy a space position for subsequent formation of a gate structure.

In this embodiment, the dummy gate layer covers the dummy gate oxide layer 300 , and the sidewalls 140 cover the sidewalls of the dummy gate layer.

As an example, the material of the dummy gate layer is polysilicon.

In this embodiment, the source-drain doped layer 160 is formed in the initial fin portion 200 on both sides of the dummy gate layer. The interlayer dielectric layer 130, the interlayer dielectric layer 130 exposes the top of the dummy gate layer, prepares for subsequent removal of the dummy gate layer.

In this embodiment, the step of forming the gate opening 150 includes: removing the dummy gate layer.

Referring to FIG. 13 and FIG. 14 together, FIG. 13 and FIG. 14 are cross-sectional views based on FIG. 11 , in the first device region 100I, the initial portion of the channel region 200c exposed to the height of the isolation layer 120 is removed. The fin portion 200 retains the remaining initial fin portion 200 as the first fin portion 210 .

Under the trend of more and more compact semiconductor structures, in the first device region 100I, the initial fins 200 in the channel region 200c exposed to the part of the height of the isolation layer 120 are removed, and the remaining initial fins 200 are retained as The first fins 210 reduce the aspect ratio of the gap between adjacent first fins 210 in the channel region 200c, which is beneficial to the formation of the gate structure and improves the gate structure in the channel region 200c. The fillability between adjacent first fins 210 in the channel region 200c is reduced, and at the same time, when forming the gate structure, void defects are generated due to the excessive filling depth between adjacent first fins 210 in the channel region 200c Moreover, the top of the first fin 210 in the channel region 200c is relatively low, which is conducive to forming a thicker first gate oxide layer according to device performance requirements, thereby increasing the resistance of the first device. In summary, the high-voltage performance is beneficial to improving the working performance of the semiconductor structure.

The first fin 210 is used to provide a channel of the first device.

In this embodiment, the material of the first fin portion 210 is silicon.

In this embodiment, in the first device region 100I, in the step of removing the initial fin portion 200 exposed at a part height of the isolation layer 120 in the channel region 200c, the dry etching process is used to remove the The initial fin portion 200 in the channel region 200c is exposed to a part of the height of the isolation layer 120 .

The dry etching process has the characteristics of anisotropic etching and more directional etching, which is conducive to improving the formation quality and dimensional accuracy of the first fin portion 210. Moreover, the dry etching process can Better control of process parameters, high process controllability, and easy to obtain more accurate graphic transfer.

In this embodiment, the remaining initial fin portion 200 of the channel region 200c exposing the isolation layer 120 has a height of the second height d1, and the proportion of the second height d1 to the first height d2 should not be too large, or Should not be too small. If the ratio of the second height d1 to the first height d2 is too large, the height d1 of the first fins 210 is too large, so that it is difficult to reduce the gap between adjacent first fins 210 in the first device region 100I. The width-to-depth ratio makes it difficult to form a thicker first gate oxide layer later, so that it is difficult to increase the high-voltage resistance performance of the first device. At the same time, when the gate structure is subsequently formed, due to the adjacent first fins in the channel region If the filling depth between the parts 210 is too large, it is easy to generate void defects, which affects the filling performance of the gate structure, thereby affecting the working performance of the semiconductor structure; if the proportion of the second height d1 to the first height d2 is too small, Then the height d1 of the first fin portion 210 is too small, making it difficult to have the first fin portion 210 of sufficient height as the channel of the first device, thus affecting the performance of the semiconductor structure. Therefore, in the first device region 100I, in the step of removing the initial fin portion 200 in the channel region 200c exposed to a part of the height of the isolation layer 120, the initial fin portion remains in the channel region 200c The height of the portion 200 exposing the isolation layer 120 is a second height d1, and the ratio of the second height d1 to the first height d2 is 5% to 95%. For example, the second height d1 is 30%, 50% or 70% of the first height d2.

Specifically, referring to FIG. 13 , in the first device region 100I, the step of removing the initial fin portion 200 in the channel region 200c exposed to a part of the height of the isolation layer 120 includes: forming a first mask covering the second fin portion 220 layer 410, in the first device region 100I, the first mask layer 410 exposes the initial fin portion 200 of the channel region 200c.

In the first device region 100I, the first mask layer 410 exposes the initial fin 200 of the channel region 200c to prepare for removing the initial fin 200 with a partial height. At the same time, the first mask The film layer 410 is also used to protect the second fin 220 located in the second device region 100C.

In this embodiment, the first mask layer 410 is a laminated structure, and the first mask layer 410 includes a planarization layer (not marked) and a photoresist layer (not marked) on the planarization layer. ).

In this embodiment, the material of the planarization layer is spin on carbon (SOC) material. The spin-on carbon is formed by a spin-coating process, and the process cost is relatively low; moreover, the use of the spin-on carbon is beneficial to improve the flatness of the top surface of the planarization layer.

In this embodiment, in the step of forming the first mask layer 410 , the first mask layer 410 covers the dummy gate oxide layer 300 on the second fin portion 220 .

Referring to FIG. 14 , after forming the first mask layer 410, before removing the initial fin portion 200 of the channel region 200c exposed by the first mask layer 410, further includes: removing the dummy gate exposed by the first mask layer 410 oxide layer 300 .

The dummy gate oxide layer 300 exposed by the first mask layer 410 is removed, exposing the surface of the first fin portion 210 , and preparing for the subsequent formation of a first gate oxide layer.

Continuing to refer to FIG. 14 , in the first device region 100I, part of the height of the initial fin 200 of the channel region 200c exposed by the first mask layer 410 is removed, leaving the remaining initial fin 200 as the first fin 210 .

Removing the partial height of the initial fin 200 of the channel region 200c exposed by the first mask layer 410 reduces the damage to the second fin 220 in the process of removing the partial height of the initial fin 200 in the first device region 100I .

Specifically, along the gate opening 150 of the first device region 100I, part of the height of the initial fin 200 of the channel region 200c is removed.

Referring to FIG. 15 , which is a cross-sectional view based on FIG. 14 , after the first fin portion 210 is formed, the first mask layer 410 is removed to prepare for the subsequent formation of a second gate oxide layer.

Specifically, the dummy gate oxide layer 300 in the gate opening 150 of the first device region 100I is removed.

Continuing to refer to FIG. 15 , a first gate oxide layer 310 is formed, and the first gate oxide layer 310 covers the top and sidewalls of the first fin portion 210 of the channel region 200c.

The first gate oxide layer 310 is used to isolate the subsequently formed gate structure from the first fin 210 .

In this embodiment, an oxidation process is used to form the first gate oxide layer 310 , so that the first gate oxide layer 310 is only formed on the top and sidewalls of the first fin portion 210 exposed to the isolation layer 120 .

The first gate oxide layer 310 needs better isolation performance, so in this embodiment, the material of the first gate oxide layer 310 includes one or both of SiO ₂ and La ₂ O ₃ .

It should be noted that a dummy gate oxide layer 300 is formed on the top and side walls of the second fin portion 220 , and during the process of forming the first gate oxide layer 310 , the dummy gate oxide layer 300 protects the top and side walls of the second fin portion 220 . walls, so that the first gate oxide layer 310 is selectively formed on the top and sidewalls of the first fin portion 210 of the channel region 200c.

Referring to FIG. 16 and FIG. 17 in conjunction, FIG. 16 and FIG. 17 are cross-sectional views based on FIG. 5 . After forming the first gate oxide layer 310 and before subsequently forming the second gate oxide layer, it also includes: forming The second mask layer 420 of the oxide layer 310, in the second device region 200C, the second mask layer 420 exposes the dummy gate oxide layer 300 located in the channel region.

The second mask layer 420 exposes the dummy gate oxide layer 300 located in the channel region to prepare for subsequent removal of the dummy gate oxide layer 300 in the second device region 100C. At the same time, the second mask layer 420 also protects the first gate oxide layer 310 located in the first device region 100I.

In this embodiment, the second mask layer 420 is a laminated structure, and the second mask layer 420 includes a planarization layer (not marked) and a photoresist layer (not marked) on the planarization layer. ).

In this embodiment, the material of the planarization layer is spin on carbon (SOC) material. The spin-on carbon is formed by a spin-coating process, and the process cost is relatively low; moreover, the use of the spin-on carbon is beneficial to improve the flatness of the top surface of the planarization layer.

Referring to FIG. 17 , the dummy gate oxide layer 300 exposed by the second mask layer 420 is removed.

The dummy gate oxide layer 300 exposed by the second mask layer 420 is removed, exposing the surface of the second fin portion 220 , and preparing for the subsequent formation of a second gate oxide layer. Referring to FIG. 18 , FIG. 18 is a cross-sectional view based on FIG. 17 . After removing the dummy gate oxide layer 300 exposed by the second mask layer 420 , the second mask layer 420 is removed to prepare for the subsequent formation of a gate structure.

Continuing to refer to FIG. 18 , before forming the gate structure, it further includes: forming a second gate oxide layer 320, the second gate oxide layer 320 covering the top and sidewalls of the second fin portion 220 of the channel region 200c, The thickness of the second gate oxide layer 320 is smaller than the thickness of the first gate oxide layer 310 .

The second gate oxide layer 320 is used to isolate the subsequently formed gate structure from the second fin 220 .

In this embodiment, the second gate oxide layer 320 is formed by an oxidation process, so that the second gate oxide layer 320 is only formed on the top and sidewalls of the second fins 220 exposed to the isolation layer 120 .

In this embodiment, the operating voltage of the first device is greater than the operating voltage of the second device, and the thickness of the second gate oxide layer 320 is smaller than the thickness of the first gate oxide layer 310 . The larger thickness of the first gate oxide layer 310 improves the breakdown resistance between the gate structure and the first fin 210 in the first device region 100I, so that the first device can be used in work at higher voltages.

The second gate oxide layer 320 needs better isolation performance, so in this embodiment, the material of the second gate oxide layer 320 includes one or both of SiO ₂ and La ₂ O ₃ .

It should be noted that a first gate oxide layer 310 is formed on the top and sidewalls of the first fin portion 210, and during the process of forming the second gate oxide layer 320, the first gate oxide layer 310 protects all The top and sidewalls of the first fin portion 210 are described so that the second gate oxide layer 320 is selectively formed on the top and sidewalls of the second fin portion 220 of the channel region 200c.

Referring to FIGS. 19 to 22 in conjunction, FIG. 19 is a sectional view based on FIG. 18 , FIG. 20 is a top view of the gate structure and fins, FIG. 21 is a sectional view of FIG. 20 based on the BB direction, and FIG. 22 is a sectional view of FIG. 20 based on the CC direction. After forming the first gate oxide layer 310, a gate structure 500 is formed on the isolation layer 120 across the first fin portion 210 of the channel region 200c, and the gate structure 500 includes a gate structure covering the first gate oxide layer 310. The high-k dielectric layer 510, and the gate electrode layer 520 on the high-k dielectric layer 510.

In this embodiment, in the step of forming the gate structure 500 , the high-k dielectric layer 510 also covers the second gate oxide layer 320 .

In this embodiment, the gate structure 500 is formed in the gate opening 150 .

The gate structure 500 is used to control the on and off of the channel of the transistor. In this embodiment, the gate structure 500 is a metal gate structure.

The high-k dielectric layer 510 is used to isolate the gate electrode layer 520 from the first fin portion 210 and the second fin portion 220 and reduce the leakage probability of the semiconductor structure.

In this embodiment, the material of the high-k dielectric layer 510 includes a high-k dielectric material. Wherein, the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k dielectric layer 510 includes one or more of HfO ₂ , ZrO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al ₂ O ₃ .

In this embodiment, the material of the gate electrode layer 520 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN and TiAlC. The gate electrode layer 520 includes a work function layer (not shown), and an electrode layer (not shown) on the work function layer. Wherein, the work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to extract the electricity of the metal gate structure.

In some other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (17)

1. A semiconductor structure, comprising:

a substrate including a first device region for forming a first device;

the fin portion protrudes from the substrate, the fin portion comprises a first fin portion located in the first device region, and the fin portion comprises a channel region along the extending direction of the fin portion;

the isolation layer is positioned on the substrate and covers partial side walls of the fin parts, the top of the isolation layer is lower than the top of the fin part of the channel region, and the part, higher than the isolation layer, of the first fin part serves as a first effective fin part;

the first gate oxide layer covers the top and the side wall of the first effective fin part of the channel region;

the grid structure is positioned on the substrate and stretches across the first fin part, and comprises a high-k dielectric layer covering the first grid oxide layer and a grid electrode layer positioned on the high-k dielectric layer;

and the source-drain doping layer is positioned in the fin parts on two sides of the grid structure, and in the first device region, the top of the source-drain doping layer is higher than that of the first fin part of the channel region.

2. The semiconductor structure of claim 1, wherein the substrate further comprises a second device region for forming a second device, the operating voltage of the first device being greater than the operating voltage of the second device;

the fin portion further comprises a second fin portion located in the second device region, and in the channel region, the top of the first fin portion is lower than the top of the second fin portion;

the part, higher than the isolation layer, of the second fin part is used as a second effective fin part;

the semiconductor structure further includes: the second gate oxide layer covers the top and the side wall of the second effective fin part of the channel region, and the thickness of the second gate oxide layer is smaller than that of the first gate oxide layer;

the grid electrode structure further stretches across the second fin portion, and the high-k dielectric layer further covers the second gate oxide layer.

3. The semiconductor structure of claim 2, wherein a height of the first effective fin is 5% to 95% of a height of the second effective fin in the channel region.

4. The semiconductor structure of claim 1, wherein a material of the first fin comprises silicon, germanium, silicon germanium, or a group iii-v semiconductor material.

5. The semiconductor structure of claim 2, wherein a material of the second fin comprises silicon, germanium, silicon germanium, or a group iii-v semiconductor material.

6. The semiconductor structure of claim 1, wherein the material of the first gate oxide layer comprises SiO ₂ And La ₂ O ₃ One or two of them; the material of the high-k dielectric layer comprises HfO ₂ 、ZrO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO and Al ₂ O ₃ One or more of; the material of the gate electrode layer comprises one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN and TiAl C.

7. The semiconductor structure of claim 2, wherein the material of said second gate oxide layer comprises SiO ₂ And La ₂ O ₃ One or two of them.

8. The semiconductor structure of claim 2, wherein the first device is an input-output device and the second device is a core device.

9. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein an initial fin portion protruding from the substrate and an isolation layer which is located on the substrate and covers a part of side walls of the initial fin portion are formed on the substrate, the substrate comprises a first device area used for forming a first device, and the initial fin portion comprises a channel area along the extending direction of the initial fin portion;

in the first device region, removing the initial fin part exposed out of the channel region at the partial height of the isolation layer, and reserving the residual initial fin part as a first fin part;

forming a first gate oxide layer, wherein the first gate oxide layer covers the top and the side wall of the first fin part of the channel region;

after the first gate oxide layer is formed, a grid electrode structure crossing the first fin portion of the channel region is formed on the isolation layer, and the grid electrode structure comprises a high-k dielectric layer covering the first gate oxide layer and a grid electrode layer located on the high-k dielectric layer.

10. The method of claim 9, wherein in the step of providing the substrate, the substrate further comprises a second device region for forming a second device, the initial fin on the substrate of the second device region is used as a second fin, and an operating voltage of the first device is greater than an operating voltage of the second device;

before forming the gate structure, the method further comprises: forming a second gate oxide layer, wherein the second gate oxide layer covers the top and the side wall of the second fin part of the channel region, and the thickness of the second gate oxide layer is smaller than that of the first gate oxide layer;

in the step of forming the gate structure, the high-k dielectric layer also covers the second gate oxide layer.

11. The method of forming a semiconductor structure of claim 10, wherein in the first device region, removing the initial fin portion of the channel region exposed to a partial height of the isolation layer comprises: forming a first mask layer covering the second fin portion, wherein the first mask layer exposes the initial fin portion of the channel region in the first device region;

in the first device area, removing the initial fin part of the channel area with the partial height exposed by the first mask layer, and reserving the residual initial fin part as a first fin part;

and removing the first mask layer after the first fin part is formed.

12. The method for forming a semiconductor structure of claim 11, wherein in the step of providing a substrate, a dummy gate oxide layer is further formed on the top and sidewalls of the initial fin portion exposed out of the isolation layer;

in the step of forming the first mask layer, the first mask layer covers the pseudo gate oxide layer on the second fin portion;

after the first mask layer is formed, before removing the initial fin portion of the channel region with the partial height exposed by the first mask layer, the method further includes: removing the pseudo gate oxide layer exposed by the first mask layer;

after the first gate oxide layer is formed and before the second gate oxide layer is formed, the method further comprises the following steps: forming a second mask layer covering the first gate oxide layer, wherein in the second device area, the second mask layer exposes the pseudo gate oxide layer positioned in the channel area;

removing the pseudo gate oxide layer exposed by the second mask layer;

and removing the second mask layer.

13. The method for forming the semiconductor structure according to claim 9, wherein in the step of providing the substrate, an interlayer dielectric layer is formed on the isolation layer, a gate opening is formed in the interlayer dielectric layer, the gate opening crosses over the initial fin portion and exposes the top and the sidewalls of the initial fin portion of the channel region, and an active drain doping layer is formed in the initial fin portion on both sides of the gate opening;

forming the gate structure in the gate opening.

14. The method of forming a semiconductor structure of claim 13, further comprising, prior to forming said interlevel dielectric layer: forming a pseudo gate layer on the isolation layer, wherein the pseudo gate layer crosses the initial fin part and covers the top and the side wall of the initial fin part of the channel region;

forming the source-drain doping layers in the initial fin parts on two sides of the pseudo gate layer;

after the source-drain doping layer is formed, forming the interlayer dielectric layer on the substrate on the side part of the pseudo gate layer, wherein the interlayer dielectric layer is exposed out of the top of the pseudo gate layer;

the step of forming the gate opening includes: and removing the pseudo gate layer.

15. The method for forming the semiconductor structure according to claim 9, wherein in the step of removing the initial fin portion of the channel region exposed to the partial height of the isolation layer in the first device region, the initial fin portion of the channel region exposed to the partial height of the isolation layer is removed by a dry etching process.

16. The method of forming a semiconductor structure of claim 10, wherein in the step of providing a substrate, the first device is an input-output device and the second device is a core device.

17. The method of forming a semiconductor structure of claim 11, wherein in the step of providing a substrate, the initial fin is exposed to the isolation layer at a first height;

in the first device region, in the step of removing the initial fin portion of the channel region exposed out of the isolation layer at a partial height, the height of the channel region with the remaining initial fin portion exposed out of the isolation layer is a second height, and the second height accounts for 5% to 95% of the first height.

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