CN115440605A - Method for constructing storage chip packaging structure and packaging structure - Google Patents

Abstract

The invention relates to the technical field of semiconductor packaging, and provides a method for constructing a memory chip packaging structure and the packaging structure. The method comprises the following steps: providing a first chip; forming a recess on a first side of the first chip; arranging a control chip at the groove; providing a second chip, wherein a storage area is arranged on the second chip; and stacking the first side of the second chip on the second side of the first chip. According to the invention, the TSV structure is constructed on the chip body, the functional chip and the adapter plate in the traditional packaging structure are combined into a whole, the performance of the chip is improved, meanwhile, the packaging volume is reduced, and the integration level of three-dimensional packaging can be effectively improved by digging a cavity in the back space of the functional chip and embedding the control chip.

Description

A method for constructing a memory chip packaging structure and the packaging structure

technical field

The present invention generally relates to the field of semiconductor packaging technology. Specifically, the present invention relates to a method and a packaging structure for constructing a memory chip packaging structure.

Background technique

Traditionally, when packaging the memory chip and the control chip, the memory chip and the control chip are usually arranged on the same side or different sides of the packaging carrier, and the memory chip and the control chip are plastic-sealed with a plastic packaging material.

However, in the traditional packaging structure, since the memory chip and the control chip are arranged on the surface of the packaging carrier, the volume of the packaging structure is too large; and due to the use of a large amount of plastic packaging material, the heat dissipation of the packaging carrier is affected, and it is easy to cause the packaging The warping of the carrier affects the reliability of the subsequent packaging; in addition, the traditional packaging structure usually uses a printed circuit board (PCB, Printed Circuit Board) as the packaging carrier, but due to the large process node and size of the printed circuit board , so it is difficult to meet the current higher integration density packaging requirements.

Contents of the invention

In order to at least partially solve the above-mentioned problems in the prior art, the present invention proposes a method for constructing a memory chip packaging structure, including the following steps:

providing the first chip;

configuring grooves on the first face of the first chip;

Arranging a control chip at the groove;

providing a second chip, wherein the second chip has a memory area disposed thereon; and

The first side of the second chip is stacked on the second side of the first chip.

According to an embodiment of the present invention, the method for constructing a memory chip packaging structure further includes:

constructing a first through-silicon via on the first chip;

forming a second through-silicon via on the second chip; and

The second TSV is connected to the first TSV when the second chip is stacked on the first chip.

According to an embodiment of the present invention, the second chip includes one or more storage areas.

According to an embodiment of the present invention, the number of the storage areas is greater than or equal to four.

In one embodiment of the invention it is provided that a plurality of said second chips are provided, wherein a plurality of said second chips are stacked on top of each other.

The present invention also proposes a storage chip packaging structure, which is constructed according to the method for constructing a storage chip packaging structure, and the structure includes:

A first chip, wherein a groove is provided on the first surface of the first chip, and a control chip is arranged at the groove;

The second chip includes a memory chip, wherein the first side of the second chip is stacked on the second side of the first chip.

According to an embodiment of the present invention, the first chip further includes a first through-silicon via, and the second chip further includes a second through-silicon via, wherein the first through-silicon via and the second through-silicon via hole connection.

According to an embodiment of the present invention, the second chip includes one or more storage areas.

According to an embodiment of the present invention, the number of storage areas is greater than or equal to 4.

According to an embodiment of the present invention, the memory chip packaging structure includes:

A plurality of second chips, wherein the plurality of second chips are stacked on each other.

The present invention has at least the following beneficial effects: the present invention provides a method for constructing a memory chip package structure and a package structure. Among them, the TSV structure is constructed on the chip body, and the functional chip and the adapter plate in the traditional packaging structure are combined into one, which improves the performance of the chip and reduces the packaging volume. Incorporating a control chip can effectively improve the integration level of three-dimensional packaging.

Description of drawings

To further clarify the present and other advantages and features of various embodiments of the present invention, a more particular description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It is understood that the drawings depict only typical embodiments of the invention and therefore are not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar symbols for clarity.

FIG. 1 shows a schematic flowchart of a method for constructing a memory chip package structure in an embodiment of the present invention.

2-5 show the structural diagrams of the construction process of a memory chip package structure in an embodiment of the present invention.

Fig. 6 shows a top view of a second chip in one embodiment of the present invention.

FIG. 7 shows a schematic diagram of a package structure of a memory chip in an embodiment of the present invention.

detailed description

It should be noted that components in the various figures may be shown exaggerated for the purpose of illustration and are not necessarily true to scale. In the various figures, identical or functionally identical components are assigned the same reference symbols.

In the present invention, unless otherwise specified, "arranged on", "arranged on" and "arranged on" do not exclude the presence of intermediates between the two. In addition, "arranged on or above" only means the relative positional relationship between two parts, and under certain circumstances, such as after the product direction is reversed, it can also be converted to "arranged under or below", and vice versa Of course.

In the present invention, each embodiment is only intended to illustrate the solutions of the present invention, and should not be construed as limiting.

In the present invention, unless otherwise specified, the quantifiers "a" and "an" do not exclude the scene of multiple elements.

It should also be pointed out here that in the embodiments of the present invention, for the sake of clarity and simplicity, only a part of parts or components may be shown, but those skilled in the art can understand that under the teaching of the present invention, specific The scene needs to add the required parts or components. In addition, unless otherwise stated, features in different embodiments of the present invention can be combined with each other. For example, a feature in the second embodiment may be used to replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the scope of disclosure or description of the present application.

It should also be pointed out that within the scope of the present invention, expressions such as "same", "equal", and "equal to" do not mean that the two values are absolutely equal, but allow a certain reasonable error, that is, the Wording also covers "substantially the same", "substantially equal", "substantially equal to". By analogy, in the present invention, the terms "perpendicular to", "parallel to" and the like referring to directions also cover the meanings of "substantially perpendicular to" and "substantially parallel to".

In addition, the numbers of the steps of the various methods of the present invention do not limit the execution sequence of the method steps. Unless otherwise indicated, the various method steps may be performed in a different order.

The present invention will be further described below in conjunction with specific embodiments with reference to the accompanying drawings.

FIG. 1 shows a schematic flowchart of a construction method of a memory chip package structure in an embodiment of the present invention. As shown in Figure 1, the method may include the following steps:

Step 101 , providing a first chip 201 .

Step 102 , constructing a groove 301 on the first surface of the first chip 201 .

Step 103 , arranging a control chip 401 at the groove 301 .

Step 104 , providing a second chip 501 , wherein the second chip 501 is provided with a storage area 502 .

Step 105 , stacking the first surface of the second chip 501 on the second surface of the first chip 201 .

2-5 show the structural diagrams of the construction process of a memory chip package structure in an embodiment of the present invention. The steps of the construction method will be specifically described below with reference to FIGS. 2-5 .

As shown in FIG. 2, in step 101, a first chip 201 may be provided, wherein a first storage area (not shown in the figure) is arranged on a second surface of the first chip 201, and a first storage area in the first storage area A first through-silicon via 202 (TSV) may be provided around the first chip 201 , and the first through-silicon via 202 may pass through the first surface and the second surface of the first chip 201 .

As shown in FIG. 3 , in step 102 , grooves 301 may be formed on the first surface of the first chip 201 through processes such as photolithography or etching.

As shown in FIG. 4 , in step 103 , a control chip 401 may be arranged at the groove 301 . By using the space on the back side of the first chip 201 to dig a cavity to embed the chip 401, the integration degree of three-dimensional packaging can be effectively improved.

As shown in FIG. 5 , in step 104, a second chip 501 can be provided, wherein a second storage area 503 is provided on the second chip 501, and a second silicon through silicon is provided around the second storage area 503. hole 502 . Figure 6 shows a top view of a second chip 501 in one embodiment of the present invention, as shown in Figure 6, the second chip 501 may include a plurality of second storage areas 503, the number of the second storage areas 503 Can be greater than or equal to 4.

FIG. 7 shows a schematic diagram of a package structure of a memory chip in an embodiment of the present invention. In step 105, the second chip 501 can be stacked on the first chip 201 to form the packaging structure shown in FIG. On the first chip 201 , during the stacking process, the first chip 201 and the second chip may be connected to each other through the first TSV 202 and the second TSV 502 .

As shown in Figure 7, the memory chip packaging structure may include:

The first chip 201, wherein a groove 301 is provided on the first surface of the first chip 201, and a control chip 401 is arranged at the groove 301;

A plurality of second chips 501 comprising a storage area, wherein a plurality of the second chips 501 are stacked on each other and on the first chip 201, wherein the first chip 201 and the plurality of second chips 501 The first TSV 202 and the second TSV 502 are connected to each other.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention disclosed herein should not be limited by the above-disclosed exemplary embodiments, but should be defined only in accordance with the appended claims and their equivalents.

Claims (10)

1. A method of constructing a memory chip package structure, comprising the steps of:

providing a first chip;

forming a recess on a first side of the first chip;

arranging a control chip at the groove;

providing a second chip, wherein a storage area is arranged on the second chip; and

stacking the first side of the second chip on the second side of the first chip.

2. The method of constructing a memory chip package of claim 1, further comprising:

constructing a first through-silicon-via on the first chip;

constructing a second through-silicon-via on the second chip; and

connecting the second through-silicon via with the first through-silicon via when the second chip is stacked on the first chip.

3. The method of claim 1, wherein the second chip comprises one or more memory regions.

4. The method of claim 3, wherein the number of the storage areas is greater than or equal to 4.

5. The method of claim 1, wherein a plurality of the second chips are provided, wherein a plurality of the second chips are stacked on top of each other.

6. A memory chip package structure constructed in accordance with the method of any one of claims 1-5, the structure comprising:

the chip comprises a first chip, a second chip and a third chip, wherein a groove is arranged on a first face of the first chip, and a control chip is arranged at the groove;

a second chip including a storage region, wherein a first side of the second chip is stacked on a second side of the first chip.

7. The memory chip package structure of claim 6, wherein the first chip further comprises a first through silicon via and the second chip further comprises a second through silicon via, wherein the first through silicon via is connected to the second through silicon via.

8. The memory chip package structure of claim 6, wherein the second chip comprises one or more memory regions.

9. The memory chip package structure of claim 8, wherein the number of the memory regions is greater than or equal to 4.

10. The memory chip package of claim 9, comprising:

a plurality of second chips, wherein a plurality of the second chips are stacked on one another.

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