CN115411510A - Manufacturing method of antenna package and antenna package - Google Patents

Abstract

A method for manufacturing an antenna package, comprising the following steps: providing a first intermediate body, the first intermediate body including a first circuit substrate, a feeder layer, and a second circuit substrate stacked, and the second circuit substrate is away from the A cavity is opened on the surface of the feeder layer, the first circuit substrate includes an antenna layer; a second intermediate body is provided, the second intermediate body includes a third circuit substrate and a chip, and the chip is located on the third circuit substrate the surface of the surface; the chip and the cavity are arranged correspondingly, and the first intermediate body and the second intermediate body are press-bonded to form the antenna package. The present application also provides an antenna packaging body.

Description

Manufacturing method of antenna package and antenna package

technical field

The present application relates to the field of antenna packaging, and in particular to a method for manufacturing an antenna packaging body and the antenna packaging body.

Background technique

With the advent of the 5G high-speed communication era, millimeter wave communication has gradually become the focus, and the design and application requirements of millimeter wave antennas are becoming more and more vigorous. Since the length of the transmission path in the millimeter-wave frequency band has a great influence on the signal amplitude loss, and the processing accuracy of the millimeter-wave antenna is very high, the packaged antenna technology with extremely short antenna feeder paths and high processing accuracy has become one of the mainstream technologies in the field of millimeter-wave antennas. one.

The usual antenna packaging technology includes: first covering the chip with molding resin, and then further processing the redistribution layer (RDL), or forming the RDL on the carrier and temporarily combining it with the chip, and then molding. The above-mentioned production methods usually require multiple wirings, which will increase the risk of peeling or skewing due to thermal effects; the temporary bonding materials used need to have high viscosity, high temperature resistance, and high chemical resistance. The combined process increases the cost.

Contents of the invention

In view of this, it is necessary to provide a manufacturing method of an antenna package that reduces the lamination process and reduces the cost, so as to solve the above-mentioned problems.

In addition, it is also necessary to provide an antenna package.

A method for manufacturing an antenna package, comprising the following steps: providing a first intermediate body, the first intermediate body including a first circuit substrate, a feeder layer, and a second circuit substrate stacked, and the second circuit substrate is away from the A cavity is opened on the surface of the feeder layer, the first circuit substrate includes an antenna layer; a second intermediate body is provided, the second intermediate body includes a third circuit substrate and a chip, and the chip is located on the third circuit substrate the surface of the surface; the chip and the cavity are arranged correspondingly, and the first intermediate body and the second intermediate body are press-bonded to form the antenna package.

In some embodiments, the step of forming the second intermediate body includes: providing the third circuit substrate, the third circuit substrate including a third dielectric layer and a third circuit layer stacked; One surface of the three-circuit substrate is electrically connected to the chips.

In some embodiments, the third circuit layer includes a copper layer, and the area of the copper layer along the stacking direction of the third circuit substrate is larger than the area of the chip, and the chip is located in the projected area of the copper layer Inside.

In some embodiments, the surface of the third circuit substrate facing away from the first intermediate body is the third dielectric layer.

In some embodiments, the first circuit substrate and the feeder layer are electrically connected through conductive paste, and the conductive paste overlaps in the lamination direction of the first intermediate body.

An antenna package, comprising a first circuit substrate, a feeder layer, a second circuit substrate, a third circuit substrate and a chip; the first circuit substrate includes an antenna layer; the feeder layer is located on a surface of the first circuit substrate; the second The circuit substrate is located on the surface of the feeder layer away from the first circuit substrate; the third circuit substrate is located on the surface of the second circuit substrate away from the feeder layer; the chip is embedded in the second circuit substrate and connected to the second circuit substrate. The third circuit substrate is electrically connected.

In some embodiments, the first circuit substrate further includes a first dielectric layer and a first circuit layer; the first dielectric layer and the first circuit layer are laminated, and at least part of the antenna layer is located on the The surface of the first dielectric layer is away from the feeder layer.

In some embodiments, the antenna layer includes an excitation radiation patch and a main radiation patch, the excitation radiation patch is located on the surface of the first dielectric layer away from the feeder layer, and the main radiation patch is embedded in in the first dielectric layer.

In some embodiments, the feeder layer includes an intermediate dielectric layer and an intermediate circuit layer, the intermediate circuit layer is located on opposite surfaces of the intermediate dielectric layer and is electrically connected through a conductive hole penetrating through the intermediate dielectric layer; the first The second circuit substrate includes a second dielectric layer and a second circuit layer stacked, and the second circuit layer is electrically connected to the middle circuit layer.

In some embodiments, the first circuit substrate includes a first dielectric layer, the feeder layer includes an intermediate dielectric layer, and the second circuit substrate includes a second dielectric layer, wherein the first dielectric layer and the The dielectric constant of the second dielectric layer is smaller than the dielectric constant of the intermediate dielectric layer, and the dielectric loss factor of the first dielectric layer and the second dielectric layer is smaller than the dielectric loss factor of the intermediate dielectric layer.

In some embodiments, the material of the first medium layer and the second medium layer is thermoplastic resin; the material of the intermediate medium layer is thermosetting resin.

In some embodiments, the third circuit substrate protrudes from the second circuit substrate.

The manufacturing method of the antenna package provided by the present application can form the antenna package by only one pressing process, which reduces the pressing process, saves costs, and reduces the risks brought by the pressing process, such as peeling off of various parts of the antenna package Or skewed; in addition, the manufacturing method of the present application does not need to use temporary bonding materials, further simplifying the manufacturing process and saving costs; moreover, the present application integrates various components (including antenna layers, ground layers, circuit layers, chips, etc.) In the antenna package, the signal loss between the various elements in the antenna package is reduced.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a first circuit substrate provided by an embodiment of the present application.

FIG. 2 is a schematic cross-sectional view of a feeder layer provided by an embodiment of the present application.

FIG. 3 is a schematic cross-sectional view of a second circuit substrate provided by an embodiment of the present application.

FIG. 4 is a schematic cross-sectional view of a first intermediate body including a first circuit substrate, a feeder layer and a second circuit substrate according to an embodiment of the present application.

Fig. 5 is a schematic cross-sectional view of the second intermediate body provided by the embodiment of the present application.

FIG. 6 is a schematic cross-sectional view of an antenna package obtained by laminating the first intermediate body shown in FIG. 4 and the second intermediate body shown in FIG. 5 according to an embodiment of the present application.

Description of main component symbols

The following specific embodiments will further illustrate the present application in conjunction with the above-mentioned drawings.

Detailed ways

In order to more clearly understand the above objects, features and advantages of the present application, the present application will be described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other. A lot of specific details are set forth in the following description to facilitate a full understanding of the application, and the described implementations are only a part of the implementations of the application, but not all of the implementations.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terminology used herein in the description of the application is only for the purpose of describing specific embodiments, and is not intended to limit the application. As used herein, the term "and/or" includes all and any combinations of one or more of the associated listed items.

In each embodiment of the present application, for the convenience of description and not to limit the present application, the term "connection" used in the specification and claims of the present application is not limited to physical or mechanical connection, no matter it is direct or indirect. of. "Up", "Down", "Above", "Bottom", "Left", "Right" and so on are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship is also corresponding Change.

Referring to FIG. 1 to FIG. 6, the embodiment of the present application provides a method for manufacturing an antenna package 100, including the following steps:

Step S1: Please refer to FIG. 1 to FIG. 4 to provide a first intermediate body 10, which includes a stacked first circuit substrate 12, a feeder layer 14, and a second circuit substrate 16. The second circuit A cavity 166 is defined on a surface of the substrate 16 away from the feeder layer 14 .

Please refer to FIG. 1 , the first circuit substrate 12 includes an antenna layer 126 , a first dielectric layer 122 and a first circuit layer 124 . The first dielectric layer 122 is stacked with the first circuit layer 124 . At least part of the antenna layer 126 is located on the surface of the first dielectric layer 122 away from the feeder layer 14 .

Please refer to FIG. 2 , the feeder layer 14 includes an intermediate dielectric layer 142 and an intermediate circuit layer 144 , the intermediate circuit layer 144 is located on opposite surfaces of the intermediate dielectric layer 142 and passes through the conductive hole 143 passing through the intermediate dielectric layer 142 electrical connection. The middle circuit layer 144 is electrically connected to the first circuit layer 124 .

Referring to FIG. 3 , the second circuit substrate 16 includes a stacked second dielectric layer 162 and a second circuit layer 164 , and the second circuit layer 164 is electrically connected to the intermediate circuit layer 144 .

The cavity 166 runs through at least part of the second dielectric layer 162 . In this embodiment, the cavity 166 also penetrates through at least part of the second circuit layer 164 . The size of the cavity 166 can be set according to the volume and quantity of the chips 24 to be accommodated subsequently.

The material of the first dielectric layer 122 and the second dielectric layer 162 is thermoplastic resin; the material of the intermediate dielectric layer 142 is thermosetting resin. The _Dk of the first dielectric layer 122 and the second dielectric layer 162 is less than the _Dk of the intermediate dielectric layer 142, and the _Df (dielectric loss factor) of the first dielectric layer 122 and the second dielectric layer 162 If it is smaller than D _f of the intermediate dielectric layer 142, the signal loss can be reduced.

The cured modulus of the intermediate dielectric layer 142 is greater than the cured modulus of the first dielectric layer 122 and the second dielectric layer 162, and the intermediate dielectric layer 142 is cured before the subsequent pressing step, which can be a subsequent The lamination process provides rigid support to ensure the flatness of the antenna package 100 obtained after the lamination process; in addition, the thickness of the intermediate dielectric layer 142 can be selected in a wide range, and can be adjusted according to the requirements of the antenna package 100 for a specific frequency band. The thickness of the intermediate dielectric layer 142 is reduced, thereby reducing the stacking number of the first circuit substrate 12 and reducing the processing cost.

Please refer to FIG. 4 , the step of forming the first intermediate body 10 may be formed by sequentially stacking the first circuit substrate 12 , the feeder layer 14 and the second circuit substrate 16 and pressing them together. In some implementations, the step of pressing the first circuit substrate 12, the feeder layer 14, and the second circuit substrate 16 can also be followed by simultaneous pressing with the second intermediate body 20 to form the antenna package 100, that is, using The antenna package 100 is formed by one-step pressing.

Step S2 : Please refer to FIG. 5 , providing a second intermediate body 20 , the second intermediate body 20 includes a third circuit substrate 22 and a chip 24 , and the chip 24 is located on the surface of the third circuit substrate 22 .

The third circuit substrate 22 includes a third dielectric layer 222 and a third circuit layer 224 that are stacked. The chip 24 is electrically connected to the third circuit substrate 22 . The chip 24 protrudes from the surface of the third circuit substrate 22 .

The material of the third dielectric layer 222 may be the same as that of the second dielectric layer 162 , for example, thermoplastic resin.

The number of chips 24 may be one or more. When there are multiple chips 24 , the multiple chips 24 are located on the same surface of the third circuit substrate 22 .

In some embodiments, the second intermediate 20 can be formed by the following steps:

Step S201 : providing a third circuit substrate 22 , the third circuit substrate 22 includes a third dielectric layer 222 and a third circuit layer 224 stacked.

The number of layers of the third dielectric layer 222 and the third wiring layer 224 is not limited. The third circuit substrate 22 is not only used for electrical connection with the first intermediate body 10, but also used for electrical connection with external circuits. The length of the third circuit substrate 22 along the extension direction L2 of the third circuit substrate 22 (perpendicular to the stacking direction L1 of the third dielectric layer 222 and the third circuit layer 224) is greater than the length of the first intermediate body 10 .

Step S202 : electrically connect the chip 24 on a surface of the third circuit substrate 22 .

The chip 24 is electrically connected to the third circuit layer 224 through the conductive paste 30 . In this embodiment, the conductive paste 30 penetrates through a third dielectric layer 222 located on the surface of the third circuit substrate 22 , so as to be electrically connected to the chip 24 . Wherein, the conductive paste 30 may be copper paste or solder paste.

Step S3 : Please refer to FIG. 6 , arrange the chip 24 corresponding to the cavity 166 , press the first intermediate body 10 and the second intermediate body 20 to form the antenna package 100 .

In some embodiments, the chip 24 is staggered from the areas with higher circuit density in the second circuit layer 164 and the third circuit layer 224, so as to prevent the chips 24 and circuit layers (including the second circuit layer 164 and the third circuit layer 164 and the Three circuit layers 224) are offset. In addition, the middle circuit layer 144 and the third circuit layer 224 include large-area copper layers 146, 2242 corresponding to the chips 24, wherein, along the stacking direction L1, the areas of the copper layers 146, 2242 are larger than the The area of the chip 24, in the pressing process, the chip 24 is located in the projected area of the copper layer 146, 2242, preventing the chip 24 and the circuit layer (including the second circuit layer 164 and the third circuit layer 224) from shifting .

Referring to FIG. 6 , the present application also provides an antenna package 100 , including a first intermediate body 10 and a second intermediate body 20 , and the first intermediate body 10 and the second intermediate body 20 are stacked.

The first intermediate body 10 includes a first circuit substrate 12 , a feeder layer 14 and a second circuit substrate 16 which are stacked.

The first circuit substrate 12 includes an antenna layer 126 , a first dielectric layer 122 and a first circuit layer 124 . The first dielectric layer 122 is stacked with the first circuit layer 124 . At least part of the antenna layer 126 is located on the surface of the first dielectric layer 122 away from the feeder layer 14 .

In some embodiments, the antenna layer 126 includes an excitation radiation patch 1262 and a main radiation patch 1264, the excitation radiation patch 1262 is located on the surface of the first dielectric layer 122 away from the feeder layer 14, the The main radiation patch 1264 is embedded in the first dielectric layer 122, the main radiation patch 1264 is set apart from the excitation radiation patch 1262, and the main radiation patch 1264 is electrically connected to the first circuit layer 124. connect.

The feeder layer 14 includes an intermediate dielectric layer 142 and an intermediate circuit layer 144 . The intermediate circuit layer 144 is located on opposite surfaces of the intermediate dielectric layer 142 and is electrically connected through a conductive hole 143 penetrating through the intermediate dielectric layer 142 . The middle circuit layer 144 is electrically connected to the first circuit layer 124 . Wherein, the intermediate circuit layer 144 includes a ground layer 1442 , and the ground layer 1442 is located on a surface of the intermediate dielectric layer 142 away from the first circuit substrate 12 .

In some embodiments, the distance between the main radiation patch 1264 and the excitation radiation patch 1262 may be 100 μm-500 μm; the distance between the excitation radiation patch 1262 and the ground layer 1442 may be 300μm-900μm.

The second circuit substrate 16 includes a stacked second dielectric layer 162 and a second circuit layer 164 , the second circuit layer 164 is electrically connected to the intermediate circuit layer 144 .

In some implementations, the first circuit layer 124 , the intermediate circuit layer 144 and the second circuit layer 164 are electrically connected through the conductive paste 30 , and there is no need to provide other connectors for electrical connection, which can reduce signal loss. The conductive paste 30 can be copper paste or solder paste.

In some implementations, the conductive paste 30 for electrically connecting the first circuit layer 124 and the intermediate circuit layer 144 overlaps in the stacking direction L1 (that is, by stacking holes), which can reduce the parasitic parameters of the first intermediate body 10 .

The material of the first dielectric layer 122 and the second dielectric layer 162 is thermoplastic resin; the material of the intermediate dielectric layer 142 is thermosetting resin. The _Dk of the first dielectric layer 122 and the second dielectric layer 162 is smaller than the _Dk of the intermediate dielectric layer 142, and the Df of the first dielectric layer 122 and the second dielectric layer 162 _is smaller than that of the intermediate dielectric layer 142 D _f , can reduce signal loss.

The cured modulus of the intermediate dielectric layer 142 is greater than the cured modulus of the first dielectric layer 122 and the second dielectric layer 162, and the intermediate dielectric layer 142 is cured before the subsequent pressing step, which can be a subsequent The lamination process provides rigid support to ensure the flatness of the antenna package 100 obtained after the lamination process; in addition, the thickness of the intermediate dielectric layer 142 can be selected in a wide range, and can be adjusted according to the requirements of the antenna package 100 for a specific frequency band. The thickness of the intermediate dielectric layer 142 is reduced, thereby reducing the stacking number of the first circuit substrate 12 and reducing the processing cost.

The second intermediate body 20 is adjacent to the second circuit substrate 16 . The second intermediate body 20 includes a third circuit substrate 22 and a chip 24 , the chip 24 is located on the surface of the third circuit substrate 22 and embedded in the second circuit substrate 16 .

The length of the third circuit substrate 22 in the extending direction L2 of the third circuit substrate 22 is greater than the length of the first intermediate body 10 , that is, the third circuit substrate 22 protrudes from the first intermediate body 10 . The third circuit substrate 22 can be directly used for electrical connection with an external circuit, and there is no need to additionally provide a connector for electrical connection, which can reduce signal loss.

The third circuit layer 224 can be electrically connected to the chip 24 and the second circuit layer 164 through the conductive paste 30 .

In some embodiments, the surface of the third circuit substrate 22 facing away from the first intermediate body 10 is the third dielectric layer 222, and the third dielectric layer 222 on the outermost layer can be used as an insulating protection layer, which can reduce the Steps to form additional protective layers.

The manufacturing method of the antenna package 100 provided in the present application can form the antenna package 100 by only one pressing, which reduces the pressing process, saves costs, and reduces the risks brought by the pressing process, such as the antenna package 100. Each part is peeled off or skewed; in addition, the manufacturing method of the present application does not need to use temporary bonding materials, which further simplifies the manufacturing process and saves costs; moreover, the present application integrates each component (including the antenna layer 126, the ground layer 1442, the circuit layer, and the chip) 24, etc.) are integrated in the same antenna package 100, reducing the signal loss between the various components in the antenna package 100.

The above embodiments are only used to illustrate the technical solutions of the present application without limitation. Although the present application has been described in detail with reference to the above preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present application can be modified or equivalently replaced All should not deviate from the spirit and scope of the technical solution of the present application.

Claims (10)

1. A method for making an antenna package, comprising the following steps: A first intermediate body is provided, the first intermediate body includes a first circuit substrate, a feeder layer, and a second circuit substrate stacked in layers, a cavity is opened on the surface of the second circuit substrate away from the feeder layer, the The first circuit substrate includes an antenna layer; providing a second intermediate body, the second intermediate body comprising a third circuit substrate and a chip, the chip being located on the surface of the third circuit substrate; and The chip and the cavity are arranged correspondingly, and the first intermediate body and the second intermediate body are press-bonded to form the antenna package. 2. The manufacturing method of the antenna package according to claim 1, wherein the step of forming the second intermediate body comprises: providing the third circuit substrate, the third circuit substrate including a third dielectric layer and a third circuit layer stacked; and The chip is electrically connected to a surface of the third circuit substrate. 3. The manufacturing method of the antenna package according to claim 2, wherein the third circuit layer comprises a copper layer, and the area of the copper layer along the stacking direction of the third circuit substrate is larger than that of the chip area, the chip is located within the projected area of the copper layer. 4 . The manufacturing method of the antenna package according to claim 2 , wherein the surface of the third circuit substrate facing away from the first intermediate body is the third dielectric layer. 5. The manufacturing method of the antenna package according to claim 1, wherein the first circuit substrate and the feeder layer are electrically connected through a conductive paste, and the conductive paste is laminated on the first intermediate body overlap in direction. 6. An antenna package, characterized in that it comprises: A first circuit substrate, including an antenna layer; a feeder layer located on a surface of the first circuit substrate; a second circuit substrate located on a surface of the feeder layer away from the first circuit substrate; a third circuit substrate located on a surface of the second circuit substrate away from the feeder layer; and A chip is embedded in the second circuit substrate and electrically connected to the third circuit substrate. 7. The antenna package according to claim 6, wherein the first circuit substrate further comprises a first dielectric layer and a first circuit layer; the first dielectric layer and the first circuit layer are laminated , at least part of the antenna layer is located on the surface of the first dielectric layer away from the feeder layer. 8. The antenna package according to claim 7, wherein the antenna layer includes an excitation radiation patch and a main radiation patch, and the excitation radiation patch is located on the first dielectric layer away from the feeder layer surface, the main radiation patch is buried in the first dielectric layer. 9. The antenna package according to claim 6, wherein the feeder layer comprises an intermediate dielectric layer and an intermediate circuit layer, the intermediate circuit layer is located on opposite surfaces of the intermediate dielectric layer and passes through the middle The conductive holes of the dielectric layer are electrically connected; the second circuit substrate includes a second dielectric layer and a second circuit layer stacked, and the second circuit layer is electrically connected to the intermediate circuit layer. 10. The antenna package according to claim 6, wherein the first circuit substrate comprises a first dielectric layer, the feeder layer comprises an intermediate dielectric layer, and the second circuit substrate comprises a second dielectric layer, Wherein, the dielectric constant of the first dielectric layer and the second dielectric layer is smaller than the dielectric constant of the intermediate dielectric layer, and the dielectric loss factor of the first dielectric layer and the second dielectric layer is smaller than the dielectric constant of the The dielectric loss factor of the intermediate dielectric layer.

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