CN115345099B - Method, electronic device, and medium for automatically generating chip verification platform - Google Patents
Method, electronic device, and medium for automatically generating chip verification platform Download PDFInfo
- Publication number
- CN115345099B CN115345099B CN202211056949.4A CN202211056949A CN115345099B CN 115345099 B CN115345099 B CN 115345099B CN 202211056949 A CN202211056949 A CN 202211056949A CN 115345099 B CN115345099 B CN 115345099B
- Authority
- CN
- China
- Prior art keywords
- verification
- dut
- generating
- verification platform
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention relates to a method, electronic equipment and medium for automatically generating a chip verification platform, wherein the method comprises the step S1 of acquiring { CF 1 ，CF 2 ，…CF M }; step S2, analyzing CF m To obtain I x m 、C x m 、Se x m 、bind x m 、items x m (ii) a Step S3, generating VIP x m A sequencer and Se contained therein x m Connect to establish VIP x m Connection to DUT generating VIP x m Of VIP x m Encapsulation to generate CF m The corresponding verification module generates a verification platform basic framework of the DUT; s4, constructing a top virtual sequence generator and Se x m Connecting corresponding sequence generators to generate a parent base class of the verification platform; and S5, setting user configuration information and/or adding a custom verification component, generating a verification platform subclass, and generating a verification platform of the DUT. The invention improves the efficiency and the accuracy of generating the chip verification platform.
Description
Technical Field
The present invention relates to the field of chip verification technologies, and in particular, to a method, an electronic device, and a medium for automatically generating a chip verification platform.
Background
In the chip verification process, a corresponding verification platform needs to be established for each Design Under Test (DUT), and the verification platform is closely related to the module connected to the DUT, and the interconnection relationship between the connected module and the DUT. If the verification platform is established for the DUT one by one directly based on the modules connected with the DUT and the interconnection relationship between the connected modules and the DUT, the efficiency is low and the errors are easy to occur. And as the chip scale is larger and larger, the defects of the existing mode for establishing the verification platform are more and more obvious, if the chip design is adjusted, the verification platform needs to be established again, the workload is large, and errors are easy to occur, so that the efficiency of establishing the chip verification platform is low, and the accuracy cannot be ensured.
Disclosure of Invention
The invention aims to provide a method, electronic equipment and medium for automatically generating a chip verification platform, and the efficiency and the accuracy of generating the chip verification platform are improved.
According to a first aspect of the present invention, there is provided a method for automatically generating a chip verification platform, including:
s1, generating a configuration file { CF (compact flash) based on the interconnection relationship between the DUT to be designed and M brother modules of the DUT and corresponding bus interface information 1 ，CF 2 ，…CF M }，CF m The value of M is a configuration file of the mth sibling module of the DUT, and the range of the value of M is 1 to M.
Step S2, analyzing CF m Get the corresponding 5 code files { F 1 m ,F 2 m ,F 3 m ,F 4 m ,F 5 m },F 1 m In which f (m) verification component packages { I) are stored 1 m ,I 2 m ,…I f(m) m }，F 2 m In which f (m) pieces of verification environment configuration information { C are stored 1 m ,C 2 m ,…C f(m) m },F 3 m In which f (m) sequencer handles { Se) are stored 1 m ,Se 2 m ,…Se f(m) m }，F 4 m In which f (m) pieces of interface bind information { bind are stored 1 m ,bind 2 m ,…bind f(m) m },F 5 m F (m) pieces of excitation sequence item information { items are stored in the device 1 m ,items 2 m ,…items f(m) m In which I x m 、C x m 、Se x m 、bind x m 、items x m Correspondingly, x has a value ranging from 1 to f (m).
Step S3, based on I x m 、C x m Generation of CF m Is marked as VIP x m To VIP x m Sequencer and Se of (1) x m Connection based on bind x m Establishing VIP x m Connection to DUT based on items x m Generating VIP x m Corresponding stimulation sequence to convert all VIPs x m Encapsulation to generate CF m Corresponding verification module, all CF m The corresponding verification module combinations generate a verification platform base architecture for the DUT.
S4, constructing a top-level virtual sequence generator and each Se in the basic framework of the verification platform x m The corresponding sequence generator establishes a connection and,and generating a parent base class of the verification platform.
And S5, setting user configuration information and/or adding a custom verification component in the verification platform parent base class to generate a verification platform subclass, and generating a verification platform of the DUT based on the verification platform subclass.
According to a second aspect of the present invention, there is provided an electronic apparatus comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of the first aspect of the invention.
According to a third aspect of the invention, there is provided a computer readable storage medium, the computer instructions being for performing the method of the first aspect of the invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the method, the electronic equipment and the medium for automatically generating the chip verification platform provided by the invention can achieve considerable technical progress and practicability, have wide industrial utilization value and at least have the following advantages:
the invention can automatically generate the verification platform father base class, covers more than eighty percent of the components of the verification platform, generates the verification platform subclass based on the user configuration information on the basis of the father base class, and further generates the verification platform of the DUT, thereby greatly improving the automation degree of generating the verification platform, reducing errors and improving the efficiency and the accuracy of generating the chip verification platform.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a flowchart of a method for automatically generating a chip verification platform according to an embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description will be given to specific embodiments and effects of a method, an electronic device and a medium for automatically generating a chip verification platform according to the present invention, with reference to the accompanying drawings and preferred embodiments.
The embodiment of the invention provides a method for automatically generating a chip verification platform, which comprises the following steps of:
s1, generating a configuration file { CF (compact flash) based on the interconnection relationship between a Design Under Test (DUT) and M brother modules of the DUT and corresponding bus interface information 1 ，CF 2 ，…CF M }，CF m The value of M is a configuration file of the mth sibling module of the DUT, and the range of the value of M is 1 to M.
The configuration file may be a Json, IPXACT, CSV, YMAL, or Excel configuration file. Sibling means a module of a chip that is at the same level in the chip design as the DUT and is interconnected by at least one bus interface.
Step S2, analyzing CF m Get the corresponding 5 code files { F 1 m ,F 2 m ,F 3 m ,F 4 m ,F 5 m },F 1 m In which f (m) verification component packages { I) are stored 1 m ,I 2 m ,…I f(m) m }，F 2 m In which f (m) pieces of verification environment configuration information { C are stored 1 m ,C 2 m ,…C f(m) m },F 3 m In which f (m) sequencer handles { Se) are stored 1 m ,Se 2 m ,…Se f(m) m }，F 4 m In which f (m) pieces of interface bind information { bind are stored 1 m ,bind 2 m ,…bind f(m) m },F 5 m F (m) pieces of excitation sequence item information { items are stored in the device 1 m ,items 2 m ,…items f(m) m In which I x m Is represented by F 1 m The xth verification component package of (1), C x m Is represented by F 2 m X verification environment configuration information of (1), se x m Is represented by F 3 m The xth sequencer handle, bind in x m Is represented by F 4 m The xth interface bind information, items in (1) x m Is represented by F 5 m The xth excitation sequence item information in (1). I.C. A x m 、C x m 、Se x m 、bind x m 、items x m Correspondingly, the value range of x is 1 to f (m), and f (m) is the number of bus interfaces between the DUT and the mth sibling module.
The code file may be a systemveilog code file or a UVM (Universal Verification method) code file. The verification component may specifically be a UVC component of the UVM. F 2 m In which is stored I x m Corresponding authentication Environment configuration information C x m . Each verification component includes a sequence generator (Sequencer), F 3 m In which is stored I x m Sequencer handle Se corresponding to the corresponding sequencer x m At a high level, se is added x m Linked to I x m The corresponding sequencer, such that the lower level sequencer executes on the corresponding handle. bin is syntax in systemveilog, and can establish the connection between Verification IP (VIP) and DUT through bin syntax, and each Verification component encapsulates a corresponding Verification VIP. I is x m The corresponding sequencer needs to receive the stimulus sequence entry to generate the corresponding stimulus, F, for the DUT 5 m In which is stored I x m Excitation sequence item information items corresponding to the corresponding sequence generators x m 。
Step S3, based on I x m 、C x m Generation of CF m Xth bus interface pair ofCorresponding verification IP example, denoted as VIP x m To VIP x m Sequencer and Se of (1) x m Connection based on bind x m Establishing VIP x m Connection to DUT based on items x m Generation of VIP x m Corresponding stimulation sequence to convert all VIPs x m Encapsulation to generate CF m Corresponding verification module, all CF m The corresponding verification module combinations generate a verification platform base architecture for the DUT.
S4, constructing a top-level virtual sequence generator (Vitural sequence) in the basic framework of the verification platform, and each Se x m And the corresponding sequence generator establishes connection to generate a verification platform parent Base class (Testbench Base).
Each sequence generator corresponds to one verification component and generates excitation based on one bus interface, but the excitation of the high level is to coordinate a plurality of bus interfaces to generate excitation and interact, so that a top virtual sequence generator is arranged for scheduling all the sequence generators.
And S5, setting user configuration information and/or adding a custom verification component in the verification platform parent base class, generating a verification platform subclass, and generating a verification platform of the DUT based on the verification platform subclass.
It should be noted that, through steps S1 to S4, a verification platform parent base class may be automatically generated based on the interconnection relationship between the DUT to be designed and the M sibling modules of the DUT and the corresponding bus interface information, where this part already contains 80% to 90% of the content of the verification platform, and the remaining part may be combined with user reconfiguration (reconfiguration) by inheriting the verification platform parent base class, or instantiating some other custom verification component, such as a Scoreboard (Scoreboard), to generate the verification platform of the DUT. The user reconfiguration may specifically add configuration information in the parent base class or cover part of the configuration information in the parent base class.
As an embodiment, the method further comprises:
and step S10, when the chip design is changed, re-executing the step S1 to the step S5, and updating the verification platform corresponding to the DUT. The automation of the generation of the verification platform is greatly realized based on the steps S1 to S5, so that when the chip design is changed, a new verification platform can be quickly and accurately generated, and the generation efficiency and accuracy of the verification platform are improved.
As an example, the step S1 includes:
step S11, obtaining M brother module information { CD) interconnected with design DUT to be tested 1 ，CD 2 ，…CD M },CD m Including identification of the mth sibling module and bus interface information between the mth sibling module and the DUT { IF } 1 m ，IF 2 m ，…IF f(m) m },IF x m The bus interface protocol comprises a bus interface protocol and a plurality of bus interface signals, wherein each bus interface signal comprises a signal direction, a signal width, a reset value and a default value.
Step S12, based on IF x m Determining a stimulus sequence between the mth sibling module and the DUT, wherein each bus interface signal corresponds to one stimulus sequence item;
step S13, based on { CD 1 ，CD 2 ，…CD M }、{IF 1 m ，IF 2 m ，…IF f(m) m } and IF x m Corresponding excitation sequence to generate { CF 1 ，CF 2 ，…CF M }。
Specifically, the chip according to the embodiment of the present invention is implemented as K1 component modules (Mod) arranged in a hierarchical manner 1 ,Mod 2 ,...,Mod K1 ) And K2 Atomic Units (AU) 1 ,AT 2 ,...,AT K2 )，K1>＝1，K2>=1, atomic unit exists pre-written RTL code.
The top-level component module (chip) has no parent component module, and the atomic unit has no child component module or child atomic unit; any module Mod except the top module i1 And arbitrary atomic units AU i2 All have only one parent component module, i1 takes values from 1 to K1, and i2 takes values from 1 to K2. The parent component module comprises Mod i1 And AU i2 And is compared Mod i1 And AU i2 One level higher. It can be seen that sibling modules may be constituent modules or atomic units.
Mod i1 Including unique identification MID of component modules i1 And Mod i1 Z1 (i 1) component module internal bus Interface (InI) list (InI) of component module and sub-atomic unit interconnection 1 ,InI 2 ,...,InI Z1(i1) ) And with Mod i1 Z2 (i 1) component module External bus Interface (External Interface) list (MExI) of sibling component modules and sibling atomic unit interconnection of (m 1) 1 ,MExI 2 ,...,MExI Z2(i1) )。
The chip also comprises K4 Design interconnection assemblY DIY (Design interconnection assemblY) = (X) 1 _Y 1 _CMD 1 ,X 2 _Y 2 _CMD 2 ,......，X K4 _Y K4 _CMD K4 ). Wherein, X i5 And Y i5 Belong to { Mod 1 ,Mod 2 ,...,Mod K1 ,AU 1 ,AU 2 ,...,AU K2 I5 ranges from 1 to K4; x i5 And Y i5 Component modules or sibling atomic units of each other, or X i5 Is Y i5 Or Y as a parent building block i5 Is X i5 The parent of (a) constitutes a module. X i5 And X i6 May be the same or different; y is i5 And Y i6 May be the same or different; the value of i6 ranges from 1 to K4.CMD i5 Belong to { IDF-ID 1 ，IDF-ID 2 ，...，IDF-IDK 3 }。
The bus Interface Description reconstruction library comprises K3 predefined bus Interface reconstruction structures IDF (Interface Description factor) = (IDF) 1 ,IDF 2 ,...,IDF K3 )，K3>And =0. Wherein, IDF i3 Including bus interface unique identification IDF-ID i3 Z4 (i 3) bus interface signals (Sig) i3 1 ,Sig i3 2 ,...,Sig i3 z4(i 3))，Sig i3 i4 Including signal directionSignal width Wid (i 3, i 4), reSeT (ReSeT) value (RST) i3i4 1 ，RST i3i4 2 ，...，RST i3i4 Wid(i 3, i 4)) and a Default (Default) value (Def) i3i4 1 ，Def i3i4 2 ，...，Def i3i4 Wid(i3,i4) ). i3 is from 1 to K3, i4 is from 1 to Z4 (i 3), and Z4 (i 3) is a function of i 3. IDF-ID i3 Associated with the bus protocol type. The bus protocol type is, for example, a standard bus protocol such as AXI bus protocol, AHB bus protocol, APB bus protocol, HBM bus protocol, PCIE bus protocol, SATA bus protocol, USB bus protocol, etc. in AMBA, or may be a non-standard custom bus protocol. The signal direction may be set to an Input direction (Input), an Output direction (Output), and a bidirectional direction (InOut). The signal width Wid (i 3, i 4) is signal Sig i3 i4 The number of signal lines (Wire) used. When one of the component modules is used as a design to be tested for verification, a corresponding chip verification IP needs to be set for each external bus interface to replace a brother component module corresponding to the design to be tested to interact with the design to be tested for verification.
As can be seen from the above description, { CD in step S11 can be acquired based on IDF and DIY 1 ，CD 2 ，…CD M And based on this, acquiring { CF 1 ，CF 2 ，…CF M And details of interconnection information between each sibling module and the DUT are recorded in the configuration file, so that a corresponding code file can be further generated based on the configuration information, and a verification platform parent base class is generated.
As an example, the step S2 includes:
step S21, analyzing CF m Based on IF x m Corresponding bus interface protocol generation I x m ，I x m Including the corresponding sequencer.
In addition, I x m May also include corresponding drivers and monitors.
Step S22, based on I x m Generating a corresponding experimentLicense environment configuration information C x m 。
It is understood that all existing ways of generating verification environment configuration information fall within the scope of the present invention.
Step S23, based on I x m The corresponding sequencer in (2) generates a corresponding sequencer handle Se x m 。
Step S24, based on IF x m Corresponding bus interface protocol and a plurality of bus interface signal generation bind x m 。
Step S25, based on IF x m Generating items for a corresponding plurality of bus interface signals x m 。
Step S26, based on all I x m 、C x m 、Se x m 、bind x m 、items x m Generating { F 1 m ,F 2 m ,F 3 m ,F 4 m ,F 5 m }。
As an example, in the step S3, based on I x m 、C x m Generation of CF m Is marked as VIP x m The method comprises the following steps:
step S31, based on I x m 、C x m The method comprises the steps of calling a preset verification IP class structure corresponding to a bus interface protocol to generate a corresponding verification IP instance, selecting different file lists based on the same verification IP class structure to generate the following four verification IP instances, realizing one-key switching among the four verification IP instances, not increasing user overhead, and keeping verification platforms consistent.
The first embodiment,
The verification IP example is a verification IP of a general non-standard bus interface and is applied to a Simulation (Simulation) process. A generic, non-standard bus-like structure includes: the device comprises a sequence generator, a sequence driving module, a clock component, a reset component, a control vector component, a data vector component and an interface module, wherein the device is connected with a design to be tested through the interface module, and the interface module comprises a clock interface unit, a reset interface unit, a control vector interface unit, an input data vector interface unit and an output data vector interface unit. The sequence generator is used for acquiring excitation sequence items and sending the excitation sequence items to the sequence driving module; the sequence driving module is used for caching the excitation sequence items and distributing the excitation sequence items to a control vector component or a data vector component according to bus interface signals corresponding to the excitation sequence items; the clock component is used for generating a clock signal and sending the clock signal to the design to be tested through the clock interface unit; the reset assembly is used for generating a reset signal and sending the reset signal to the design to be tested through the reset interface unit; the control vector component is used for splicing the received excitation sequence items into control vectors and sending the control vectors to the design to be tested through the control vector interface unit; the data vector component is used for splicing the received excitation sequence items into input data vectors and sending the input data vectors to the design to be tested through the input data vector interface unit; the system is also used for receiving response data sent by the design to be tested through the output data vector interface unit and splicing the response data into an output data vector; the control vector, the input data vector and the output data vector are all variable length vectors, and the vector length is related to the bus protocol.
Example two
The verification IP example is suitable for standard bus protocols and non-standard bus protocols, is applied to a Simulation (Simulation) process and comprises a system sequence generator, a configuration module, a first sequence generator, a second sequence generator, a first sequence driving module, a second sequence driving module and M standard bus protocol modules { IF } 1 ，IF 2 ，…IF M And non-standard bus protocol modules, where IF m The m standard bus protocol module; the device is connected with the design to be tested through one interface of M standard bus protocol modules and non-standard bus protocol modules. The configuration module is used for configuring the mapping relation between the excitation sequence items and the protocol; the system sequence generator is used for acquiring excitation sequence items and passing through the configuration moduleDetermining a protocol corresponding to the excitation sequence item, if the protocol is a standard bus protocol, sending the excitation sequence item to the first sequencer, and if the protocol is a non-standard bus protocol, sending the excitation sequence item to the second sequencer; the first sequence generator is used for sending the standard bus protocol excitation sequence item to the first sequence driving module; the second sequence generator is used for sending the nonstandard bus protocol excitation sequence item to the second sequence driving module; the first sequence driving module is used for caching the standard bus protocol excitation sequence items and distributing the standard bus protocol excitation sequence items to the corresponding standard bus protocol modules according to the protocol corresponding to the standard bus protocol excitation sequence items; the second sequence driving module is used for caching the nonstandard bus protocol excitation sequence items, splicing the nonstandard bus protocol excitation sequence items into vectors and sending the vectors to the nonstandard bus protocol module, wherein the vectors are variable-length vectors, and the length of the vectors is related to the corresponding nonstandard bus protocol; the standard bus protocol module is used for sending an excitation sequence item of a corresponding standard bus protocol to the design to be tested; and the nonstandard bus protocol module is used for sending the excitation sequence item of the corresponding nonstandard bus protocol to the design to be tested.
Example III,
The verification IP example is a verification IP of a general non-standard bus interface, and is applied to a Hardware acceleration (Hardware Emulation) process of chip verification, the device comprises a first verification IP and a second verification IP, wherein the first verification IP comprises a sequence generator, a sequence driving module, a first control vector component and a first data vector component; the second verification IP comprises a second control vector component, a second data vector component and an interface module; the first verification IP is not synthesizable; the second verification IP is synthesizable; the first verification IP and the second verification IP are connected through a conversion interface; the device is connected with the design to be tested through the interface module, and the interface module comprises a control vector interface unit, an input data vector interface unit and an output data vector interface unit. The sequence generator is used for acquiring excitation sequence items and sending the excitation sequence items to the sequence driving module; the sequence driving module is used for caching the excitation sequence items and distributing the excitation sequence items to a first control vector component or a first data vector component according to bus interface signals corresponding to the excitation sequence items; the first control vector component is used for splicing the received excitation sequence items into control vectors, converting the control structure through a corresponding conversion interface and sending the control vectors to the second control vector component; the second control vector component is used for sending the control structure body to a design to be tested through a control vector interface unit; and the first data vector component is used for splicing the received excitation sequence items into input data vectors, converting the input data vectors into an input structural body through a corresponding conversion interface, and sending the input structural body to the second data vector component. The second data vector component is used for sending the input data vector interface unit to the design to be tested; the output data vector interface unit is used for receiving response data sent by the design to be tested, splicing the response data to generate an output data vector structure, converting the output data vector structure into an output data vector through a corresponding conversion interface, and sending the output data vector structure to the first data vector component; the control vector, the input data vector and the output data vector are all variable length vectors, and the vector length is related to the bus protocol.
Example four,
The verification IP example is a verification IP supporting a standard bus protocol and a non-standard bus protocol, is applied to a Hardware acceleration (Hardware Emulation) process of chip verification, and comprises a first verification IP and a second verification IP, wherein the first verification IP comprises a system sequence generator, a configuration module, a first sequence generator, a second sequence generator, a first sequence driving module, a second sequence driving module and M first standard bus protocol modules { IF (intermediate frequency) modules) 1 ，IF 2 ，…IF M And a first non-standard bus protocol module; the second authentication IP comprises M second standard bus protocol modules { IE 1 ，IE 2 ，…IF M -and a second non-standard bus protocol module, wherein said first authentication IP is not synthesizable; the second verification IP is synthesizable; IF (intermediate frequency) circuit m For the mth first standard bus protocol module, IE m Is the m second standard bus protocol module；IF m And IE m The device is connected with the design to be tested through one of M second standard bus protocol modules and non-standard bus protocol modules. The configuration module is used for configuring the mapping relation between the excitation sequence items and the protocol; the system sequence generator is used for acquiring an excitation sequence item and determining a protocol corresponding to the excitation sequence item through the configuration module, if the excitation sequence item is a standard bus protocol, the excitation sequence item is sent to the first sequence generator, and if the excitation sequence item is a non-standard bus protocol, the excitation sequence item is sent to the second sequence generator; the first sequence generator is used for sending the standard bus protocol excitation sequence item to the first sequence driving module; the second sequence generator is used for sending the nonstandard bus protocol excitation sequence item to the second sequence driving module. The first sequence driving module is used for caching the standard bus protocol excitation sequence items and distributing the standard bus protocol excitation sequence items to the corresponding first standard bus protocol module according to the protocol corresponding to the standard bus protocol excitation sequence items. The second sequence driving module is used for caching the nonstandard bus protocol excitation sequence items, splicing the nonstandard bus protocol excitation sequence items into vectors and sending the vectors to the first nonstandard bus protocol module, wherein the vectors are variable length vectors, and the lengths of the vectors are related to the corresponding nonstandard bus protocols. The first standard bus protocol module is used for converting the standard bus protocol excitation sequence items into a standard bus protocol structural body through the corresponding conversion interface and sending the standard bus protocol structural body to the second standard bus protocol module. And the second standard bus protocol module is used for sending the standard bus protocol structure body to the design to be tested. The first nonstandard bus protocol module is used for converting the excitation sequence items of the nonstandard bus protocol into a nonstandard bus protocol structure body through the corresponding conversion interface and sending the nonstandard bus protocol structure body to the second nonstandard bus protocol module. And the second nonstandard bus protocol module is used for sending the nonstandard bus protocol structural body to the design to be tested.
It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
An embodiment of the present invention further provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor and configured to perform a method according to an embodiment of the invention.
The embodiment of the invention also provides a computer-readable storage medium, and the computer instructions are used for executing the method of the embodiment of the invention.
The embodiment of the invention can automatically generate the verification platform father base class, cover more than eighty percent of the verification platform, generate the verification platform subclass based on the user configuration information on the basis of the father base class, further generate the verification platform of the DUT, greatly improve the automation degree of generating the verification platform, reduce errors and improve the efficiency and the accuracy of generating the chip verification platform.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A method for automatically generating a chip verification platform is characterized by comprising the following steps:
s1, generating a configuration file { CF (compact flash) based on the interconnection relationship between the DUT to be designed and M brother modules of the DUT and corresponding bus interface information 1 ，CF 2 ，…CF M }，CF m The value range of M is 1 to M for the configuration file of the mth brother module of the DUT;
step S2, analyzing CF m Get the corresponding 5 code files { F 1 m ,F 2 m ,F 3 m ,F 4 m ,F 5 m },F 1 m In which f (m) verification component packages { I) are stored 1 m ,I 2 m ,…I f(m) m }，F 2 m In which f (m) pieces of verification environment configuration information { C are stored 1 m ,C 2 m ,…C f(m) m },F 3 m In which f (m) sequencer handles { Se) are stored 1 m ,Se 2 m ,…Se f(m) m }，F 4 m In which f (m) pieces of interface bind information { bind are stored 1 m ,bind 2 m ,…bind f(m) m },F 5 m F (m) pieces of excitation sequence item information { items are stored in the device 1 m ,items 2 m ,…items f(m) m In which I x m 、C x m 、Se x m 、bind x m 、items x m Correspondingly, the value range of x is 1 to f (m);
step S3, based on I x m 、C x m Generation of CF m Is marked as VIP x m To VIP x m Sequencer and Se of (1) x m Connection based on bind x m Establishing VIP x m Connection to DUT based on items x m Generating VIP x m Corresponding excitation sequences, allVIP x m Encapsulation to generate CF m Corresponding verification module, all CF m Generating a verification platform basic framework of the DUT by corresponding verification module combinations;
s4, constructing a top-level virtual sequence generator and each Se in the basic framework of the verification platform x m Establishing connection between corresponding sequence generators to generate a verification platform parent base class;
and S5, setting user configuration information and/or adding a custom verification component in the verification platform parent base class, generating a verification platform subclass, and generating a verification platform of the DUT based on the verification platform subclass.
2. The method of claim 1,
the step S1 includes:
step S11, obtaining M brother module information { CD) interconnected with design DUT to be tested 1 ，CD 2 ，…CD M },CD m Including identification of the mth sibling module and bus interface information between the mth sibling module and the DUT { IF } 1 m ，IF 2 m ，…IF f(m) m },IF x m The bus interface signal comprises a bus interface protocol and a plurality of bus interface signals, wherein each bus interface signal comprises a signal direction, a signal width, a reset value and a default value;
step S12, based on IF x m Determining a stimulus sequence between the mth sibling module and the DUT, wherein each bus interface signal corresponds to one stimulus sequence item information;
step S13, based on { CD 1 ，CD 2 ，…CD M }、{IF 1 m ，IF 2 m ，…IF f(m) m And IF x m Corresponding excitation sequence to generate { CF 1 ，CF 2 ，…CF M }。
3. The method of claim 2,
the step S2 comprises the following steps:
step S21, analyzing CF m Based on IF x m Corresponding bus interface protocol generation I x m ，I x m Including a corresponding sequencer;
step S22, based on I x m Generating corresponding verification environment configuration information C x m ；
Step S23, based on I x m The corresponding sequencer in (2) generates a corresponding sequencer handle Se x m ；
Step S24, based on IF x m Corresponding bus interface protocol and a plurality of bus interface signal generation bind x m ；
Step S25, based on IF x m Generating items for a corresponding plurality of bus interface signals x m ；
Step S26, based on all I x m 、C x m 、Se x m 、bind x m 、items x m Generating { F 1 m ,F 2 m ,F 3 m ,F 4 m ,F 5 m }。
4. The method of claim 1,
in the step S3, based on I x m 、C x m Generation of CF m Is marked as VIP x m The method comprises the following steps:
step S31, based on I x m 、C x m And calling a preset verification IP class structure corresponding to the bus interface protocol to generate a corresponding verification IP instance.
5. The method of claim 1,
the method further comprises the following steps:
and when the chip design is changed, re-executing the step S1 to the step S5, and updating the verification platform corresponding to the DUT.
6. The method of claim 1,
the configuration file is a Json, IPXACT, CSV, YMAL or Excel configuration file.
7. The method of claim 1,
the code file is a SystemVerilog code file or a UVM code file.
8. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-7.
9. A computer-readable storage medium having stored thereon computer-executable instructions for performing the method of any one of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211056949.4A CN115345099B (en) | 2022-08-31 | 2022-08-31 | Method, electronic device, and medium for automatically generating chip verification platform |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211056949.4A CN115345099B (en) | 2022-08-31 | 2022-08-31 | Method, electronic device, and medium for automatically generating chip verification platform |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115345099A CN115345099A (en) | 2022-11-15 |
| CN115345099B true CN115345099B (en) | 2023-03-28 |
Family
ID=83955031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211056949.4A Active CN115345099B (en) | 2022-08-31 | 2022-08-31 | Method, electronic device, and medium for automatically generating chip verification platform |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115345099B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116756049B (en) * | 2023-08-17 | 2023-11-07 | 上海燧原科技有限公司 | Universal verification methods, devices, electronic equipment and storage media for chips |
| CN117290254A (en) * | 2023-11-24 | 2023-12-26 | 沐曦集成电路(南京)有限公司 | Chip verification method based on component automation |
| CN120870834A (en) * | 2025-09-25 | 2025-10-31 | 沐曦集成电路(南京)有限公司 | Chip function testing methods, electronic devices and media based on Internet IP |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114265730A (en) * | 2021-11-23 | 2022-04-01 | 北京智芯微电子科技有限公司 | Platform and method for verifying module-level interrupts |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7237210B2 (en) * | 2005-02-08 | 2007-06-26 | International Business Machines Corporation | Methods, systems and media for managing functional verification of a parameterizable design |
| CN109684681B (en) * | 2018-12-06 | 2023-05-16 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | High-level verification method using UVM verification platform |
| CN113947048B (en) * | 2021-10-21 | 2023-06-27 | 杭州云合智网技术有限公司 | Interface connection method for verifying design to be tested and related equipment |
| CN114444420B (en) * | 2022-01-21 | 2025-06-17 | 山东云海国创云计算装备产业创新中心有限公司 | A verification IP integration method and system based on chip verification |
| CN114780143B (en) * | 2022-04-26 | 2025-08-12 | 北京全路通信信号研究设计院集团有限公司 | CAN controller excitation sequence generation method and device based on UVM and verification platform |
-
2022
- 2022-08-31 CN CN202211056949.4A patent/CN115345099B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114265730A (en) * | 2021-11-23 | 2022-04-01 | 北京智芯微电子科技有限公司 | Platform and method for verifying module-level interrupts |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115345099A (en) | 2022-11-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN115345099B (en) | Method, electronic device, and medium for automatically generating chip verification platform | |
| CN100399341C (en) | A Vector Mode Software-Hardware Co-simulation/Verification Method | |
| CN112632880B (en) | Compiling method for logic system design, electronic device, and storage medium | |
| CN106156424B (en) | Simulation system | |
| WO2016197768A1 (en) | Chip verification method, device, and system | |
| CN102798836B (en) | A kind of standardization control device of electric energy meter calibrating apparatus and control method | |
| CN113742221A (en) | Method for generating test case, electronic device and storage medium | |
| CN106844900B (en) | The Construction Method of Electromagnetic Transient Simulation System | |
| CN112287569B (en) | Method, electronic device and storage medium for simulating logic system design | |
| CN116048652A (en) | VIP verification-based reusability verification platform and verification method | |
| CN117370088A (en) | Performance test method and system for artificial intelligent accelerator card of domestic heterogeneous platform | |
| CN113947048B (en) | Interface connection method for verifying design to be tested and related equipment | |
| CN115496034A (en) | Multi-mode GPU joint simulation system | |
| CN115719047A (en) | Joint simulation system based on waveform GPU | |
| CN115688676A (en) | TLM-based GPU joint simulation system | |
| CN115686655A (en) | Joint simulation system for GPU IP verification | |
| CN112067978A (en) | FPGA screening test system and method based on FPGA | |
| US20210109154A1 (en) | Portable chip tester with integrated field programmable gate array | |
| CN115345122B (en) | Chip verification device for non-standard bus protocol of simulation | |
| CN112486833B (en) | An on-demand dynamic reconfigurable software testing system and method for software-defined satellites | |
| CN115345102A (en) | Universal chip verification device for hardware acceleration | |
| Guo et al. | A SPI interface module verification method based on UVM | |
| CN114942878A (en) | Automatic performance testing method for internet application and related equipment | |
| CN113947047B (en) | Interface connection method for verifying design to be tested and related equipment | |
| CN102541830A (en) | Method and device for generating simulation report in simulation platform |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |