CN115344522B

CN115344522B - Message conversion channel, message conversion device, electronic equipment and exchange equipment

Info

Publication number: CN115344522B
Application number: CN202211257952.2A
Authority: CN
Inventors: 朱珂; 姜海斌; 王盼; 吴佳骏; 刘长江; 袁晓妹
Original assignee: Jingxin Microelectronics Technology Tianjin Co Ltd
Current assignee: Jingxin Microelectronics Technology Tianjin Co Ltd
Priority date: 2022-10-14
Filing date: 2022-10-14
Publication date: 2023-01-03
Anticipated expiration: 2042-10-14
Also published as: CN115344522A

Abstract

The utility model provides a message conversion channel, a message conversion device, an electronic device and a switching device, which realize the improvement of message conversion efficiency by adopting a descriptor prefetching mechanism, and have larger throughput; in addition, through the parallel operation of at least two message conversion channels, each channel can process 1 message in progress, and further can support the parallel forwarding of at least two message messages, namely the number of the message messages supported at the same time is more; moreover, each channel supports an independent descriptor linked list, so that the electronic equipment can be processed in a centralized manner, and frequent operation of the electronic equipment is not required; finally, by means of the descriptor linked list and the descriptor pre-fetching mechanism, pipeline operation is achieved, bandwidth of a high-speed channel is fully utilized, and message processing efficiency is improved.

Description

Message conversion channel, message conversion device, electronic equipment and exchange equipment

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to a message conversion channel, a message conversion apparatus, an electronic device, and an exchange device.

Background

The RapidIO protocol and the PCIe protocol are currently common high-speed serial bus protocols. The conventional electronic equipment only supports the direct mounting of RapidIO equipment, and the scheme that most of electronic equipment mounts RapidIO equipment still realizes the connection with RapidIO equipment by externally arranging a PCIe-RapidIO bridge chip on a PCIe bus.

A message (also called a message) based on a RapidIO protocol is used as a message protocol of the RapidIO protocol, has a special structure and a special transmission mode, and can realize data unaddressed transmission. That is, for one device, a section of address space can be mapped by destID (destination device identification), mailbox (or xmelbox), and letter, thereby realizing address information isolation between communication devices. A single group of message messages can be transmitted in a slicing mode, the message messages can be cut into 16 message slices at most, each message slice can transmit 256 bytes of data at most, and a single message can transmit 4096 bytes of data at most. The user can distinguish and classify the message through the combination of the sourceID, destID, the mailbox, the xmailbox, the letter and other information in the message.

Disclosure of Invention

The disclosure provides a message conversion channel, a message conversion device, an electronic device and a switching device.

In a first aspect, the present disclosure provides a message conversion channel for converting a PCIe message into a RapidIO message, including:

the device comprises a descriptor prefetching circuit, a descriptor storage circuit, a data acquisition circuit, a data storage circuit, a message generation circuit and a descriptor state processing circuit which are electrically connected in sequence, wherein the descriptor prefetching circuit and the data acquisition circuit are respectively connected with an external PCIe module through a first PCIe interface and a second PCIe interface, the message generation circuit is connected with the external RapidIO module through a RapidIO interface, and the descriptor prefetching circuit and the data acquisition circuit are connected with the external RapidIO module through a RapidIO interface, wherein:

the descriptor prefetch circuitry configured to: generating and transmitting a descriptor prefetch request corresponding to the loaded descriptor address to an external PCIe module via the first PCIe interface; in response to receiving, via the first PCIe interface, a descriptor returned by an external PCIe module in response to the descriptor prefetch request, transmitting the received descriptor to the descriptor storage circuit for storage;

the data acquisition circuitry configured to: acquiring a message storage address in the current descriptor from the descriptor storage circuit, generating a message acquisition request according to the acquired message storage address, and transmitting the message acquisition request to the external PCIe module through the second PCIe interface;

the descriptor storage circuit is configured to: when the data acquisition circuit acquires the message storage address in the current descriptor from the descriptor storage circuit, the current descriptor is transferred to the descriptor state processing circuit;

the data acquisition circuitry is configured to: receiving message content returned by the external PCIe module in response to the message acquisition request through the second PCIe interface, and transmitting the message content to the data storage circuit for storage;

the message packet generation circuitry is configured to: and acquiring current message attribute information of the current descriptor from the descriptor state processing circuit, acquiring data from the data storage circuit according to the current message attribute information, converting the data into a message slice of the current message, and transmitting the message slice of the current message to the external RapidIO module through the RapidIO interface.

In some optional embodiments, the message conversion channel further comprises: descriptor state sending circuitry electrically connected with the descriptor state processing circuitry, the descriptor state sending circuitry being electrically connected to an external PCIe module through a third PCIe interface, wherein:

the message packet generation circuitry is further configured to: after all message slices of the current message are determined to be successfully sent, transmitting completion indication information for indicating that the current message is converted to be completed to the descriptor state processing circuit;

the descriptor state processing circuitry is configured to: releasing the current descriptor in response to the completion indication information and transmitting the current descriptor storage address to the descriptor state transmitting circuit;

the descriptor state transmitting circuit is configured to: and in response to the collection of a preset number of descriptor storage addresses or the reaching of a preset timeout duration, generating a descriptor state write message by using each collected descriptor storage address, and transmitting the descriptor state write message to an external PCIe module through the third PCIe interface.

In some optional embodiments, the descriptor prefetch request is a descriptor prefetch request corresponding to a loaded descriptor address and a number of descriptors.

In some optional embodiments, the descriptor prefetch circuitry is configured to: generating and sending a descriptor prefetch request corresponding to the loaded descriptor address to the first PCIe interface; in response to receiving, via the first PCIe interface, a descriptor returned by an external PCIe module in response to the descriptor prefetch request, transmitting the received descriptor to the descriptor storage circuit for storage, comprising: the descriptor prefetch circuitry is configured to:

in response to real-time monitoring that the number of stored descriptors of the descriptor storage circuit is smaller than a preset descriptor number threshold, determining whether the number of remaining descriptors to be fetched is smaller than a preset single prefetch descriptor number;

in response to determining that the number of remaining descriptors is less than the threshold number, generating a descriptor prefetch request comprising the loaded descriptor address and the number of remaining descriptors to fetch;

in response to determining not less than, generating a descriptor prefetch request that includes the loaded descriptor address and the preset number of single prefetch descriptors;

transmitting the generated description prefetch request to an external PCIe module via the first PCIe interface;

in response to receiving the descriptors returned by the external PCIe module in response to the descriptor prefetching request through the first PCIe interface, executing the following storage operations for each received descriptor according to the sequence of the received descriptor: determining whether the descriptor is a block descriptor; in response to determining that it is a block descriptor, updating the loaded descriptor address with a descriptor store address in the descriptor, and discarding the descriptor and subsequent other descriptors for which the store operation is no longer to be performed; in response to determining that it is not a block descriptor, transferring the descriptor to the descriptor storage circuit for storage;

and in response to the fact that the number of the descriptors stored in the descriptor storage circuit this time is larger than zero, subtracting the number of the descriptors stored this time from the number of the remaining descriptors to be fetched, and updating the address of the loaded descriptor to the address after the memory space corresponding to the number of the descriptors stored this time is moved. In a second aspect, the present disclosure provides a message conversion apparatus for converting a PCIe message into a RapidIO message, including: PCIe module, message conversion module and RapidIO module that the electricity connects in proper order, and with the PCIe module with register management circuit that the message conversion module electricity is connected respectively, wherein:

the PCIe module is electrically connected with external electronic equipment, and the RapidIO module is electrically or optically connected with the external RapidIO equipment;

the message conversion module comprises at least two message conversion channels as described in any embodiment of the first aspect, and the descriptor prefetch circuit and the data acquisition circuit in each message conversion channel are electrically connected to the PCIe module and the RapidIO module in parallel through a corresponding first PCIe interface, a second PCIe interface, and a RapidIO interface, respectively;

the RapidIO module is configured to: and sending the message slice generated by the message generating circuit in each message conversion channel.

In some optional embodiments, the PCIe module includes a PCIe control circuit and a PCIe scheduling circuit that are electrically connected, the RapidIO module includes a RapidIO control circuit and a RapidIO scheduling circuit that are electrically connected, the PCIe control circuit is electrically connected to an external electronic device, the PCIe scheduling circuit and the RapidIO scheduling circuit are both electrically connected to the message conversion module, the RapidIO control circuit is electrically connected to or optically connected to an external RapidIO device, the message conversion channels are connected in parallel, the descriptor prefetch circuit and the data acquisition circuit in each message conversion channel are respectively electrically connected to the PCIe scheduling circuit through a corresponding first PCIe interface and a second PCIe interface, and the message generation circuit in each message conversion channel is electrically connected to the RapidIO scheduling circuit through a corresponding RapidIO interface.

In a third aspect, the present disclosure provides an electronic device, comprising:

one or more processors;

a PCIe interface;

a storage device having one or more programs stored thereon,

the one or more programs, when executed by the one or more processors, cause the one or more processors to perform the operations of:

transmitting the descriptor starting address and the starting signal to an external PCIe module electrically connected with a PCIe interface of the electronic equipment;

in response to receiving a descriptor prefetch request including a loaded descriptor address via the external PCIe module, obtaining a descriptor corresponding to the descriptor prefetch request and transmitting the descriptor prefetch request to the external PCIe module;

and responding to a message acquisition request received from the external PCIe module, and transmitting message content corresponding to the message acquisition request to the PCIe module.

In some optional embodiments, the transmitting the descriptor start address and the initiation signal to an external PCIe module electrically connected to a PCIe interface of the electronic device, includes:

and transmitting the descriptor starting address, the total number of descriptors to be fetched and a starting signal to an external PCIe module electrically connected with a PCIe interface of the electronic equipment.

In some optional embodiments, the external PCIe module electrically connected to the PCIe interface of the electronic device includes PCIe control circuitry and PCIe scheduling circuitry, and the PCIe control circuitry of the external PCIe module is electrically connected to the PCIe interface of the electronic device.

In a fourth aspect, the present disclosure provides a switching device including the message conversion apparatus as described in any implementation manner of the second aspect.

One of the existing methods for converting a Message from a PCIe Message to a RapidIO is a conversion chip for converting PCIe to RapidIO, and the other method is implemented by an FPGA (Field Programmable Gate Array). However, the current message conversion method does not consider the particularity of the RapidIO message and other RapidIO messages, so that certain limitation is imposed on the transmission of the message when the message is processed, and the unique characteristic of the message cannot be fully exerted. In addition, the existing conversion method cannot meet the message distribution in the complex RapidIO network, only supports the simultaneous transmission of a group of incomplete message slices, and has low bus bandwidth utilization rate and throughput.

According to the message conversion channel, the message conversion device, the electronic equipment and the switching equipment, the message conversion efficiency is improved by adopting a descriptor prefetching mechanism, and the throughput is higher; in addition, through the parallel operation of at least two message conversion channels, each channel can process 1 message in progress, and further can support the parallel forwarding of at least two message messages, namely the number of the message messages supported at the same time is more; moreover, each channel supports an independent descriptor linked list, so that the electronic equipment can be processed in a centralized manner, and frequent operation of the electronic equipment is not required; finally, by means of the descriptor linked list and the descriptor pre-fetching mechanism, pipeline operation is achieved, bandwidth of a high-speed channel is fully utilized, and message processing efficiency is improved.

Drawings

Other features, objects and advantages of the present disclosure will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

FIG. 1A is a schematic diagram of a structure of one embodiment of a message conversion channel, according to the present disclosure;

FIG. 1B is a schematic block diagram of one embodiment of a message conversion apparatus according to the present disclosure;

FIG. 2A is a flow diagram for one embodiment of a message conversion method according to the present disclosure;

FIG. 2B is an exploded flow diagram for one embodiment of step 202 of a message conversion method according to the present disclosure;

FIG. 2C is a flowchart of an embodiment of step 204 of a message conversion method according to the present disclosure;

FIG. 2D is an exploded flow diagram illustrating one embodiment of the store operation in step 2041 of the message conversion method according to the present disclosure;

FIG. 3 is a schematic diagram of one embodiment of a data descriptor and a block descriptor according to the present disclosure.

Detailed Description

The present disclosure is described in further detail below with reference to the figures and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It should be noted that, for convenience of description, only the portions related to the related invention are shown in the drawings.

It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Referring to fig. 1A and fig. 1B, fig. 1A shows an embodiment 1A of a message conversion apparatus for converting a PCIe message into a RapidIO message according to the present disclosure, and fig. 1B shows an embodiment 301 of a message conversion channel for converting a PCIe message into a RapidIO message according to the present disclosure.

The message conversion apparatus 1a is configured to convert a PCIe message into a RapidIO message, and the message conversion apparatus 1a may include: PCIe module 20, message conversion module 30 and RapidIO module 40 that connect electrically in proper order to and register management circuit 60 that is connected electrically with PCIe module 20 and message conversion module 30 respectively, wherein:

the PCIe module 20 may be electrically connected with the external electronic device 10 on the PCIe side, and the RapidIO module 40 may be electrically or optically connected with the external RapidIO device 50 on the RapidIO side.

The message conversion module 30 includes at least two message conversion channels 301 as shown in fig. 1B. For example, message conversion module 30 shown in FIG. 1A includes 16 message conversion channels 301, …,316, and message conversion channels 301, …,316 may have the same structure as message conversion channel 301 shown in FIG. 1B. And the message conversion channels are connected in parallel.

As shown in fig. 1A and 1B, the message conversion channel 301 may include a descriptor prefetch circuit 3011, a descriptor storage circuit 3012, a data acquisition circuit 3013, a data storage circuit 3014, a message packet generation circuit 3015, and a descriptor state processing circuit 3016, which are electrically connected in sequence. The descriptor prefetch circuit 3011 and the data acquisition circuit 3013 in each message conversion channel are electrically connected to the PCIe module 20 through the corresponding first PCIe interface 30111 and second PCIe interface 30131, respectively, and the message packet generation circuit 3015 is electrically connected to the RapidIO module 40 through the RapidIO interface 30151.

Register management circuitry 60 is electrically coupled to each message conversion channel.

In practice, each component circuit of each message conversion channel may be provided with a register, and the external electronic device 10 may perform signal loading and writing on the register in each message conversion channel through the PCIe module and the register management circuit 60. The registers in the message conversion channel may include various registers, such as configuration registers, for receiving configuration data written by the external electronic device 10.

For a detailed description of the components, the message conversion channel, and the functions of the electronic device in the message conversion apparatus 1a, please refer to the related description below, which is not repeated herein.

In order to convert a PCIe message into a RapidIO message, a specific conversion process is specifically described below with reference to fig. 1A, fig. 1B, and fig. 2 shows a conversion method process 200 for converting a PCIe message into a RapidIO message according to the present disclosure, which includes the following steps:

in step 201, the electronic device transmits the descriptor address and the start signal to the descriptor prefetch circuit of the current message conversion channel in the message conversion module via the PCIe module.

Here, the electronic device 10 may transmit the descriptor address and the enable signal to the PCIe module 20 under the control of a sequence of program instructions. Here, the descriptor address is used to indicate a storage address of the descriptor to be prefetched in the electronic device. The PCIe module 20 may transmit the received descriptor address and enable signal to the register management circuit 60, and then the register management circuit 60 may load the descriptor address and enable signal to the descriptor prefetch circuit 3011 (as shown in S1 in fig. 1A) in the current message conversion channel 301 (the message conversion channel 301 is only used as an example for explanation, and in practice, any message conversion channel may be used) through the relevant configuration register in the current message conversion channel 301. Or the PCIe module 20 may also directly transmit the received descriptor address and start signal to the descriptor prefetch circuit 3011 in the current message conversion channel 301 through the first PCIe interface 30111 in the current message conversion channel 301 (as shown in S1 in fig. 1A).

It should be noted that, since the message conversion module 30 has at least two message conversion channels connected in parallel, in practice, which message conversion channels in the message conversion module 30 are the message conversion channels running in parallel may be specified by the electronic device. The PCIe module can adopt various implementation modes to determine the current message conversion channel in the message conversion channels running in parallel, and only one message conversion channel is the current message conversion channel at the same time. For example, the PCIe module may determine the current message translation channel using a polling policy.

In step 202, the descriptor prefetch circuit of the current message translation channel generates a descriptor prefetch request corresponding to the loaded descriptor address, and transmits the descriptor prefetch request to the PCIe module via the first PCIe interface.

Here, the descriptor prefetch circuit 3011 of the current message conversion channel 301 may generate a descriptor prefetch request corresponding to a loaded descriptor address in the case of the loaded descriptor address. The generated descriptor prefetch request is transmitted to the PCIe module 20 via the first PCIe interface 30111 (as shown in S2 in fig. 1A).

Here, the descriptor prefetch request may be, for example, a Memory Read request MRd (Memory Read request) conforming to the PCIe protocol.

In step 203, in response to receiving the descriptor prefetch request from the PCIe module, the electronic device transmits a descriptor corresponding to the descriptor prefetch request to the descriptor prefetch circuit in the current message conversion channel via the PCIe module.

The PCIe module may transmit the descriptor prefetch request to the electronic device 10 upon receiving the descriptor prefetch request from the first PCIe interface 30111 of the current message conversion channel 301.

However, the electronic device 10 may, when receiving the descriptor prefetch request transmitted by the PCIe module 20, first obtain a descriptor corresponding to the descriptor prefetch request, specifically, may parse the descriptor prefetch request to obtain a descriptor address, and then obtain the descriptor according to the descriptor address obtained by parsing. The retrieved descriptor may then be transmitted to the descriptor prefetch circuit 3011 in the current message conversion channel 301 via the PCIe module 20 (as shown at S3 in fig. 1A). Here, the electronic device may transmit the descriptor to the descriptor prefetch circuit 3011 in the current message conversion channel 301 via the PCIe module 20 using a CplD (Completion with data) packet compliant with the PCIe protocol.

Here, the descriptor is used to describe the message. The descriptor can read the message content data and generate the message content data according to the descriptor.

In step 204, the descriptor prefetch circuit of the current message conversion channel sends the received descriptor to the descriptor storage circuit for storage.

Here, the descriptor prefetch circuit 3011 of the current message conversion channel 301 may, in a case where a descriptor returned by the PCIe module 20 in response to the descriptor prefetch request is received via the first PCIe interface, send the received descriptor to the descriptor storage circuit 3012 for storage (as shown by S4 in fig. 1A).

In step 205, the data obtaining circuit of the current message conversion channel obtains the message storage address in the current descriptor from the descriptor storage circuit, and the descriptor storage circuit simultaneously stores the current descriptor to the descriptor state processing circuit.

Here, the data acquisition circuit 3013 of the current message conversion channel 301 acquires the message storage address in the current descriptor from the descriptor storage circuit 3012, while the descriptor storage circuit 3012 transfers the current descriptor to the descriptor state processing circuit 3016 (as shown in S5 in fig. 1A).

It should be noted that, in practice, at least one descriptor may be stored in the descriptor storage circuit 3012. When only one descriptor can be stored in the descriptor storage circuit 3012, the descriptor stored in the descriptor storage circuit 3012 is the current descriptor. When more than one descriptor may be stored in the descriptor storage circuit 3012, the descriptor stored at a specified location in the descriptor storage circuit 3012 may be the current descriptor. For example, when the descriptor storage circuit 3012 is a FIFO (First Input First Output) memory, the descriptor Output by the Output port of the descriptor storage circuit 3012 may be the current descriptor.

In addition, optionally, when the descriptor storage circuit 3012 spools the current descriptor into the descriptor state processing circuit 3016, since the message storage address in the current descriptor is no longer needed in the descriptor state processing circuit 3016, the descriptor storage circuit 3012 may spool the part of the current descriptor other than the message storage address into the descriptor state processing circuit 3016 to reduce the memory space requirement of the descriptor state processing circuit 3016.

In step 206, the data obtaining circuit of the current message conversion channel generates a message obtaining request according to the obtained message storage address, and transmits the message obtaining request to the electronic device through the PCIe module.

Here, the data obtaining circuit 3013 of the current message conversion channel 301 may first generate a message obtaining request MRd according to the message storage address obtained from the descriptor storage circuit 3012, and then transmit the message obtaining request to the electronic device 10 from the second PCIe interface 30131 via the PCIe module 20 (as shown in S6 in fig. 1A).

In step 207, the electronic device transmits the message content corresponding to the received message obtaining request to the data obtaining circuit of the current message conversion channel through the PCIe module.

Here, the electronic device 10 may, in response to receiving the message obtaining request sent by the PCIe module 20, parse the message storage address in the message obtaining request, obtain corresponding message content according to the message storage address, transmit the obtained message content to the second PCIe interface 30131 in the current message conversion channel 301 through the PCIe module 20, and finally transmit the message content to the data obtaining circuit 3013 of the current message conversion channel 301 (as shown in S7 in fig. 1A). Here, the electronic device 10 may transmit the message content to the PCIe module 20 using a CplD (Completion with data) message conforming to the PCIe protocol.

In step 208, the data acquisition circuit of the current message conversion channel transmits the received message content to the data storage circuit for storage. The data obtaining circuit 3013 of the current message conversion channel 301 may, in response to receiving the message content returned by the PCIe module 20 via the second PCIe interface 30131, transmit the received message content to the data storage circuit 3014 for storage (as shown in S8 in fig. 1A).

And step 209, the message generating circuit of the current message conversion channel acquires the current message attribute information of the current descriptor from the descriptor state processing circuit, acquires data from the data storage circuit according to the current message attribute information and converts the data into the message slice of the current message, and transmits the message slice of the current message to the external RapidIO module through the RapidIO interface.

Here, the message packet generating circuit 3015 of the current message conversion channel 301 may first obtain the message attribute information of the current descriptor from the descriptor state processing circuit 3016 as the current message attribute information (as shown in S9 in fig. 1A), then obtain data from the data storage circuit 3014 according to the current message attribute information (as shown in S9 in fig. 1A), then convert the data obtained from the data storage circuit 3014 into the message slice of the current message, and finally transmit the message slice of the current message to the RapidIO module 40 through the RapidIO interface 30151 (as shown in S10 in fig. 1A). It should be noted that, here, the message packet generating circuit 3015 may obtain data from the data storage circuit 3014 and perform message slice conversion when the data content continuously stored in the data storage circuit 3014 is greater than or equal to the message packet slice length in one piece of current message attribute information. In practice, data returned to the data storage circuit 3014 by using CplD packets may be stored out of order, and for this reason, the message packet generation circuit 3015 may generate a packet slice of the current message after performing address translation sorting according to the current message attribute information.

Through the above steps 201 to 209, the message content stored in the electronic device 10 can be converted into a message slice by the PCIe module and the message conversion module 30 and transmitted to the RapidIO module 40, and then finally transmitted to the external RapidIO device 50 by the RapidIO module 40.

In some cases, this embodiment may have the following optional implementations:

alternative embodiment (one): each message conversion channel (the following only takes the message conversion channel 301 as an example, and does not represent a specific limitation on the message conversion channel) may further include: the descriptor status sending circuit 3017 is electrically connected to the descriptor status processing circuit 3016, and the descriptor status sending circuit 3017 is electrically connected to the PCIe module 20 through the third PCIe interface 30171. Accordingly, the conversion method 200 may further include the following steps 212 to 214:

in step 210, the message generating circuit of the current message conversion channel transmits completion indication information indicating that the conversion of the current message is completed to the descriptor state processing circuit in response to the feedback signal indicating that all message slices of the current message are successfully transmitted.

It should be noted that, one descriptor correspondingly describes one message packet, and one message packet may be divided into a plurality of message slices. The message slices of the same message can be dispatched to the message generating circuits of the same message conversion channel, and can not be distributed to the message generating circuits of different message conversion channels.

The message generating circuit 3015 of the current message conversion channel 301 finishes transmitting a message slice to the RapidIO module 40, and the RapidIO module 40 also transmits the corresponding message slice to the RapidIO device 50. Next, the message generating circuit 3015 may receive a feedback signal (or referred to as a completion response signal) returned from the RapidIO device 50 via the RapidIO module 40, which indicates that the RapidIO device 50 has received the message slice. The message slices generated by the message generating circuit 3015 of the current message conversion channel in one operation process all correspond to the same message. The message packet generation circuit 3015 of the current message conversion channel 301 may transmit, in response to determining that the feedback signal indicating that all the packet slices of the current message have been successfully transmitted is received, completion indication information indicating that the conversion of the current message is completed to the descriptor state processing circuit 3016 (as shown in S11 in fig. 1A).

In step 211, the descriptor state processing circuit of the current message conversion channel releases the current descriptor in response to the completion indication information, and transfers the current descriptor storage address to the descriptor state transmitting circuit.

Here, the descriptor state processing circuit 3016 of the current message conversion channel 301 may, in response to receiving the completion indication information transmitted by the message packet generation circuit 3015, release the current descriptor stored in the descriptor state processing circuit 3016 (for example, the current descriptor may be set to an invalid state), and transmit the storage address of the current descriptor to the descriptor state transmitting circuit 3017 (as shown in S12 in fig. 1A). The storage address of the current descriptor may be stored in a relevant register of the current message conversion channel, and the descriptor state processing circuit 3016 may obtain the storage address of the current descriptor through the relevant register.

In step 212, the descriptor state sending circuit of the current message conversion channel generates a descriptor state write message by using the collected descriptor storage addresses in response to the collection of the preset number of descriptor storage addresses or the reaching of the preset timeout duration, and transmits the descriptor state write message to the electronic device through the third PCIe interface and the PCIe module.

Here, the descriptor state sending circuit 3017 of the current message conversion channel 301 may generate a descriptor state write message using each of the collected descriptor storage addresses in response to collecting a preset number of descriptor storage addresses or reaching a preset timeout duration, and transmit the descriptor state write message to the electronic device 10 via the third PCIe interface 30171 and the PCIe module 20 (as shown in S13 in fig. 1A). Here, the descriptor state write message may be an MWr (memory write request) message conforming to the PCIe protocol. In this manner, the electronic device 10 can learn from the descriptor status write message which specific descriptors were successfully transmitted.

Here, the preset number may be set by a skilled person in advance according to the positive correlation of the cache line sizes of the processors in the electronic device 10. For example, the preset number may be 8. For example, if the cache line (cache line) size of the processor in the electronic device 10 is 64 bytes, each descriptor storage address size needs to occupy 8 bytes, that is, 8 descriptor storage addresses need to occupy 64 bytes, and here, the preset number may be 8. That is, a cache line of a processor in the electronic device 10 may store up to 8 descriptor storage addresses in the future.

Here, the preset timeout period may be empirical data set in advance by a skilled person according to a period required for the descriptor state transmission circuit 3017 to collect a preset number of descriptor storage addresses in a normal case.

Alternative embodiment (b): PCIe module 20 may include PCIe control circuitry 21 and PCIe scheduling circuitry 22 electrically connected, rapidIO module 40 may include RapidIO control circuitry 41 and RapidIO scheduling circuitry 42 electrically connected, and electronic device 10 is electrically connected to PCIe control circuitry 21, rapidIO control circuitry 41 is electrically or optically connected to external RapidIO device 50. The message conversion channels are connected in parallel, the descriptor prefetch circuit 3011 and the data acquisition circuit 3013 in each message conversion channel are electrically connected to the PCIe scheduling circuit 22 through the corresponding first PCIe interface 30111 and second PCIe interface 30131, respectively, and the message packet generation circuit 3015 in each message conversion channel is electrically connected to the RapidIO scheduling circuit 42 through the RapidIO interface 30151.

Here, the PCIe scheduling circuit 22 is configured to determine, from among the message conversion channels designated by the electronic device 10 to be operated in parallel, a current message conversion channel for converting the current message corresponding to the current descriptor. The RapidIO scheduling circuit 42 is configured to determine, in each message conversion channel, a current message receiving channel for receiving the message slice. The specific scheduling manner of the PCIe scheduling circuit 22 and the RapidIO scheduling circuit 42 is not the key point of the technology of the present disclosure, and is not described herein again.

Alternative embodiment (c): the descriptor prefetch circuit of the current message conversion channel in step 202 generates a descriptor prefetch request corresponding to the address of the loaded descriptor, which may also be performed as follows: the descriptor prefetch circuit 3011 of the current message conversion channel 301 generates a descriptor prefetch request corresponding to the loaded descriptor address and the number of descriptors.

Here, the descriptor address may be a descriptor start address, and the number of descriptors is used to indicate the number of descriptors that the descriptor prefetch circuit 3011 prefetches from the electronic device 10 via the PCIe module 20. Accordingly, in step 203, the electronic device 10 may, in response to receiving the above-mentioned descriptor prefetch request from the PCIe module 20, retrieve the descriptor number descriptors in the descriptor prefetch request according to the descriptor start address in the descriptor prefetch request, and transmit the retrieved descriptors to the descriptor prefetch circuit 3011 in the current message conversion channel 301 via the PCIe module.

By adopting the optional implementation mode, a plurality of descriptors can be prefetched at one time, and the message conversion efficiency and the throughput are improved.

Alternative embodiment (iv): based on the above-mentioned alternative embodiment (three), the generating, by the descriptor prefetch circuit of the current message conversion channel in step 202, the descriptor prefetch request corresponding to the loaded descriptor address, and transmitting the descriptor prefetch request to the PCIe module via the first PCIe interface may specifically include steps 2021 to 2024 shown in fig. 2B:

in step 2021, in response to detecting in real time that the number of stored descriptors in the descriptor storage circuit is less than the threshold value of the number of descriptors, determining whether the number of remaining descriptors to be fetched is less than the preset number of descriptors to be prefetched once.

In practice, for example, the descriptor storage circuit 3012 may be provided with a counter to indicate in real time the number of descriptors already stored in the descriptor storage circuit 3012. Accordingly, the descriptor prefetch circuit 3011 may obtain the number of stored descriptors of the descriptor storage circuit 3012 through the counter in real time, and then determine whether the number of stored descriptors is smaller than a preset descriptor number threshold (e.g., 24) in real time.

If it is determined that the number is not smaller, it indicates that there are more descriptors stored in the descriptor storage circuit 3012, and it is necessary for the data fetch circuit 3013 to process the descriptors stored in the descriptor storage circuit 3012 at a certain time in the future, so the descriptor prefetch circuit 3011 may suspend prefetching descriptors. Therefore, only real-time monitoring needs to be continued.

If it is determined that the descriptor prefetch circuit 3011 prefetches the descriptors, it indicates that there are fewer descriptors already stored in the descriptor storage circuit 3012, and the data fetch circuit 3013 will soon complete processing of the descriptors stored in the descriptor storage circuit 3012. Therefore, if it is determined here to be less, the descriptor prefetch circuit 3011 may start descriptor prefetching, specifically, first determine whether the number of remaining descriptors to be fetched is less than a preset single prefetch descriptor number.

Here, the remaining number of descriptors to be fetched refers to the number of descriptors remaining in the electronic device 10 that have not yet been acquired.

Accordingly, the step 201 of the electronic device transmitting the descriptor address and the enable signal to the descriptor prefetch circuit of the current message conversion channel in the message conversion module via the PCIe module may include:

the electronic device 10 transmits the descriptor start address, the total number of descriptors to be fetched, and the enable signal to the descriptor prefetch circuit of the current message conversion channel in the message conversion module via the PCIe module.

In practice, the PCIe module may transmit the descriptor start address, the total number of descriptors to be fetched, and the enable signal to the message conversion channel 301 through the register management circuit 60, and registers for storing the descriptor start address, the total number of descriptors to be fetched, and the enable signal may be provided, respectively. The descriptor prefetch circuit 3011 may obtain the total number of descriptors to be fetched through the corresponding register, and then subtract the number of descriptors already read to obtain the number of descriptors remaining to be fetched for the descriptor chain in the electronic device 10.

Here, the preset number of single prefetch descriptors may be a number of descriptors that are prefetched at most consecutively by the descriptor prefetch circuit each time, which is preset by a skilled person according to the distribution of the number of block descriptors in the descriptor chain. Alternatively, the preset single prefetch descriptor number may be 8. This is to be taken into account that bandwidth may be wasted if there are more descriptors in a single consecutive prefetch, such as when there are more descriptor chains, and block descriptors may be encountered when a second descriptor is fetched if there are more descriptors in a single consecutive prefetch, and block descriptors fetched later will be useless. If there are fewer than 8 descriptors per single sequential prefetch, too few descriptors per single sequential prefetch results in wasted bandwidth for the PCIe module. In this way, it is possible to achieve both a reduction in the number of PCIe bandwidths occupied by descriptor prefetching as much as possible and a reduction in the waste of unexpected descriptors after a block descriptor due to the block descriptor. Alternatively, when the preset single prefetch descriptor number may be 8, the preset descriptor number threshold may be 24.

If it is determined that the number of remaining descriptors to be fetched is less than the preset number of single prefetch descriptors, it indicates that all remaining descriptors to be fetched in the electronic device 10 can be fetched, and therefore, it may proceed to step 2022.

On the contrary, if it is determined that the number of remaining descriptors to be fetched is not less than the preset number of single prefetch descriptors, it indicates that all the remaining descriptors to be fetched in the electronic device 10 may not be fetched, and only a part of them may be fetched, so that it may be proceeded to step 2023 for execution.

At step 2022, a descriptor prefetch request is generated that includes the address of the loaded descriptor and the number of descriptors remaining to be fetched.

Here, since it is determined in step 2021 that the number of remaining to-be-fetched descriptors is less than the preset number of single prefetch descriptors, indicating that all remaining to-be-fetched descriptors in the electronic device 10 can be fetched, the number of descriptors in the generated descriptor prefetch request may be the number of remaining to-be-fetched descriptors in the electronic device 10.

After the step 2022 is executed, the step 2024 is executed.

At step 2023, a descriptor prefetch request is generated that includes the loaded descriptor address and a predetermined number of single prefetch descriptors.

Here, since it is determined in step 2021 that the number of remaining to-be-fetched descriptors is not less than the preset number of single prefetch descriptors, which indicates that all remaining to-be-fetched descriptors in the electronic device 10 may not be fetched, but only the preset number of single prefetch descriptors may be prefetched at one time, the number of descriptors in the generated descriptor prefetch request may be the preset number of single prefetch descriptors.

After step 2023 is performed, go to step 2024 for execution.

In step 2024, the prefetch request is transmitted to the PCIe module via the first PCIe interface.

Alternative embodiment (v): based on the above-mentioned alternative embodiment (four), in step 204, the descriptor prefetch circuit of the current message conversion channel sends the received descriptor to the descriptor storage circuit for storage, which may include

steps

2041 and 2042 as shown in fig. 2C:

step 2041, in response to receiving the descriptor returned by the PCIe module in response to the descriptor prefetch request via the first PCIe interface, the descriptor prefetch circuit of the current message conversion channel executes a storage operation for each received descriptor in the order in which the descriptor is received.

In practice, when the electronic device 10 acquires the descriptors, the descriptors are acquired one by one from the descriptor start address, and the descriptors returned from the electronic device 10 via the PCIe module 20 are also generally arranged in the storage order in the electronic device 10. Therefore, the descriptor prefetch circuit 3011 of the current message conversion channel 301 may perform a store operation for each received descriptor in the order in which the descriptor was received. The storing operation may include steps 20411 through 20413 as shown in FIG. 2D:

at step 20411, it is determined whether the descriptor is a block descriptor.

The descriptor may specifically comprise a descriptor type. Wherein the descriptor type is used to indicate the type of the descriptor. In particular, the descriptor types may be two different types, data descriptors or block descriptors.

When the descriptor type in the descriptor is a data descriptor, the descriptor may include message attribute information and a message storage address, where the message attribute information may include attribute information of a message packet to be transmitted. For example, but not limited to, how many slices the message to be transmitted is sliced into, what each slice length is, and attribute information such as priority, mailbox, xmelbox, letter, and the like. The message storage address in the descriptor stores the storage address of the message to be transmitted in the electronic device 10.

When the descriptor type in the descriptor is a block descriptor, the descriptor is indicated as a connection descriptor, and the descriptor storage address of the next descriptor prefetching is stored in the descriptor.

Thus, if the descriptor is determined to be a block descriptor here, execution may proceed to step 20412. If it is determined that the descriptor is not a block descriptor, execution may proceed to step 20413.

Step 20412 updates the loaded descriptor address with the descriptor store address in the descriptor, and discards the descriptor and subsequent other descriptors on which no further store operations are performed.

That is, in the case where the descriptor is a block descriptor, since the descriptor storage address at the time of next prefetching of the descriptor is stored in the fast descriptor, the loaded descriptor address may be updated with the descriptor storage address in the descriptor, and the descriptor and the other descriptors in the following are discarded, and the storing operation is no longer performed on the descriptor and the other descriptors in the following.

After step 20412 is executed, the process goes to step 2042 for execution.

Step 20413 transfers the descriptor to the descriptor storage circuit for storage.

That is, in the case where the descriptor is a data descriptor, the message attribute information and the message storage address are stored in the data descriptor, and the descriptor can be transferred to the descriptor storage circuit 3012 and stored therein.

After step 20413 is executed, go to step 2042 for execution.

Step 2042, in response to determining that the number of descriptors stored in the descriptor storage circuit this time is greater than zero, subtracting the number of descriptors stored this time from the number of remaining descriptors to be fetched, and updating the address of the loaded descriptor to the address after the memory space corresponding to the number of descriptors stored this time is moved.

That is, if the number of descriptors stored in the descriptor storage circuit in step 2041 is greater than zero, indicating that a new descriptor is stored in the descriptor storage circuit 3012, the number of descriptors remaining to be fetched and the descriptor start address of the next prefetch, i.e., the address of the descriptor to be loaded into the descriptor prefetch circuit 3011, need to be updated. Specifically, the number of the remaining descriptors to be fetched minus the number of the descriptors stored this time may be obtained, and the address of the loaded descriptor may be updated to the address obtained by moving the storage space corresponding to the number of descriptors stored this time.

Referring specifically to fig. 3, a schematic diagram of data descriptors and block descriptors is shown in fig. 3. As can be seen from fig. 3, with this alternative embodiment, in order to transmit multiple messages, the electronic device 10 does not need to provide a descriptor corresponding to each message separately to the message conversion module 30, but only needs to provide the start addresses of the descriptors corresponding to multiple messages to be transmitted. In the descriptor storage block of the descriptor chain, addresses among data descriptors are continuous, and if address jump occurs, a block connection descriptor is added at the tail of the current descriptor. In this way, a longer length descriptor chain can be realized.

Here, it is assumed that N message conversion channels are included in the message conversion module 30, that is, the message conversion module 30 can process N descriptor chains at the same time, each message conversion channel can process only one descriptor chain at the same time, and the N message conversion channels can fetch descriptors of the N descriptor chains from the electronic device 10 in parallel. However, there is only one interface between the PCIe module 20 and the message conversion module 30, and there is only one interface between the message conversion module 30 and the RapidIO module 40, so that the PCIe scheduling circuit 22 and the RapidIO scheduling circuit 42 are required to perform message conversion scheduling and message transmission scheduling, respectively. From the above analysis, it can be known that the greater the number of message conversion channels in the message conversion module 30 (i.e. the greater N is), the stronger the processing capability of the message conversion module 30 is, the more requirements of the user can be processed, and for the user, only one description chain is needed to meet the requirements of the user. The N message conversion channels process N descriptor chains correspondingly. For example, N may be 16.

The message conversion channel and the message conversion device for converting the PCIe message into the RapidIO message provided by the disclosure can realize the following technical effects including but not limited to:

first, complex RapidIO network messaging can be handled.

Here, the message conversion apparatus provided by the present disclosure can process messages having the same message attribute information (e.g., destID, mailbox, and letter information) because at least two message conversion channels are provided in parallel. This is because, in general, the RapidIO module allocates an address according to the message attribute information of the message, and if two different sources send message messages with the same attribute information to the same RapidIO application, a complex scenario of memory confusion may be caused. In the message conversion apparatus provided by the present disclosure, when the electronic device side performs scheduling, the message attribute information of the message transmitted to the outside may be queried, and if there is a message with the same message attribute information, the electronic device 10 may perform unified scheduling on different message conversion channel components, thereby avoiding a complex scenario in which two different sources send a message with the same attribute information to the same RapidIO application. I.e. complex RapidIO network messages can be processed.

Second, each message conversion channel supports an independent descriptor chain table, so that the electronic device can process the descriptors in a centralized manner without frequent operation of the electronic device. That is, the electronic device does not need to send out a message and then prepare the descriptor of the next message, that is, the electronic device does not need to separately prepare the descriptor for each message to be transmitted, but only needs to form descriptor chains of all the descriptors of the messages to be transmitted and provide the descriptor chains to the message conversion module, the message conversion module can automatically prefetch the descriptors and complete the transmission of subsequent message messages, and the electronic device does not need to continuously schedule different descriptors to complete the transmission of the message messages.

Third, by employing at least two message conversion channels, each message conversion channel can be targeted to one application. For example, assuming 16 message conversion channels, 16 applications can be targeted, i.e., the application scenario is more complex.

Fourth, the message conversion apparatus provided by the present disclosure supports parallel operation of at least two message conversion channels, each channel can process 1 ongoing message, and if there are N message conversion channels, at most N messages can be forwarded in parallel. Although the bandwidth is unchanged, N descriptor chains can be processed simultaneously.

And fifthly, by adopting the combination of the descriptor chain table and the descriptor prefetching mechanism, the pipeline operation is realized, the bandwidth of a high-speed channel is fully utilized, and the message processing efficiency is improved. That is, the descriptor prefetch circuit may fetch one descriptor and then another descriptor, so as to implement parallel processing of the descriptors, including fetching message content data and also simultaneously fetching message content data corresponding to the two descriptors, and then sorting the message content data in the data storage circuit, which is equivalent to message content data that can be fetched in parallel. When the message is generated, serial processing is carried out according to the RapidIO protocol, and only one ongoing message is sent each time, namely, the message is processed in a parallel mode before and then processed in a serial mode after being processed in a parallel mode.

As another aspect, the present disclosure further provides a switching device, where the switching device may include the message conversion apparatus according to the foregoing embodiments and various optional implementations of the present disclosure.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional units in the embodiments of the present disclosure may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

The foregoing description is only exemplary of the preferred embodiments of the disclosure and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention in the present disclosure is not limited to the specific combination of the above-mentioned features, but also encompasses other embodiments in which any combination of the above-mentioned features or their equivalents is possible without departing from the inventive concept as defined above. For example, the above features and (but not limited to) the features disclosed in this disclosure having similar functions are replaced with each other to form the technical solution.

Claims

1. A message translation channel for translating PCIe messages to RapidIO message messages, comprising:

the descriptor prefetch circuitry configured to: generating and transmitting a descriptor prefetch request corresponding to the loaded descriptor address to an external PCIe module via the first PCIe interface; in response to receiving, via the first PCIe interface, a descriptor returned by an external PCIe module in response to the descriptor prefetch request, transmitting the received descriptor to the descriptor storage circuitry for storage;

2. The message conversion channel of claim 1, further comprising:

descriptor state sending circuit that is connected with descriptor state processing circuit electricity, descriptor state sending circuit passes through third PCIe interface electricity and connects outside PCIe module, wherein:

3. The message conversion channel of claim 1, the descriptor prefetch request being a descriptor prefetch request corresponding to a loaded descriptor address and a number of descriptors.

4. The message conversion channel of claim 3, wherein the descriptor prefetch circuit is configured to: generating and sending a descriptor prefetch request corresponding to the loaded descriptor address to the first PCIe interface; in response to receiving, via the first PCIe interface, a descriptor returned by an external PCIe module in response to the descriptor prefetch request, transmitting the received descriptor to the descriptor storage circuit for storage, comprising:

the descriptor prefetch circuitry is configured to:

in response to determining that the number of descriptors remaining to be fetched is less than the threshold number, generating a descriptor prefetch request comprising the loaded descriptor address and the number of descriptors remaining to be fetched;

in response to receiving the descriptors returned by the external PCIe module in response to the descriptor prefetching request through the first PCIe interface, executing the following storage operation for each received descriptor according to the sequence of receiving the descriptor: determining whether the descriptor is a block descriptor; in response to determining that it is a block descriptor, updating the loaded descriptor address with a descriptor store address in the descriptor, and discarding the descriptor and subsequent other descriptors for which the store operation is no longer to be performed; in response to determining that it is not a block descriptor, transferring the descriptor to the descriptor storage circuit for storage;

and in response to the fact that the number of the descriptors stored in the descriptor storage circuit this time is larger than zero, subtracting the number of the descriptors stored this time from the number of the remaining descriptors to be fetched, and updating the address of the loaded descriptor to the address after the memory space corresponding to the number of the descriptors stored this time is moved.

5. A message translation device for translating PCIe messages to RapidIO message messages, comprising: PCIe module, message conversion module and RapidIO module that the electricity connects in proper order, and with the PCIe module with register management circuit that the message conversion module electricity is connected respectively, wherein:

the message conversion module comprises at least two message conversion channels according to any one of claims 1 to 4, wherein the descriptor prefetch circuit and the data acquisition circuit in each message conversion channel are electrically connected in parallel with the PCIe module and the RapidIO module through a corresponding first PCIe interface, a second PCIe interface and a RapidIO interface respectively;

6. The message conversion apparatus according to claim 5, wherein the PCIe module includes a PCIe control circuit and a PCIe scheduling circuit electrically connected, the RapidIO module includes a RapidIO control circuit and a RapidIO scheduling circuit electrically connected, the PCIe control circuit is electrically connected to an external electronic device, the PCIe scheduling circuit and the RapidIO scheduling circuit are both electrically connected to the message conversion module, the RapidIO control circuit is electrically connected or optically connected to an external RapidIO device, the message conversion channels are connected in parallel, the descriptor prefetch circuit and the data fetch circuit in each message conversion channel are electrically connected to the PCIe scheduling circuit through a corresponding first PCIe interface and a second PCIe interface, respectively, and the message generation circuit in each message conversion channel is electrically connected to the RapidIO scheduling circuit through a corresponding RapidIO interface.

7. A switching device comprising a message conversion apparatus as claimed in any one of claims 5 to 6.