CN115332099B - Detection structure, preparation and detection method for pad overetching - Google Patents
Detection structure, preparation and detection method for pad overetching Download PDFInfo
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- CN115332099B CN115332099B CN202210963411.5A CN202210963411A CN115332099B CN 115332099 B CN115332099 B CN 115332099B CN 202210963411 A CN202210963411 A CN 202210963411A CN 115332099 B CN115332099 B CN 115332099B
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- 238000001514 detection method Methods 0.000 title claims abstract description 198
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 239000003990 capacitor Substances 0.000 claims abstract description 58
- 238000005530 etching Methods 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000005520 cutting process Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims description 32
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 238000007689 inspection Methods 0.000 claims description 8
- 238000012545 processing Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000012360 testing method Methods 0.000 claims description 4
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 238000012790 confirmation Methods 0.000 abstract description 3
- 238000012544 monitoring process Methods 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 53
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 239000011295 pitch Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/116—Manufacturing methods by patterning a pre-deposited material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/117—Manufacturing methods involving monitoring, e.g. feedback loop
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a detection structure, a preparation and a detection method for over-etching of a bonding pad, wherein a reference unit and a detection unit are formed in a wafer cutting area and are combined with a dielectric layer to form a reference capacitor and a detection capacitor, a dielectric layer detection window is arranged above the dielectric layer in the detection capacitor, and the detection bonding pad and the dielectric layer have larger selective etching ratio, so that the dielectric layer in the detection capacitor is etched in the etching process, the capacitance value of the detection capacitor is changed, and the over-etching condition of the bonding pad can be reflected by monitoring the electric performance data of the detection capacitor and the reference capacitor, namely the change of the capacitance value, and the slice confirmation is avoided.
Description
Technical Field
The invention belongs to the field of semiconductors, and particularly relates to a detection structure for over-etching of a bonding pad, a preparation method and a detection method.
Background
In the wafer process, it is often necessary to connect the components formed in the respective layers together to form a complete semiconductor device, or to connect the semiconductor device with other electronic components to form a desired electronic circuit, and to complete these connections, many PADs (PADs) are required to be formed, which may be said to be important connection components in the wafer process. For this reason, in the semiconductor field, there is a high demand for the pad in terms of conductivity and reliability.
In order to ensure the exposure of the bonding pad for subsequent electrical connection, an over-etching process exists in the existing preparation process, the common practice in the industry is to grab the Ti/TiN signal on the upper layer of the bonding pad and then etch the Ti/TiN for a certain time, or directly etch the default bonding pad after a certain time, the etching process has a certain risk, such as plasma (plasma) accumulation, or formation of lattice defects (CRYSTALDEFECT) and the like, so that the over-etching condition of the bonding pad needs to be detected, the over-etching process of the bonding pad can only be observed through Failure Analysis (FA) slicing, and the test convenience is extremely low.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a detection structure, a preparation method and a detection method for over-etching of a bonding pad, which are used for solving the problem that in the prior art, it is difficult to perform convenient operation on the over-etching detection of the bonding pad.
To achieve the above and other related objects, the present invention provides a sensing structure for pad overetching, comprising:
the substrate comprises a wafer active area and a wafer cutting area;
The reference unit is positioned in the wafer cutting area and is formed synchronously with the bonding pads positioned in the wafer active area, and comprises 2 reference bonding pads arranged at intervals and first detection bonding pads in one-to-one correspondence connection with the reference bonding pads;
The detection unit is positioned in the wafer cutting area and is formed synchronously with the bonding pads positioned in the wafer active area, the detection unit and the reference unit have the same appearance, and the detection unit comprises 2 detection bonding pads arranged at intervals and second detection bonding pads in one-to-one correspondence connection with the detection bonding pads;
the dielectric layer is positioned on the substrate and covers the substrate, the reference unit and the detection unit, and is provided with a dielectric layer detection window exposing the first detection pad and the second detection pad and a dielectric layer detection window exposing at least the dielectric layer positioned between the detection pads, wherein 2 correspondingly arranged reference pads are combined with the dielectric layer to form a reference capacitor, and 2 correspondingly arranged detection pads are combined with the dielectric layer to form a detection capacitor.
Optionally, the reference unit and the detection unit are simultaneously located in the wafer edge cutting area, simultaneously located in the wafer center cutting area, or simultaneously distributed in the whole wafer cutting area.
Optionally, the reference unit and the detection unit are located in a wafer dicing area of an adjacent chip.
Optionally, the dielectric layer comprises a silicon oxide dielectric layer, and the bonding pad comprises an aluminum bonding pad or an aluminum alloy bonding pad.
Optionally, the dielectric layer inspection window exposes the inspection pad.
The invention also provides a preparation method for the bonding pad over-etching detection structure, which comprises the following steps:
providing a substrate, wherein the substrate comprises a wafer active area and a wafer cutting area;
Forming a reference unit and a detection unit with the same shape on a wafer cutting area of the substrate, wherein the reference unit and the detection unit are synchronously formed with the bonding pads positioned in the wafer active area, the reference unit comprises 2 reference bonding pads arranged at intervals and first detection bonding pads connected with the reference bonding pads in a one-to-one correspondence manner, and the detection unit comprises 2 detection bonding pads arranged at intervals and second detection bonding pads connected with the detection bonding pads in a one-to-one correspondence manner;
forming a dielectric layer on the substrate, wherein the dielectric layer covers the substrate, the reference unit and the detection unit;
forming a mask layer on the dielectric layer, and patterning the mask layer;
Etching the dielectric layer to form a dielectric layer detection window exposing the first detection pad and the second detection pad and a dielectric layer detection window exposing at least the dielectric layer positioned between the detection pads, wherein 2 correspondingly arranged reference pads are combined with the dielectric layer to form a reference capacitor, and 2 correspondingly arranged detection pads are combined with the dielectric layer to form a detection capacitor.
Optionally, a bottom metal layer and a metal post connected with the bottom metal layer are also formed in the substrate.
The invention also provides a detection method for the over etching of the bonding pad, which comprises the following steps:
providing any one of the above detection structures;
Acquiring a reference capacitance value of the reference capacitor through the first detection bonding pad and a detection capacitance value of the detection capacitor through the second detection bonding pad by combining the dielectric layer detection window;
and comparing the acquired reference volume with the detection volume to detect the over etching of the bonding pad.
Optionally, the method of changing the detection capacitance includes changing one or a combination of thickness, length, pitch and size of the dielectric layer detection window of the correspondingly arranged 2 detection pads.
Optionally, the method further includes comparing the detected capacitance values of the detected capacitors in different wafer dicing areas to reflect differences in wafer processing in different areas.
As described above, the detection structure, the preparation and the detection method for the over etching of the bonding pad form the reference unit and the detection unit in the wafer cutting area and combine with the dielectric layer to form the reference capacitor and the detection capacitor, because the dielectric layer detection window is arranged above the dielectric layer in the detection capacitor, and the detection bonding pad and the dielectric layer have larger selective etching ratio, so that the dielectric layer in the detection capacitor is etched in the etching process, the capacitance value of the detection capacitor is changed, and the over-etching condition of the bonding pad can be reflected by monitoring the electric performance data of the detection capacitor and the reference capacitor, namely the change of the capacitance value, and the slice confirmation is avoided.
Drawings
Fig. 1 is a schematic view of a wafer structure according to a first embodiment of the invention.
Fig. 2 is an enlarged schematic view of a reference capacitor according to a first embodiment of the present invention.
Fig. 3 shows a schematic cross-sectional structure along A-A in fig. 2.
Fig. 4 is an enlarged schematic diagram of a detection capacitor according to a first embodiment of the invention.
Fig. 5 is a schematic cross-sectional view of fig. 4 along B-B.
Fig. 6 is a flowchart of a preparation process for a pad over-etching detection structure in a second embodiment of the invention.
Fig. 7 is a flowchart for pad over-etch detection in a third embodiment of the invention.
Description of element reference numerals
10. Wafer with a plurality of wafers
20. Wafer active region
30. Wafer dicing area
100. Substrate
101. Bottom metal layer
102. Metal column
211. Reference pad
212. First probe bonding pad
221. Detection bonding pad
222. Second probe bonding pad
300. Dielectric layer
301. Dielectric layer detection window
302. Dielectric layer detection window
Length of X
Y thickness
L spacing
S1-S5, sa-Sc steps
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present. In this regard, when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
The expression "between" is meant to include both end values, and the expression "plurality" is meant to mean two or more, unless specifically defined otherwise, as used herein. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
Example 1
As shown in fig. 1 to 5, the present embodiment provides a detection structure for pad over-etching, the detection structure includes:
a substrate 100, the substrate 100 comprising a wafer active region 20 and a wafer dicing region 30;
The reference unit is located in the wafer dicing area 30 and is formed synchronously with the bonding pads located in the wafer active area 20, and the reference unit comprises 2 reference bonding pads 211 arranged at intervals and first detection bonding pads 212 connected with the reference bonding pads 211 in a one-to-one correspondence manner;
The detecting unit is located in the wafer cutting area 30 and is formed synchronously with the bonding pads located in the wafer active area 20, and the detecting unit and the reference unit have the same shape, and the detecting unit comprises 2 detecting bonding pads 221 arranged at intervals and second detecting bonding pads 222 connected with the detecting bonding pads 221 in a one-to-one correspondence manner;
The dielectric layer 300 is disposed on the substrate 100 and covers the substrate 100, the reference unit and the detection unit, and has a dielectric layer detection window 301 exposing the first detection pad 212 and the second detection pad 222, and a dielectric layer detection window 302 exposing at least the dielectric layer 300 disposed between the detection pads 221, wherein 2 corresponding reference pads 211 and 300 are combined to form a reference capacitor, and 2 corresponding detection pads 221 and 300 are combined to form a detection capacitor.
Specifically, referring to fig. 1, in the process of preparing a wafer 10, typically, a wafer 10 will include several to several thousands to tens of thousands of chips, and dicing channels are disposed between adjacent chips to facilitate the subsequent dicing of the chips, in this embodiment, the area occupied by the chips in the wafer 10 is referred to as the active area 20, the area occupied by the dicing channels is referred to as the dicing area 30, and the detection structure according to the present application is preferably located in the dicing area 30 to reduce the occupation of the active area of the wafer.
In the process of manufacturing the wafer 10, a bonding pad, such as a surface of the chip, is disposed in the wafer active area 20 for facilitating subsequent electrical connection, and the bonding pad is preferably an aluminum bonding pad or an aluminum alloy bonding pad, but not limited thereto, and in the process of manufacturing, the surface of the bonding pad is covered with a passivation layer or other material layer, so that the material layer on the surface of the bonding pad needs to be etched to completely expose the conductive layer of the bonding pad, and in order to ensure complete opening of the surface of the bonding pad, over-etching is generally performed.
Referring to fig. 2 to 5, in this embodiment, in order to improve the detection of the over-etching condition of the pad, the reference pad 211, the first probing pad 212 in the reference cell, and the detection pad 221 and the second probing pad 222 in the detection cell are prepared in the wafer dicing area 30 while the pad is prepared. The detecting unit and the reference unit have the same shape, the first detecting pad 212 and the second detecting pad 222 are pin-inserted testing pads, and the reference pad 211 and the detecting pad 221 are combined with the dielectric layer 300 to form a plate capacitor structure, that is, the reference pad 211 and the detecting pad 221 can be regarded as plates of the plate capacitor.
In the process of etching to expose the pad, since the dielectric layer 300 and the pad material have different etching selectivity ratios, the rate at which the dielectric layer 300 is removed is greater than that of the pad, for example, the dielectric layer 300 may include a silicon oxide dielectric layer, but is not limited to this, so that the dielectric layer 300 in the detection capacitor has a larger loss through the dielectric layer detection window 302 in the dielectric layer 300, so that according to the capacitance principle, the capacitance value of the detection capacitor changes, and since the dielectric layer 300 above the reference capacitor does not have the dielectric layer detection window 302, that is, the upper part of the reference capacitor is covered by the dielectric layer 300, and in the etching process, the capacitance value of the reference capacitor is not changed, that is, the capacitance values of the reference capacitor are respectively corresponding to the capacitance value of the first detection pad 212 and the capacitance value of the second detection pad 222 are compared, that is, the capacitance value of the reference capacitor can be monitored, that is, the data of the capacitance value of the reference capacitor can be prevented from being etched, and the pad can be prevented from being subjected to the operation of slicing.
In this embodiment, regarding the structure of the substrate 100, it may include the bottom metal layer 101 and the metal pillars 102 in the passivation layer such as the silicon oxide layer as shown in fig. 2 and 3, but not limited thereto, and active or passive devices may be disposed in the substrate 100 according to need, which is not limited thereto.
As an example, the reference unit and the detection unit may be located at the edge dicing area of the wafer at the same time, at the center dicing area of the wafer at the same time, or distributed at the entire wafer dicing area at the same time.
Specifically, for the requirement of the over-etching detection of the bonding pads located in different areas on the wafer 10, the reference unit and the detection unit may be simultaneously disposed in the wafer edge cutting area, or simultaneously disposed in the wafer center cutting area, or simultaneously distributed in the whole wafer cutting area, which is not limited herein.
Further, in order to improve the accuracy of the detection structure in detecting the over-etching of the bonding pad, it is preferable that the reference unit, the detection unit, and the bonding pad to be detected are disposed close to each other, for example, the reference unit and the detection unit are located in a dicing area (dicing street) of a wafer to be detected adjacent to each other, and specific pitches may be set as required, which is not limited excessively herein.
Further, when comparing the detected capacitance values of the detected capacitors in different wafer dicing areas 30, the differences of the wafer process in different areas, such as processing differences, can be reflected, so as to optimize the wafer process.
As an example, the dielectric layer inspection window 302 may expose the inspection pad 221.
Specifically, when more consideration is given to the etching condition of the pad metal, the window opening of the dielectric layer detection window 302 may be increased (more or less of the pad metal is determined) as needed, and when the etching condition of the pad is to be reflected by the change of the dielectric layer 300, the window opening of the dielectric layer detection window 302 may be reduced, and the detection capacitance of the detection capacitor may be changed by changing the dielectric layer detection window 302 without being excessively limited with respect to the specific size of the dielectric layer detection window 302.
As shown in fig. 4 and fig. 5, the detection capacitance of the detection capacitor may be changed by changing one or a combination of the thickness Y, the length X, and the spacing L of the 2 detection pads 221 that are correspondingly disposed, or by changing the shapes of the detection pads 221 and the dielectric layer detection window 302 to change the detection capacitance of the detection capacitor, which may be specifically set as required.
Example two
As shown in fig. 6, the present embodiment provides a method for manufacturing a pad over-etching detection structure, which can be used to manufacture the detection structure in the first embodiment, but the manufacturing process of the detection structure is not limited thereto. In this embodiment, the following preparation process is used to prepare the above detection structure, so that the description of the detection structure can refer to embodiment one, and will not be repeated here.
Specifically, the preparation method can comprise the following steps:
s1, providing a substrate, wherein the substrate comprises a wafer active area and a wafer cutting area;
S2, forming a reference unit and a detection unit with the same shape on a wafer cutting area of the substrate, wherein the reference unit and the detection unit are synchronously formed with the bonding pads positioned in the wafer active area, the reference unit comprises 2 reference bonding pads arranged at intervals and first detection bonding pads in one-to-one correspondence with the reference bonding pads, and the detection unit comprises 2 detection bonding pads arranged at intervals and second detection bonding pads in one-to-one correspondence with the detection bonding pads;
S3, forming a dielectric layer on the substrate, wherein the dielectric layer covers the substrate, the reference unit and the detection unit;
s4, forming a mask layer on the dielectric layer, and patterning the mask layer;
And S5, etching the dielectric layer to form a dielectric layer detection window exposing the first detection bonding pad and the second detection bonding pad and a dielectric layer detection window exposing at least the dielectric layer positioned between the detection bonding pads, wherein 2 correspondingly arranged reference bonding pads are combined with the dielectric layer to form a reference capacitor, and 2 correspondingly arranged detection bonding pads are combined with the dielectric layer to form a detection capacitor.
The substrate may have a bottom metal layer and a metal pillar connected to the bottom metal layer, but is not limited thereto, and other active or passive devices may be disposed in the substrate according to need, which is not limited thereto.
Example III
As shown in fig. 7, the embodiment provides a method for detecting over-etching of a pad, which specifically includes the following steps:
providing the detection structure in the first embodiment;
Sb, in combination with the dielectric layer detection window, acquiring a reference capacitance value of the reference capacitor through the first detection pad, and acquiring a detection capacitance value of the detection capacitor through the second detection pad;
And Sc, comparing the acquired reference volume with the detection volume to detect the over etching of the bonding pad.
As an example, the method for changing the detection capacitance may include changing one or a combination of the thickness, the length, the pitch, and the size of the detection window of the 2 detection pads correspondingly disposed, which may be described in detail in the first embodiment, and will not be described herein.
As an example, the method may further include the step of comparing the detected capacitance values of the detected capacitors in different wafer dicing areas to reflect differences in wafer processing in different areas, such as processing differences.
As described above, the detection structure, the preparation and the detection method for the over etching of the bonding pad form the reference unit and the detection unit in the wafer cutting area and combine with the dielectric layer to form the reference capacitor and the detection capacitor, because the dielectric layer detection window is arranged above the dielectric layer in the detection capacitor, and the detection bonding pad and the dielectric layer have larger selective etching ratio, so that the dielectric layer in the detection capacitor is etched in the etching process, the capacitance value of the detection capacitor is changed, and the over-etching condition of the bonding pad can be reflected by monitoring the electric performance data of the detection capacitor and the reference capacitor, namely the change of the capacitance value, and the slice confirmation is avoided.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A test structure for pad overetching, the test structure comprising:
the substrate comprises a wafer active area and a wafer cutting area;
The reference unit is positioned in the wafer cutting area and is formed synchronously with the bonding pads positioned in the wafer active area, and comprises 2 reference bonding pads arranged at intervals and first detection bonding pads in one-to-one correspondence connection with the reference bonding pads;
The detection unit is positioned in the wafer cutting area and is formed synchronously with the bonding pads positioned in the wafer active area, the detection unit and the reference unit have the same appearance, and the detection unit comprises 2 detection bonding pads arranged at intervals and second detection bonding pads in one-to-one correspondence connection with the detection bonding pads;
the dielectric layer is positioned on the substrate and covers the substrate, the reference unit and the detection unit, and is provided with a dielectric layer detection window exposing the first detection pad and the second detection pad and a dielectric layer detection window exposing at least the dielectric layer positioned between the detection pads, wherein 2 correspondingly arranged reference pads are combined with the dielectric layer to form a reference capacitor, and 2 correspondingly arranged detection pads are combined with the dielectric layer to form a detection capacitor.
2. The detecting structure for over-etching of bonding pads according to claim 1, wherein the reference unit and the detecting unit are simultaneously located in an edge dicing area of a wafer, simultaneously located in a center dicing area of the wafer, or simultaneously distributed in a dicing area of a whole wafer.
3. The structure of claim 1, wherein the reference cell and the detection cell are located in a wafer dicing area of an adjacent chip.
4. The inspection structure for pad over-etching as set forth in claim 1 wherein the dielectric layer comprises a silicon oxide dielectric layer and the pad comprises an aluminum pad or an aluminum alloy pad.
5. The inspection structure for pad overetch as set forth in claim 1, wherein said dielectric layer inspection window exposes said inspection pad.
6. The preparation method for the bonding pad overetching detection structure is characterized by comprising the following steps of:
providing a substrate, wherein the substrate comprises a wafer active area and a wafer cutting area;
Forming a reference unit and a detection unit with the same shape on a wafer cutting area of the substrate, wherein the reference unit and the detection unit are synchronously formed with the bonding pads positioned in the wafer active area, the reference unit comprises 2 reference bonding pads arranged at intervals and first detection bonding pads connected with the reference bonding pads in a one-to-one correspondence manner, and the detection unit comprises 2 detection bonding pads arranged at intervals and second detection bonding pads connected with the detection bonding pads in a one-to-one correspondence manner;
forming a dielectric layer on the substrate, wherein the dielectric layer covers the substrate, the reference unit and the detection unit;
forming a mask layer on the dielectric layer, and patterning the mask layer;
Etching the dielectric layer to form a dielectric layer detection window exposing the first detection pad and the second detection pad and a dielectric layer detection window exposing at least the dielectric layer positioned between the detection pads, wherein 2 correspondingly arranged reference pads are combined with the dielectric layer to form a reference capacitor, and 2 correspondingly arranged detection pads are combined with the dielectric layer to form a detection capacitor.
7. The method of claim 6, wherein a bottom metal layer and a metal pillar connected to the bottom metal layer are further formed in the substrate.
8. A method for detecting over-etching of a bonding pad, comprising the steps of:
Providing a detection structure according to any one of claims 1 to 5;
Acquiring a reference capacitance value of the reference capacitor through the first detection bonding pad and a detection capacitance value of the detection capacitor through the second detection bonding pad by combining the dielectric layer detection window;
and comparing the acquired reference volume with the detection volume to detect the over etching of the bonding pad.
9. The method for detecting overetch of a pad according to claim 8, wherein the method of changing the detecting capacitance includes changing one or a combination of a thickness, a length, a pitch, and a size of the dielectric layer detecting window of the 2 detecting pads which are correspondingly disposed.
10. The method for detecting over-etching of a bonding pad according to claim 8, further comprising the step of comparing the detected capacitance values of the detecting capacitors located in different wafer dicing areas to reflect differences in wafer processing in different areas.
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| CN202210963411.5A CN115332099B (en) | 2022-08-11 | 2022-08-11 | Detection structure, preparation and detection method for pad overetching |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112713113A (en) * | 2021-01-14 | 2021-04-27 | 长鑫存储技术有限公司 | Inclination angle prediction method and device, equipment monitoring method, medium and equipment |
| CN112838073A (en) * | 2019-11-25 | 2021-05-25 | 格科微电子（上海）有限公司 | Electrical test structure for wafer bonding and method of forming the same |
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