CN1153290C - Electrostatic discharge protection arrangement method with current uniform distribution characteristic - Google Patents

Abstract

The invention provides a new method for electrostatic discharge (ESD) protection arrangement, which can enable a CMOS element to have the characteristic of current uniform distribution and greatly improve the voltage resistance of the CMOS element to electrostatic discharge in a submicron manufacturing process. The CMOS transistor structure of the present invention includes a semiconductor substrate having a P-well or N-well, a gate structure between the drain and the source, a lightly doped drain region in the P-well or N-well, and an ESD layout region having the same polarity as the P-well or N-well, formed under the drain region and surrounding the drain region upwardly corresponding to the drain contact.

Description

Arrangement method for electrostatic discharge protection with uniform current distribution characteristics

technical leadership

The invention relates to an electrostatic discharge (electrostatic discharge) protection arrangement method, which can make the semiconductor element have the characteristics of uniform current distribution under the electrostatic discharge overvoltage, so the electrostatic discharge tolerance of the semiconductor element can be improved.

Background technique

The impact of electrostatic discharge is an important issue in the reliability of semiconductor integrated circuits today. As the miniaturization of MOS components enters the field of submicron, the thinner gate oxide layer is more susceptible to damage by electrostatic discharge. In terms of specifications, according to the human body model of electrostatic discharge, the input and output pins of IC products must be able to withstand an electrostatic discharge voltage of more than 2000 volts. Therefore, both the output and input pads of the IC must be equipped with electrostatic discharge protection circuits.

In the output buffer of CMOS IC, the output NMOS and PMOS elements are often designed to have a large element aspect ratio (W/L) in order to provide sufficient current for the output load. This large-sized output NMOS and PMOS It can be used as an electrostatic discharge protection component by itself. For example, in a 0.35 micron MOS manufacturing process, an output NMOS with an aspect ratio W/L of 300/0.5 (micron/micron) can withstand an electrostatic voltage greater than 2000 volts with a specific electrostatic discharge protection design. One way to improve the ESD withstand voltage performance of output NMOS and PMOS is to add ESD arrangements during the manufacturing process.

The structure of an output NMOS element as shown in FIG. 1 is shown in FIG. 2 . In order to improve the withstand voltage performance against electrostatic discharge, the layout of the output NMOS usually has a wider interval SDG, and the SDG value is about 3-5 microns. In the manufacturing process of even sub-micron CMOS, NMOS (or PMOS) is formed with a lightly doped drain region structure to overcome the hot carrier effect of short-channel devices. However, the lightly doped drain region structure is equivalent to forming a tip-like structure at the drain region close to the channel surface. When the NMOS is discharged by electrostatic discharge, the electrostatic discharge current will pass through the drain region and concentrate on the The lightly doped drain region structure is connected to the grounded source, which is shown in Figure 3. The region of the lightly doped drain region is usually a shallow junction with a depth of about ~0.02 microns. It has the highest bias electric field and a pointed structure, so the electrostatic discharge electrode is easy to discharge through this area, thus causing damage to the device.

In order to improve the electrostatic discharge withstand voltage performance of the output NMOS, the known method is to add an additional electrostatic discharge arrangement manufacturing process in the CMOS manufacturing process so as to form a drain region that does not have a lightly doped drain region tip structure, which is as Figures 4 and 5 show. The drain region without the structure of the lightly doped drain region can usually withstand high ESD voltage, and the ESD arrangement can be formed before or after the isolation layer of the gate oxide layer is formed. Such known methods are disclosed in several U.S. patents, such as U.S. Patent No. 5,416,036 (inventor is C.C.Hsue), No. 5,455,444 (C.C.Hsue), No. 5,496,751 (Y.H.Wei), No. 5,529,941 ( T.Y. Huang), No. 5,585,299 (C.C. Hsue), No. 5,672,527 (Lee), and No. 5,733,794 (P. Gilbert et al.). As shown in Figure 4, the lightly doped drain structure is included in an additional N region formed by the electrostatic discharge arrangement, or alternatively, the lightly doped drain structure may not be included, so that the drain is properly adjusted The distance between the contact and the gate can prevent NMOS from being damaged by electrostatic discharge caused by lightly doping the tip structure of the drain region. However, this method may cause hot electron effects, or a shorter service life of the device, compared to a typical MOSFET with a lightly doped drain region structure.

For NMOS with a lightly doped drain structure, another known method to improve the ESD withstand voltage is to try to form a junction with a low breakdown voltage under the drain diffusion region, so that the ESD current will be reversed. First pass through this junction instead of the above-mentioned lightly doped drain region tip structure, so as to achieve the purpose of protecting the device. That is, as shown in FIGS. 6 and 7 , a highly doped P+ material is implanted in the junction region under the drain contact, so that the breakdown voltage of the junction region can be reduced. As shown in Figure 7, the electrostatic discharge arrangement region is only located directly below the drain contact, including the center of the drain region of the junction, and the breakdown voltage of the junction depends on the p and n-type diffusion regions at the p-n junction doping concentration. For example, in a 0.25 micron and 3.3 volt CMOS manufacturing process, the original output NMOS with a slightly doped drain region structure has a breakdown voltage of about 8 volts. If the output NMOS is placed in a P+ (boron) arrangement, The breakdown voltage of the junction then drops to about 5 volts or so. Therefore, although the junction region of this electrostatic discharge arrangement adds a mask exposure manufacturing process, it can indeed effectively form a junction with a low breakdown voltage in the output NMOS. Such improved methods have been disclosed in U.S. Patent Nos. 5,374,565 (inventor C.C. Hsue), 5,581,104 (A. Lowrey and R.W. Chance), 5,674,761 (K.Z. Chang), and 5,953,601 (R.Y. Shiue et al.). The electrostatic discharge current path of this design is shown in Figure 8. The junction area below the drain contact has a lower breakdown voltage due to the electrostatic discharge arrangement, so the electrostatic discharge current tends to concentrate in this area and flow to the substrate Therefore, the electrostatic discharge arrangement area in the shallow junction is prone to high heat and melts the metal material of the drain contact, and the melted metal material flows downward to form the so-called "contact damage" ( contact spiking) phenomenon, thus causing damage to components.

Contents of the invention

The main purpose of the present invention is to provide a new method of electrostatic discharge arrangement, the method of this electrostatic discharge protection arrangement can make the CMOS element have the characteristics of uniform current distribution under the electrostatic discharge overvoltage, so it is more suitable for submicron manufacturing process In other words, the withstand voltage performance of CMOS components against electrostatic discharge can be greatly improved. The electrostatic discharge protection layout method with uniform current distribution characteristics includes the following steps: providing a semiconductor substrate with a P well or N well structure; forming a complementary field effect transistor in the P well or N well of the semiconductor substrate , the field effect transistor comprises a gate, a drain region, and a source region, and the gate comprises: a gate oxide layer, a gate electrode located on the gate oxide layer and two electrodes formed on the gate an isolation layer for the sidewall; a slightly doped drain region adjacent to the source region and the drain region is formed under the gate isolation layer, and the slightly doped drain region has the same conductivity type; forming an electrostatic discharge arrangement region under the drain region, the electrostatic discharge arrangement region has the same conductivity type as the P well or N well, and surrounds the drain region vertically corresponding to the drain contact.

To achieve this goal, the CMOS transistor structure provided by the present invention includes a semiconductor substrate with a P well or an N well, a gate structure between the drain and the source, and a slightly doped gate structure in the P well or the N well. The impurity drain region, and an ESD arrangement region having the same polarity as the P-well or the N-well, is formed under the drain region and surrounds the drain region upwardly corresponding to the drain contact.

Description of drawings

FIG. 1 is a cross-sectional view of a known NMOS with a lightly doped drain region structure.

FIG. 2 is a top view of FIG. 1 .

FIG. 3 is a diagram of an electrostatic discharge current path of a conventional NMOS with a lightly doped drain region structure.

Figure 4 is a known ESD arrangement method with N-type doping.

FIG. 5 is a top view of FIG. 4 .

Figure 6 is a known ESD arrangement method with P-type doping.

FIG. 7 is a top view of FIG. 6 .

Fig. 8 is a diagram of an ESD current path of a known P-type ESD arrangement element with P-type doping.

Fig. 9 is a cross-sectional view of a P-type electrostatic discharge arrangement in the first embodiment of the present invention.

FIG. 10 is a top view of FIG. 9 .

FIG. 11 is a cross-sectional view of the electrostatic discharge current discharge path in the first embodiment of the present invention.

FIG. 12 is a top view of a layout in the first embodiment of the present invention.

FIG. 13 is a top view of a layout in the first embodiment of the present invention.

FIG. 14 is a schematic diagram of the present invention applied to a 1.8V/3.3V I/O circuit.

FIG. 15 is a schematic diagram of a stacked NMOS applied to a 1.8V/3.3V I/O circuit in the first embodiment of the present invention.

FIG. 16 is a cross-sectional view of a P-type electrostatic discharge arrangement method in the second embodiment of the present invention.

Fig. 17 is a cross-sectional view of a P-type electrostatic discharge arrangement method applied to a field oxide layer element in the second embodiment of the present invention.

FIG. 18 is a cross-sectional view of a P-type electrostatic discharge arrangement method in the second embodiment of the present invention. Explanation of reference numbers:

101～isolating layer, 102～drain contact, 103～source area, 104～drain area, 105～electrostatic discharge arrangement area, 106～electrostatic discharge arrangement area, 107～electrostatic discharge arrangement area, 201～drain contact, 301～drain contact.

In addition, "drain" ~ 2, "gate" ~ 4, "source" ~ 3; "P well" in Figures 1, 3, 4, 6, 8, 9, 11, 16, 17, 18 ~ 10, "P-type substrate" ~ 1; Figure 2, 3. The drain contact in 10"~102; the "ESD arrangement area"~105 in Fig. 4, 7, 10, 11, 12, 15; "(ESD arrangement)"~(205) in Fig. 4; Fig. "Junction breakdown position" in 8 and 11 ~ 5; in Fig. 8 "ESD current gathers under the drain contact, which may easily cause the contact metal to melt and penetrate downward into the silicon material" ~ 6; Fig. 16, 17, 18 The "N well" in ~20.

Detailed ways

FIG. 9 is used to show an ESD layout of an NMOS device, and FIG. 10 is its relative layout.

As shown in FIGS. 9 and 10, according to the first embodiment of the present invention, an NMOS device with an electrostatic discharge protection design includes a gate structure with an isolation layer 101, a source region 103, and a drain contact 102. lower drain region 104 . A lightly doped drain region is formed under the isolation layer 101 . For example, the lightly doped drain region can be formed by ion implantation of, for example, phosphorous or arsenic, using energies and implant doses that are known in the art.

Referring to FIGS. 9 and 10 , a P-type ESD arrangement region 105 is formed under the drain region 104 , and its doping concentration is greater than that of the P-well. Referring to the top view of the layout shown in FIG. 10 , the electrostatic discharge arrangement area 105 is formed around the drain contact, or, as shown in FIG. 12 , the electrostatic discharge arrangement area can also be formed into a plurality of square areas. If the uniform distribution method is adopted, the electrostatic discharge current passing through the drain region 104 has a better current distribution, so the heat caused by the electrostatic discharge can be effectively dissipated, and the withstand voltage performance of the device against the electrostatic discharge can be improved. Figure 1 3 shows another variation of the layout. In this example, the electrostatic discharge layout area is composed of two rectangular areas and multiple square areas, which also have the effect of uniformly distributing the electrostatic discharge current and dissipating heat. The doping concentration in the electrostatic discharge arrangement region 105 is higher than that of other drain regions, so the pn junction formed by it has a relatively low breakdown voltage, and the pn junction below the drain contact 102 and beside the electrostatic discharge arrangement region 105 The drain junction region maintains a normal breakdown voltage, so its electrostatic discharge current path will be as shown in Figure 11, that is, an electrostatic discharge high voltage applied to an output NMOS will be dispersed between the drain contact 102 and the electrostatic discharge The junction region between the regions 105 is arranged, and is guided to the ground terminal VSS of the NMOS. The current path shown in FIG. 11 has a wider current distribution area than the conventional electrostatic discharge arrangement, so the current does not concentrate on the junction area under the drain contact 102 and easily cause contact damage.

FIG. 14 is a schematic diagram of the present invention applied to a 1.8V/3.3V I/O circuit. The ESD arrangement region 106 shown in FIG. 14 can be used to improve the ESD withstand voltage performance of the 1.8V/3.3V I/O circuit of the submicron CMOS IC. Fig. 15 is the layout of the stacked NMOS (Mn1 and Mn2) in Fig. 14, wherein the polysilicon gates of Mn1 and Mn2 are close to each other, and the electrostatic discharge arrangement region is arranged between the drain contact and the polysilicon gate of Mn1 In this way, when a high electrostatic discharge voltage occurs at the I/O bonding area, the electrostatic discharge arrangement area 106 can fully exert its function of protecting the stacked NMOS.

Referring to FIG. 16, according to the second embodiment of the present invention, in addition to the same electrostatic discharge arrangement region 107 as the first embodiment, an additional N well is further added under the drain contact 201. This N well is compared with The normal drain junction (junction depth about 0.15 microns) has an extremely deep junction depth (about 2 microns), so it can significantly reduce the damage effect of the drain contact, that is, this electrostatic discharge arrangement can further increase the static electricity of the component Discharge withstand voltage performance.

The ESD arrangement described above can also be applied to a device with a field-oxide (FOD) to improve its ESD withstand voltage performance. For example, in the N-type FOD shown in FIG. 17, the drain junction is subjected to the aforementioned electrostatic discharge arrangement manufacturing process except for the area directly below the drain contact 301. Further, this FOD can also form an above-mentioned Extra N-well to overcome the damage effect of the drain contact. In FIGS. 16 and 17 , the extra N well region and the ESD arrangement region 107 may also have overlapping regions as shown in FIG. 18 , so as to disperse the ESD discharge current and increase the layout flexibility.

The above description using the embodiment is for the convenience of explaining the content of the present invention, rather than restricting the present invention to the embodiment in a narrow sense. All changes made without departing from the spirit of the present invention fall within the scope of the claims of the present invention.

Claims (5)

1. A static discharge protection arrangement method with uniform current distribution characteristics, comprising the following steps: providing a semiconductor substrate with a P-well or N-well structure; Forming a complementary field effect transistor in the P well or N well of the semiconductor substrate, the field effect transistor includes a gate, a drain region, and a source region, and the gate includes: a gate oxide layer, a gate electrode located on the gate oxide layer and an isolation layer formed on two sidewalls of the gate; The isolation layer forms slightly doped drain regions adjacent to the source region and the drain region respectively under the gate isolation layer, and the slightly doped drain region has the same conductivity type as the drain region; An electrostatic discharge arrangement region is formed under the drain region, the electrostatic discharge arrangement region has the same conductivity type as the P well or the N well, and surrounds the drain region vertically corresponding to the drain contact. 2. The electrostatic discharge protection arrangement method with uniform current distribution characteristics as claimed in claim 1, wherein the electrostatic discharge arrangement region is formed as a plurality of rectangular regions, and the plurality of rectangular regions are spaced along both sides of the drain region configuration. 3. The electrostatic discharge protection arrangement method with uniform current distribution characteristics according to claim 1, wherein the electrostatic discharge arrangement area is arranged in a comb shape. 4. A static discharge protection arrangement method with uniform current distribution characteristics, comprising the following steps: providing a semiconductor substrate with a first P-well or N-well structure; A complementary field effect transistor is formed in the first P well or N well of the semiconductor substrate, the field effect transistor includes a gate, a drain and a source, and the gate includes: a gate oxide layer, a a gate electrode located on the gate oxide layer and an isolation layer formed on two sidewalls of the gate; forming a second N-well or P-well under the drain contact, and the conductivity type of the second well is opposite to that of the first well; The isolation layer forms slightly doped drain regions adjacent to the source region and the drain region respectively under the gate isolation layer, and the slightly doped drain region has the same conductivity type as the drain; An electrostatic discharge arrangement region is formed under the drain region, the electrostatic discharge arrangement region has the same conductivity type as the first P-well or N-well, and surrounds the drain region vertically corresponding to the drain contact. 5. The electrostatic discharge protection arrangement method with uniform current distribution as claimed in claim 4, wherein the second N well or P well is separated from or partially overlapped with the electrostatic discharge arrangement area.

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