CN115274461B - A packaging method for a packaging structure of a planar power device - Google Patents
A packaging method for a packaging structure of a planar power device Download PDFInfo
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- CN115274461B CN115274461B CN202210604881.2A CN202210604881A CN115274461B CN 115274461 B CN115274461 B CN 115274461B CN 202210604881 A CN202210604881 A CN 202210604881A CN 115274461 B CN115274461 B CN 115274461B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/01—Manufacture or treatment
- H10W40/03—Manufacture or treatment of arrangements for cooling
- H10W40/037—Assembling together parts thereof
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/20—Arrangements for cooling
- H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
- H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/421—Shapes or dispositions
- H10W70/438—Shapes or dispositions of side rails, e.g. having holes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/461—Leadframes specially adapted for cooling
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
- H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/877—Bump connectors and die-attach connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
本发明公开了一种应用于平面型功率器件的封装结构的封装方法，属于半导体封装技术领域。其采用芯片的正面的芯片下金属凸块倒装至立体金属框架的刻蚀面上，通过芯片下金属凸块、立体金属框架的折转实现芯片与PCB直接互联，精减了封装结构，避免了传统打线工艺，降低了封装电阻，增加了电流承载能力；同时缩短了芯片与外界互联距离，增强了芯片的导电效果。其提供了一种单面精准塑封、低温贴合保护膜的工艺，精简了封装工艺，相比与传统打线方式，FC工艺传输性能提升，互联结构尺寸短小，减少了电感，电阻以及电容，信号完整性，射频性能更好，提高了生产效率并降低了生产成本。
The present invention discloses a packaging method for a packaging structure applied to a planar power device, and belongs to the field of semiconductor packaging technology. It adopts the metal bump under the chip on the front of the chip to be flipped onto the etched surface of the three-dimensional metal frame, and realizes direct interconnection between the chip and the PCB through the folding of the metal bump under the chip and the three-dimensional metal frame, which simplifies the packaging structure, avoids the traditional wire bonding process, reduces the packaging resistance, and increases the current carrying capacity; at the same time, it shortens the interconnection distance between the chip and the outside world, and enhances the conductive effect of the chip. It provides a single-sided precise plastic sealing and low-temperature bonding protective film process, simplifies the packaging process, and compared with the traditional wire bonding method, the FC process transmission performance is improved, the interconnection structure size is short, the inductance, resistance and capacitance are reduced, the signal integrity, the radio frequency performance is better, the production efficiency is improved and the production cost is reduced.
Description
Technical Field
The invention relates to a packaging method of a packaging structure applied to a planar power device, and belongs to the technical field of semiconductor packaging.
Background
With the development of the 5G industry, consumer electronics and new energy automobile industry, for example, the power consumption of the 5G base station is improved, the power consumption of the 5G base station is doubled as that of the 4G base station, in order to reduce the power consumption requirement, the requirements on low loss and high thermal stability of the chip are required to be increased, and meanwhile, the requirements on low on-resistance, low heat productivity and fast heat dissipation of the packaging type are also higher.
The traditional bonding wire type packaging adopts a wire bonding packaging mode, and the bonding wire resistance R w is larger, so that the on-resistance of the whole packaging can be increased, and the current bearing capacity of a product is finally affected.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a packaging method of a packaging structure applied to a planar power device, so that a chip adopting the packaging mode realizes low on-resistance, high load-bearing current, excellent heat dissipation performance and simple packaging structure.
The technical scheme of the invention is as follows:
the invention provides a packaging method of a packaging structure applied to a planar power device, which comprises the following steps:
firstly, preparing an incoming wafer, wherein the wafer is provided with a cutting channel I which is orderly arranged and transversely and longitudinally crossed, the cutting channel I pre-divides the wafer into a plurality of chips, the front surface of each chip is provided with a plurality of under-chip metal bumps, the back surface of each chip is provided with a heat dissipation layer, and one end of each under-chip metal bump is provided with a welding layer I corresponding to an electrode of the chip and the other end of each under-chip metal bump;
Cutting the wafer along the cutting path I by adopting a cutting process to form a plurality of independent chips;
Preparing a metal original plate, wherein the metal original plate is preferably made of metal copper with excellent conductivity and comprises a metal surface I on the upper surface and a metal surface II on the lower surface, and the metal surface II forms a welding layer II through an electroplating process;
Fourthly, the back surfaces of the chips are fixedly connected with the metal surface I of the metal original plate through silver paste in sequence, the chips are arranged in an array, the chips are spaced apart from each other, and a cutting channel II is reserved on the metal original plate;
step five, cutting the metal original plate along the cutting path II to form a new chip monomer, wherein the metal original plate forms a metal radiating fin on the back of the chip;
Step six, preparing a three-dimensional metal frame strip, wherein an etching surface on the back surface of the three-dimensional metal frame strip is used as a working surface, the back surface of the three-dimensional metal frame strip is etched through a half etching process, redundant metal materials are removed, a plurality of hollowed-out patterns I, hollowed-out patterns II and opposite sites are arrayed on the back surface of the three-dimensional metal frame strip, an etching surface is formed, transverse cutting channels III and longitudinal cutting channels III are designed, opposite sites are arranged on the upper side, the lower side, the left side and the right side of the three-dimensional metal frame strip, the hollowed-out patterns I and the hollowed-out patterns II are distributed in the center of the three-dimensional metal frame strip in a parallel and staggered mode, the hollowed-out patterns I and the hollowed-out patterns II are all rectangular with equal length, and the width of the hollowed-out patterns I is larger than the width of the hollowed-out patterns II; the three-dimensional metal frame strip is divided into a plurality of block-shaped metal frame bodies by the hollowed-out pattern I, the metal frame body is further divided into a plurality of strip-shaped metal frame support strips by the hollowed-out pattern II in parallel with the hollowed-out pattern I, and the metal frame body is divided into a plurality of metal frame support strips by the hollowed-out pattern II;
Metal pins are formed on two ends of the etching surface of the metal frame support bar and are positioned on the inner sides of long sides of the hollowed-out patterns I and II;
The longitudinal cutting channel III is parallel to the length direction of the hollowed-out pattern I, the transverse cutting channel III is arranged on the upper side edge and the lower side edge of the three-dimensional metal frame strip, penetrates through the upper end and the lower end of the hollowed-out pattern I and the hollowed-out pattern II, and pre-cuts the metal frame support strips from the three-dimensional metal frame strip one by one;
the etched surface of the metal frame support bar and the metal pins on the etched surface together form a cavity;
Step seven, sequentially placing the front face of the new chip monomer into a cavity of the three-dimensional metal frame strip in a flip-chip manner, and aligning the chip lower metal lug of the new chip monomer through an alignment point, wherein the chip lower metal lug is correspondingly and fixedly connected with the metal frame support strip through a welding layer I, so that the circuit conduction of the chip is realized;
step eight, filling gaps between the three-dimensional metal frame strips and the new chip monomers by pressure after melting the plastic packaging material through a film-assisted plastic packaging single-sided molding process, filling the hollowed-out patterns I and II, and accurately exposing the welding layer II on the back of the new chip monomers and the upper surfaces of the metal pins; the hollowed-out pattern I and the hollowed-out pattern II play a role in guiding the plastic package material to form a guiding channel;
Step nine, attaching a protective film with back adhesive on the flat front surface of the three-dimensional metal frame strip through a lamination process;
step ten, manufacturing a conductive metal layer on the upper surface of the metal pin in sequence through sputtering corrosion, chemical deposition, printing or spraying;
And eleven, dividing the packaging body into packaging structure monomers of a plurality of chips along the transverse cutting channel III and the longitudinal cutting channel III, and upwardly turning the chips to be directly interconnected with the back surface of the chips and the PCB through the lower chip metal bumps and the three-dimensional metal frame of the chips and radiating heat.
Further, in the third step, the forming process of the metal pin is as follows:
Symmetrical metal posts are formed on the two ends of the etching surface of the metal frame support bar in a sputtering, etching, chemical deposition, printing or spraying mode to serve as metal pins.
Further, in the third step, the forming process of the metal pin is as follows:
Forming a plurality of metal columns with the same height through photoresist patterns and a metal deposition method, and respectively connecting the bottoms of the metal columns to the etching surfaces of the metal frame support bars through a welding process to form metal pins.
Further, in the third step, the forming process of the metal pin is as follows:
Preparing a metal sheet, forming a plurality of metal columns with the same height by adopting a high-reflection laser through a laser cutting process, and connecting the bottoms of the metal columns to the etching surfaces of the metal frame support bars through a welding process to form metal pins.
Further, in the third step, the forming process of the metal pin is as follows:
when the three-dimensional metal frame strip is formed, the back of the three-dimensional metal frame strip is etched through a half etching process, redundant metal materials are removed, a plurality of hollowed-out patterns I, hollowed-out patterns II, opposite sites and metal pins are arrayed on the back of the three-dimensional metal frame strip, a transverse cutting channel III and a longitudinal cutting channel III are designed, the cylindrical surfaces of the metal pins are in a concave arc column shape due to the difference of etching speeds, the radian R of the concave arc column shape is controlled by an actual process, and the metal pins and the metal frame support bar are of an integrated structure.
Further, the surface of the metal pin or the surface of the metal pin and the etched surface of the three-dimensional metal frame strip are roughened together by a plasma etching process, and the control range of the roughness Ra is as follows: ra is 0.2 to 0.4.
Further, the welding layer I is one metal or a combination of several metals of titanium, copper, silver, nickel, gold, tin and tin-silver.
Further, the cross-sectional dimension of the metal heat sink is not smaller than the cross-sectional dimension of the chip.
Further, the cross section of the metal pin is round, rectangular or hexagonal.
Further, in step ten, the welding layer II and the conductive metal layer are formed simultaneously.
Advantageous effects
The packaging method of the packaging structure applied to the planar power device provides a process of single-sided accurate plastic packaging and low-temperature laminating of the protective film, simplifies the packaging process, improves the transmission performance of the FC process, shortens the size of the interconnection structure, reduces inductance, resistance and capacitance, has better signal integrity and radio frequency performance, improves the production efficiency and reduces the production cost compared with the traditional routing mode; the traditional wire bonding mode is avoided, the resistance R D between the chip and the lead frame is reduced, and the bonding wire resistance R W is reduced, so that the aim of reducing the on-resistance RDS (on) of the packaged product is fulfilled; the formed packaging structure applied to the planar power device adopts the structure that the chip lower metal lug on the front surface of the chip is inverted to the etching surface of the three-dimensional metal frame, and the chip and the PCB are directly interconnected through the folding of the chip lower metal lug and the three-dimensional metal frame, so that the packaging structure is reduced, the traditional wire bonding process is avoided, the packaging resistance is reduced, and the current carrying capacity is increased; meanwhile, the interconnection distance between the chip and the outside is shortened, and the conductive effect of the chip is enhanced; the back of the chip is exposed, and heat is dissipated through the close connection of the metal radiating fins and the PCB, so that the packaging heat dissipation capacity is improved, the stability of the chip in high-speed operation is improved, and the quality of products is improved; in addition, the metal pins of the three-dimensional metal frame are in a concave arc column shape, so that the binding force between the metal pins and the plastic packaging material is enhanced, and the purpose of increasing the reliability of the product is achieved.
Drawings
Fig. 1 is a flow chart of a packaging method of a packaging structure applied to a planar power device;
fig. 2 is a schematic diagram illustrating an embodiment of a cross-sectional structure of a package structure applied to a planar power device according to the present invention;
Fig. 3 is a schematic diagram illustrating an embodiment of a cross-sectional structure of a package structure applied to a planar power device according to the present invention;
FIG. 4 is a schematic view of the relative positions of the chip and the solid metal frame of FIG. 2;
fig. 5 is a schematic diagram illustrating a cross-sectional structure of an embodiment of a package structure applied to a planar power device according to the present invention;
fig. 6A to 6Q are flowcharts of a process of a packaging method applied to a packaging structure of a planar power device according to the present invention;
Wherein: chip 10
Weld layer I12
Weld layer II 55
Conductive circuit layer 30
Three-dimensional metal frame 20
Metal frame support bar 21
Cavity 26
Metal heat sink 50
Cutting path II 57
Conductive metal layer 61
A molding material 90;
Wafer 100
Cutting lane I110
Three-dimensional metal frame strip 200
Transverse cutting lane III 210
Longitudinal cutting lane III 230
Alignment site 250
The metal conductive heat sink plate 400.
Detailed Description
The application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be noted that, for convenience of description, only the portions related to the present application are shown in the drawings.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
The invention relates to a flow chart of a packaging method applied to a packaging structure of a planar power device, which is shown in fig. 1:
step S1: preparing an incoming wafer;
step S2: cutting the wafer into a plurality of independent chips by adopting a cutting process;
step S3: preparing a metal original plate;
step S4: the back of the chip is fixedly connected with a metal original plate through silver paste in sequence;
step S5: cutting the metal original plate to form a new chip monomer;
step S6: preparing a three-dimensional metal frame strip, forming a metal frame support strip through a half etching process, and forming metal pins at two ends of an etching surface of the metal frame support strip to form a cavity;
Step S7: sequentially inversely placing the front surface of a new chip monomer into a cavity of the three-dimensional metal frame strip;
step S8: plastic packaging the three-dimensional metal frame strip and the new chip monomer through a film auxiliary plastic packaging single-sided molding process;
step S9: laminating a protective film on the front surface of the three-dimensional metal frame strip through a lamination process;
step S10: manufacturing a conductive metal layer on the upper surface of the metal pin by sputtering corrosion, chemical deposition, printing or spraying in sequence;
step S11: the package is divided into a plurality of package structure units.
Examples are as follows:
The invention relates to a packaging structure applied to a planar power device, as shown in fig. 2 to 5, the front surface of a chip 10 is provided with a plurality of under-chip metal bumps 11, one end of each under-chip metal bump 11 is connected with an electrode (the electrode is not shown in the figure) of the chip 10, and the electrode of the chip 10 is buried in a silicon substrate 13 under a passivation layer on the surface of the chip; the other end of the under-chip metal bump 11 is provided with a solder layer I12, which becomes the I/O terminal of the chip 10.
One surface of the metal heat sink 50 is a metal surface I51, and the other surface is a metal surface II 52, and the back surface of the chip 10 is fixedly connected with the metal surface I51 of the metal heat sink 50 through silver paste 53 to form a new chip unit 30. The metal surface II 52 is formed into a welding layer II 55 by an electroplating process.
The cross section size of the metal radiating fin 50 is not smaller than the cross section size of the chip 10, the material of the metal radiating fin 50 is preferably metal copper with excellent electric conduction performance, the metal radiating fin 50 is arranged on the back surface of the chip 10, the chip 10 and the PCB are closely connected to radiate heat, the packaging heat radiation capacity is improved, the quality of a product is improved, and the excellent heat radiation performance of the packaged product is realized.
The three-dimensional metal frame 20 comprises a plurality of metal frame supporting bars 21 and a plurality of metal pins 22. The back surfaces of the metal frame support bars 21 are etched surfaces, and the metal pins 22 are disposed at both ends of the etched surface of each metal frame support bar 21. The cross section of the metal pins 22 is circular, rectangular, hexagonal, etc., and is illustrated in fig. 3 as a rectangular cross section of the metal pins 22. The etched surface of the metal frame support bar 21 and the inner sides of the metal pins 22 form a cavity 26.
The front surface of the new chip unit 30 is flip-chip mounted in the cavity 26 through the welding layer I12 of the chip 10, and the under-chip metal bump 11 is fixedly connected with the etching surface of the metal frame support bar 21 through the welding layer I12 and is electrically connected with the three-dimensional metal frame 20. The etched surface of the metal frame support bar 21 is a roughened surface, and the roughness thereof contributes to the strength of the connection with the chip 10.
In an alternative embodiment, the metal pins 22 and the metal frame support bar 21 are of unitary construction, as shown in fig. 2.
The chip 10 and the PCB are directly interconnected through the deflection of the lower metal lug 11 and the three-dimensional metal frame 20, the chip 10 is efficiently radiated through the metal radiating fins 50 and the PCB, the interconnection distance between the chip 10 and the outside is shortened, the conductive effect of the chip is enhanced, the traditional wire bonding mode is avoided, the resistance R D between the drain electrode of the chip and the lead frame is reduced, and the bonding wire resistance R W is reduced, so that the aim of reducing the on-resistance RDS (on) of a packaged product is fulfilled.
The front surface of the three-dimensional metal frame 20 is a flat exposed surface, and a protective film 40 with back adhesive, such as Adwill LC adhesive tape, is arranged. The protective film 40 is uniform in thickness, is attached to the front surface of the three-dimensional metal frame 20 by a lamination process, can be performed at a relatively low temperature, and is convenient to install, thereby reducing the risk of damaging a circuit due to heat. It can protect the chip from external solvents, moisture, impact, etc., and electrically insulate the chip from the external environment. It also blocks light and minimizes the effect of light on the circuit surface.
The plastic package material 90 is used for integrally filling and plastic packaging the three-dimensional metal frame 20 and the chip 10, only the metal cooling fins 50 and the etched surfaces 221 of the metal pins are exposed, and the plastic package material 90 arranged between the chip 10 and the metal cooling fins 50 and the metal pins 22 can effectively prevent short circuits caused by voltage breakdown, so that the reliability of products is improved.
In an alternative embodiment, the metal pins 22 are in a concave arc shape, and the radian R is generated due to the difference of etching rates in the half etching process of the three-dimensional metal frame 20, as shown in fig. 4, by controlling the half etching process to obtain the actually required radian R, the bonding force between the metal pins 22 and the plastic package material 90 can be increased, so as to achieve the purpose of increasing the reliability of the product.
In an alternative embodiment, the cylindrical surface of the metal pin 22 may also be roughened, with a roughness Ra in the range of: ra is 0.2-0.4, and the bonding force between the metal pins 22 and the plastic package material 90 can be increased, so that the purpose of increasing the reliability of the product is achieved.
In an alternative embodiment, the plastic sealing material 90 may be exposed on both sides of the metal frame support bar 21 as shown in fig. 5.
In an alternative embodiment, the novel package structure applied to the planar power device of the present invention further includes a conductive metal layer 26, where the conductive metal layer 26 is disposed on the etched surface 221 of the metal pin, so as to be convenient for electrically connecting and dissipating heat with other external devices.
The invention relates to a packaging method of a packaging structure applied to a planar power device, as shown in fig. 6A to 6Q, which comprises the following steps:
step one, as shown in fig. 6A and 6B, a wafer 100 is prepared, a qualified wafer is picked by an incoming material inspection process, dust, oil dirt and the like are removed by a cleaning process, a cutting path i 110 which is orderly arranged and transversely and longitudinally crossed is arranged on the wafer 100, the wafer 100 is pre-divided into a plurality of chips 10 by the cutting path i 110, a plurality of under-chip metal bumps 11 are arranged on the front surface of each chip 10, the under-chip metal bumps 11 correspond to electrodes (not shown in the drawings) of the chips 10, the electrodes of the chips 10 are buried in a silicon substrate 13 under a passivation layer on the surface of the chips, one end of each under-chip metal bump 11 corresponds to the electrodes of the chips 10, and the other end of each under-chip metal bump 11 is provided with a welding layer i 12.
Step two, as shown in fig. 6C and fig. 6D, a dicing process is used to dice the wafer 100 along dicing streets i 110 to form a plurality of individual chips 10, and fig. 6D is a front view of the chips, and the under-chip metal bumps 11 are shown as 3*5 arrays.
Step three, as shown in fig. 6E and 6F, a metal original plate 500 is prepared, which is preferably made of metallic copper with excellent conductivity, and includes a metallic surface i 51 on the upper surface and a metallic surface ii 52 on the lower surface, wherein the metallic surface ii 52 forms a solder layer ii 55 by electroplating, the solder used in the solder layer ii 55 may be one metal or a combination of several metals of titanium, copper, silver, nickel, gold, tin and tin silver, and the solder layer ii 55 covers the metallic surface ii 52 to prevent oxidation of the metal.
Step four, as shown in fig. 6G, the back surface of the chip 10 is fixedly connected with the metal surface i 51 of the metal original plate 500 sequentially through silver paste 53, the chips 10 are arranged in an array, the chips are spaced apart from each other, and a cutting channel ii 57 is left on the metal original plate 500;
step five, as shown in fig. 6H, the metal plate 500 is cut along the scribe line ii 57 to form a new chip unit 30, and the metal plate 500 forms the metal heat sink 50 on the back of the chip 10;
Step six, as shown in fig. 6I, 6J and 6K, a three-dimensional metal frame bar 200 is prepared, and the material selection of the three-dimensional metal frame bar 200 refers to the lead frame of the chip carrier for the integrated circuit, and the etched surface of the back surface is used as the working surface. Fig. 6I is a top view of the back surface of the stereoscopic metal frame strip 200, fig. 6J and 6K are cross-sectional views B-B of fig. 6I, and the stereoscopic metal frame strip 200 etches the back surface of the stereoscopic metal frame strip 200 through a half etching process to remove the redundant metal material, and a plurality of hollowed-out patterns I221 and ii 222 and alignment points 250 are arranged on the back surface of the stereoscopic metal frame strip 200 in an array manner to form an etched surface, and a transverse scribe line iii 210 and a longitudinal scribe line iii 230 are designed. The opposite points 250 are arranged on the four sides of the three-dimensional metal frame strip 200, the hollowed-out patterns I221 and II 222 are distributed in the center of the three-dimensional metal frame strip 200 in a parallel and staggered mode, the hollowed-out patterns I221 and II 222 are rectangular with equal length, and the width of the hollowed-out patterns I221 is larger than that of the hollowed-out patterns II 222. The hollow pattern I221 divides the three-dimensional metal frame bar 200 into a plurality of block-shaped metal frame bodies, the hollow pattern ii 222 is parallel to the hollow pattern I221 to further divide the metal frame body into a plurality of bar-shaped metal frame support bars 21, in fig. 6I, four hollow patterns ii 222 are arranged between adjacent hollow patterns I221 to illustrate, and the hollow patterns ii 222 divide the metal frame body into five metal frame support bars 21. Symmetrical metal posts are formed on the two ends of the etched surface of the metal frame support bar 21 in sequence through sputtering, corrosion, chemical deposition, printing or spraying to serve as metal pins 22, and the metal pins 22 are located on the inner sides of the long sides of the hollowed-out patterns I221 and II 222 so as to avoid the transverse cutting channel III 210, so that the metal pins 22 are not damaged.
The longitudinal cutting channel III 230 cuts the hollowed pattern I221 in parallel with the length direction of the hollowed pattern I221, and in general, the longitudinal cutting channel III 230 coincides with the central line of the hollowed pattern I221; for the outermost hollowed-out pattern I221, the longitudinal cutting channel III 230 cuts out a part of the hollowed-out pattern I221 along the length direction of the hollowed-out pattern I221.
The transverse cutting channels III 210 are arranged on the upper side and the lower side of the three-dimensional metal frame strip 200, penetrate through the upper end and the lower end of the hollowed-out patterns I221 and the hollowed-out patterns II 222, and pre-cut the metal frame support strips 21 one by one from the three-dimensional metal frame strip 200.
The etched surfaces of the five metal frame support bars 21 and the metal pins 22 thereon together form a cavity 26, as shown in fig. 6J;
or when the three-dimensional metal frame strip 200 is formed, the redundant metal materials are removed from the raw material of the three-dimensional metal frame strip 200 through a half etching process, a plurality of hollowed patterns I221 and II 222 which are arranged in an array manner, a position aligning point 250 and a metal pin 22 are formed on an etching surface, a transverse cutting channel III 210 and a longitudinal cutting channel III 230 are designed, the cylindrical surface of the metal pin 22 is in a concave arc column shape due to different etching speeds, the radian R of the concave arc column is controlled by an actual process, the metal pin 22 and the metal frame support bar 21 are in an integrated structure, and the five metal frame support bars 21 and the metal pins 22 on the metal frame support bar form a cavity 26 together, as shown in fig. 6K.
Or forming a plurality of metal columns with the same height by a photoresist pattern and a metal deposition method, respectively connecting the bottoms of the metal columns to the etching surface of the metal frame support bar 21 by a welding process to form metal pins 22, wherein the welding solder can be one metal or a combination of several metals of titanium, copper, silver, nickel, gold, tin and tin silver.
Or preparing a metal sheet, forming a plurality of metal columns with the same height by adopting a high-reflection laser through a laser cutting process, connecting the bottoms of the metal columns to the etching surface of the metal frame support bar 21 through a welding process to form metal pins 22, wherein the welding flux can be one or a combination of a plurality of titanium, copper, silver, nickel, gold, tin and tin silver.
In this step, the surface of the metal lead 22 or the surface of the metal lead 22 and the etched surface of the three-dimensional metal frame bar 200 may be roughened by a plasma etching process, and the roughness Ra is controlled in the following range: ra is 0.2 to 0.4.
Step seven, as shown in fig. 6L and 6M, the front face of the new chip unit 30 is placed in the cavity 26 of the three-dimensional metal frame strip 200 in a flip-chip manner, and the under-chip metal bump 11 is correspondingly and fixedly connected with the metal frame support bar 21 through the welding layer i 12 by aligning the alignment point 250, so as to realize the circuit conduction of the chip 10, wherein the welding material used in the welding layer i 12 can be one metal or a combination of several metals of titanium, copper, silver, nickel, gold, tin and tin silver. Fig. 6L is a schematic diagram illustrating the relative positions of the three-dimensional metal frame strip 200 and the chip 10, and fig. 6M is a cross-sectional view of fig. 6L.
Step eight, as shown in fig. 6N, after the plastic packaging material 90 is melted by a film-assisted plastic packaging single-sided molding process (FAM), the gap between the three-dimensional metal frame strip 200 and the new chip unit 30 is filled by pressure, and the hollowed-out pattern i 221 and the hollowed-out pattern ii 222 are filled, and simultaneously, the welding layer ii 55 on the back surface of the new chip unit 30 and the upper surface 221 of the metal pin are accurately exposed. The hollowed-out pattern I221 and the hollowed-out pattern II 222 play a role in guiding the plastic package material 90 to form a guiding channel.
Step nine, as shown in fig. 6O, the protective film 70 with the back adhesive, such as Adwill LC adhesive tape, is attached to the flat front surface of the three-dimensional metal frame strip 200 by a lamination process at a relatively low temperature, so that the installation is convenient, the risk of damaging the circuit due to heat is reduced, and the conventional EMC process is simplified.
Step ten, as shown in fig. 6P, a conductive metal layer 61 is sequentially manufactured on the upper surface 221 of the metal pin by means of sputter etching, chemical deposition, printing or spraying, and the conductive metal layer 61 is used for subsequent mounting and application of the packaged chip. Solder layer ii 55 may also be formed at the same time as conductive metal layer 61. Typically, it is required that solder layer II 55 and conductive metal layer 61 be flush.
Step eleven, as shown in fig. 6Q, the package is divided into a plurality of package structure units along the transverse dicing channels iii 210 and the longitudinal dicing channels iii 230, the chip 10 is folded upwards to be directly connected with the back surface of the chip 10 and the PCB in a telecommunication manner through the under-chip metal bump 11 and the three-dimensional metal frame 20, and the chip 10 is directly and efficiently cooled through the metal heat sink 50 and the PCB.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the technical scope of the present invention disclosed in the embodiments of the present invention should be covered by the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (10)
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