CN1152288C - Medium-high frequency short delay clock pulse width adjusting circuit - Google Patents

Abstract

The invention relates to a middle-high frequency short delay clock pulse width adjusting circuit, which is provided with a hysteresis comparator and also comprises: the hysteresis comparator is used for comparing the sine wave signal input at one end with the threshold voltage input at the other end and outputting a clock signal; a detection circuit for detecting whether a wobble signal appears in the input clock signal; and a correction circuit for correcting the threshold voltage input by the hysteresis comparator according to the fluctuation signal detected by the detection circuit. The circuit can process clock signals below 400MHz, has the advantages of no abrupt change of duty ratio, strong adaptive capacity and suitability for the manufacturing process of submicron integrated circuits.

Description

Medium and high frequency short delay clock pulse width adjustment circuit

The invention relates to a delay clock pulse width adjustment circuit, in particular to a medium-high frequency short delay clock pulse width adjustment circuit composed of a hysteresis comparator and a clock signal duty cycle to DC level converter.

In modern signal processing systems, clock signals are indispensable. Due to the rapid development of communication and other technical fields, the requirements for clock signals are getting higher and higher, which are mainly reflected in the following aspects: (1) The frequency of clock signals Accuracy, in this aspect, is mainly solved by crystal oscillators and atomic clocks; (2) The long-term stability of the clock signal, within a year or longer, the error of the clock signal is in the range of one second or less Internally, this aspect is determined by the stability of the clock source; (3) The duty cycle stability of the clock signal, due to sudden external changes and other reasons, the duty cycle of the clock has a large shift, which can lead to resulting in a higher bit error rate. In the analog-to-digital converter, since the conversion rate (SAMPLE RATE) in the sample/hold circuit is a value determined in the design, the change of the duty cycle will shorten the charging time of the capacitor and cannot achieve the specified conversion accuracy.

Figure 1 is a simple schematic diagram of an existing high-precision clock generator. In Fig. 1, the change of the clock duty cycle mainly comes from two parts of system error and random error. System errors include: changes in crystal oscillator output signal amplitude, harmonics due to loads, changes in DC trigger levels, and temperature drift. The random error mainly comes from: the deviation of the DC component in the sinusoidal output of the crystal oscillator, the random deviation of the input stage of the comparator, and the deviation of the DC trigger level.

In order to simplify the analysis process, all the errors are transformed to the sinusoidal signal output stage of the crystal oscillator, and it is assumed that the deviation of the signal is small, that is, when analyzing the influence of the error on the duty cycle, according to the sine wave equation, the trigger edge occurs The time is:

ΔV＝Vsin(2πf*Δt)         (1)

Among them, V represents the amplitude of the sine wave, f represents the frequency, ΔV represents the change of the DC component in the sine wave, assuming: V>> ΔV, according to the approximate equation of the sine function, from the above formula (1), the occurrence of the trigger edge can be obtained The time variation approximate formula is:

Δt＝ΔV/V*2πf (2)

Since the same time change occurs on both the rising trigger edge and the falling trigger edge, according to formula (2), the change in duty cycle can be expressed as:

ΔD＝ΔV/πV (3)

From the above formula (3), the signal shown in Figure 2 can be obtained.

In Fig. 2, the ideal clock signal, if duty=t2/(t1+t2), its DC level coincides with the sinusoidal DC component. For an actual clock signal, the DC trigger level does not coincide with the sinusoidal DC component, as shown by the dotted line in Figure 2. At this time, the change of the DC component in the sine wave output by the crystal oscillator is negative, that is, the polarity of the change component is uncertain.

The object of the present invention is to provide a medium-high frequency short-delay clock pulse setting adjustment circuit capable of processing clock signals below a specified frequency and having self-adaptive capability, so that the duty cycle of the clock signal does not have a large mutation and reduces the burden on digital signal processing. Pressure, even when the clock signal duty ratio varies relative to the set value, it can be corrected within 1 to 2 clocks, and makes the adjustment circuit suitable for sub-micron integrated circuit manufacturing processes to reduce random errors in the chip manufacturing process Therefore, it can meet the requirements of high information content, low bit error rate, and high stability of the duty cycle of the clock signal in the application of digital-analog hybrid integrated circuit chips in modern communication systems.

In order to achieve the above object, the circuit of the present invention includes: a hysteresis comparator, which is used to compare the sine wave signal input by one input terminal with the threshold voltage input by the other input terminal, and output a clock signal with a prescribed duty cycle; a detection circuit for detecting whether a fluctuating signal appears in the clock signal output by the input hysteresis comparator; and a correction circuit for correcting the clock signal according to the fluctuating signal detected by the detection circuit A clock signal is converted to the threshold voltage at the input of the hysteretic comparator.

According to the medium-high frequency short-delay clock pulse width adjustment circuit of the present invention, the duty cycle of the clock signal can be set to a certain value, and any change that deviates from this set value, including slow changes and sharp mutations, can be It is detected and corrected immediately, and the correction period is 1 to 2 clock signal periods.

The duty ratio detection circuit of the present invention adopts two structures, and for the bottleneck problem of the fast response channel in the integrated circuit, one of the implementations adopts the method of equal constant current source for correction.

In the circuit of the present invention, the output of the clock signal is directly used in the duty cycle detection circuit, which eliminates the influence of the offset on the clock signal duty cycle caused by the matching of devices in integrated circuit manufacturing.

Although the adjustment circuit of the duty ratio of the clock signal in the present invention is aimed at the sudden change of fast response, the circuit can also adjust and compensate for the change of the duty ratio of the clock signal caused by the low-speed deviation.

In a word, the medium-high frequency short-delay clock pulse width adjustment circuit of the present invention can handle the clock signal below 400MHz frequency, has the advantages of no large mutation in the duty ratio of the clock signal, strong self-adaptive ability, and is suitable for the advantages of submicron integrated circuit manufacturing process, Therefore, it can meet the high requirements of modern communication for high information content, low bit error rate, and the stability of the duty ratio of the clock signal in the digital-analog hybrid system.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein:

Fig. 1 shows the schematic diagram of the clock signal generator;

Fig. 2 represents the output signal comparison chart of ideal clock signal generator and actual clock signal generator;

Fig. 3 represents the block diagram of clock signal duty ratio adjustment circuit;

Fig. 4 shows the schematic diagram of immunity to level deviation of the circuit of the embodiment of the present invention;

Fig. 5 shows the schematic diagram (MOS) of the clock signal duty cycle detection and correction circuit of embodiment 1;

Fig. 6 shows the schematic diagram (bipolar) of the clock signal duty cycle detection and correction circuit of embodiment 2;

FIG. 7 shows a specific structural diagram of a clock signal duty cycle detection and correction circuit in Embodiment 1 of the present invention;

Figure 8 is a schematic diagram of a clock signal duty cycle detection and correction circuit that eliminates the influence of parasitic capacitance;

FIG. 9 shows a specific structural diagram of a clock signal duty ratio detection and correction circuit according to Embodiment 2 of the present invention;

FIG. 10 shows a schematic diagram of a fast adjustment process of the clock signal duty cycle.

First, referring to FIG. 3 , a block diagram of the basic structure of the clock signal duty ratio adjustment circuit of the present invention will be described. The adjustment circuit is composed of a hysteresis comparator module and a clock signal duty ratio detection and correction circuit module. VCC and gnd are power supply and ground respectively, VinP is the sine wave input of the oscillator, Vout is the clock signal output, Vref is the reference level input, Vbiasl, Vbias2 and Vbias3 are three bias voltage inputs. The power supply VCC and the ground gnd are respectively connected with the power terminal and the ground terminal of the hysteresis comparator and the detection and correction circuit. The bias voltage Vbias1 is connected to the reference level input terminal Vref of the hysteresis comparator. The reference voltage Vref, the bias voltages Vbias2 and Vbias3 are respectively connected to corresponding terminals of the detection and correction circuit. The output of the sine wave is connected to the P terminal of the hysteresis comparator, the output terminal of the detection and correction circuit is connected to the N terminal of the hysteresis comparator, and the output terminal of the hysteresis comparator is connected to the input terminal of the detection and correction circuit.

The output of the sine wave is connected to the input terminal P of the hysteresis comparator. When the input voltage of the input terminal P is greater than the input voltage of its input terminal N, the output of the hysteresis comparator is 1; otherwise, the output of the hysteresis comparator is 0. At the same time, since the output of the clock signal is connected to the input terminal of the detection and correction circuit, and the output terminal of the detection and correction circuit is connected to the input terminal N of the hysteresis comparator, the circuit has an adaptive function.

When the output is stable, the output of the detection and correction circuit is the set value, and the duty cycle of the clock signal is within the specified range. When for some reason, the duty cycle of the output signal of the hysteresis comparator increases, the output of the detection circuit will also increase, thereby changing the threshold voltage of the hysteresis comparator. At the output of the hysteresis comparator, the duty cycle of the clock signal The void ratio changes accordingly. Take the increase of the duty cycle of the clock signal as an example, at this time, the output of the detection circuit will rise (see Figure 10 below), and the duty cycle of the clock signal will fall back.

In addition, the clock signal duty ratio adjustment circuit of the above embodiments of the present invention can be applied in a digital CMOS process, and better meet the requirement for clock signal duty ratio adjustment in a digital-analog hybrid system.

In the following, this embodiment will be described, which has an immune function against DC offset voltage caused by device mismatch and the like. For this reason, the adjustment circuit is further simplified as schematic diagram 4.

In Figure 4 shown, all circuits are considered to have no voltage deviation, and all factors that may produce deviation voltage are represented by Vos. Vsin is a sine wave input including a DC component, and Vth is the threshold voltage of the hysteresis comparator , which is the output of the pulse duty ratio detection and correction circuit, whose input is the shaped clock signal.

When Vos is positive, at the signal input port of the hysteresis comparator, the signal will move up, resulting in an increase in the duty cycle of the output clock signal; after the clock signal with increased duty cycle is input into the detection and correction circuit, so that Vth rises. In the stable working state of the circuit, the increased value of Vth is offset by Vos, so the system has the function of self-adaptive elimination of the random errors introduced by the manufacturing process in the circuit, and is immune to the deviation of the level.

Set the transfer function of the duty cycle detection and correction circuit as:

H(D)＝Vdc+K*ΔV

In the above formula, Vdc is the DC component, and K is the gain of the correction circuit.

Set the duty cycle transfer function of the hysteretic comparator as:

Δduty=F(V)*ΔV

In the above formula, it is assumed that the response of the hysteresis comparator to the duty cycle is linear, and F(V) is the duty cycle coefficient when the level is constant.

The change in duty cycle due to the introduction of offset voltage is:

Δduty=F(V)*Vos

The hysteretic comparator threshold voltage change due to the offset voltage is:

Vth＝Vdc+K*Δduty＝Vdc+F(V)*Vos (4)

Removing the influence of the DC component from formula (4), and only considering the response of the offset voltage, four situations can be obtained, namely:

1. K*F(V)=1

The duty cycle variation caused by the offset voltage is completely eliminated;

2. K*F(V)<1

The offset voltage will still cause a change in the duty cycle of the clock signal, but the change will be reduced;

3. 1<K*F(V)<2

The offset voltage causes a change in the duty cycle of the clock signal, the change is reduced and the polarity is reversed;

4. K*F(V)>2

The offset voltage causes a change in the duty cycle of the clock signal, which is increasing and opposite in polarity.

It can be seen that, except for the above (4), the adjustment circuit composed of the detection and correction circuit of the present invention can completely eliminate the change of the duty ratio caused by the offset voltage.

Example 1

FIG. 5 is a schematic diagram of a clock signal duty ratio detection and correction circuit integrated with MOS transistors in Embodiment 1. FIG. In FIG. 5 , Vin is the clock signal input, and Vout is the output of the duty cycle detection and correction circuit, which is used as the threshold voltage of the hysteresis comparator.

The detection circuit includes: a current switch, a first bias circuit, a first current mirror circuit, a second current mirror circuit and a third current mirror circuit. The first bias circuit M6' outputs a bias current I1. The first current mirror circuit is composed of M27' and M26', the second current mirror circuit is composed of M10' and M9', and the third current mirror circuit is composed of M28' and M29', and the output currents are I2 and I7, I3 and I4, I5 and I6. The input terminals of the first current mirror circuit and the second current mirror circuit of the detection circuit are connected to the power supply, and their respective output terminals are respectively connected to an input terminal of the current switch, and the other output terminal of the first current mirror circuit is connected to the power supply. The gate of the MOS transistor M30' is connected to one end of the capacitor C as a current-to-voltage converter, and the other output end of the second current mirror circuit is connected to an input end of the third current mirror circuit. The other input end of the third current mirror circuit is connected to one end of the capacitor C. In addition, the input terminal of the first bias circuit is connected to the common output terminal of the current switch. The output terminal of the third current mirror circuit, the output terminal of the first bias circuit and the other end of the capacitor C are grounded.

The correction circuit part has a current-to-voltage conversion circuit and a comparison circuit. Specifically, the composition includes: a second bias circuit M24', a third bias circuit M33', a fourth current mirror circuit, a MOS transistor M30', and resistors R1 and R2 and capacitance C. This 4th current mirror circuit is made up of M31 ' and M322, and output current is I8 and I9 respectively, and its input end connects power supply, and its output end connects the drain of MOS transistor M30 ', and another output end connects the second The input terminal of the bias circuit M332 and the node of the third bias circuit and the resistor R2 are the Vout of the PWM filter. The source of the MOS transistor M30' is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded. The current-to-voltage converter has a circuit composed of a MOS transistor M30' and a capacitor C. According to the voltage level on the capacitor C, the gate of M30' is controlled to determine the magnitude of its conduction current.

The clock signal is input from Vin to the current switch to control the flow of the current I1 of the current switch. When Vin=1, I2=I1, I3=0; when Vin=0, I2=0, I3=I1. Taking x=y=1 as an example, the duty cycle of the clock signal at this time is 50%. When for some reason, the duty cycle of the clock signal increases, the time for I1 of the first bias circuit to connect to I2 and I7 of the first current mirror circuit will be longer than the time to connect to I3 and I4 of the second current mirror circuit time, therefore, in each clock cycle, the charge injected into capacitor C by I7 of the first current mirror will be greater than the charge released by I6; due to the injection of excess net charge, the voltage on capacitor C will gradually increase; the voltage on capacitor rise, causing the gate voltage of transistor M30' to rise, and the bearing voltage of resistor R1 to increase, so that the channel current in transistor M30' increases, and the current I8 increases; because I8 and I9 are current mirrors, the current of I9 follows the current of I8 As the current increases, the carrying voltage of the resistor R2 increases, and Vout increases; since Vout is the threshold voltage of the hysteresis comparator, as shown in Figure 10, the increased threshold voltage will cause the duty cycle to drop; After several cycles of adjustment, the duty cycle is adjusted to the set value, and at this point, the adjustment process ends.

The setting of the duty ratio of the clock signal is related to the values of x and y in FIG. 10 . The following analysis shows the relationship between the duty cycle of the clock signal and the values of x and y, and the set duty cycle is only related to x and y.

Set the time when Vin is 1 as t1, and the time when Vin is 0 as t2, then the period of the signal is T=t1+t2. The change in voltage across the capacitor is:

ΔV=(t1*y-t2*x)*I1/C

Vout=(Ibias-I10)*R2+R2*ΔV/R1

ΔVout=R2*ΔV/R1

D=t1/(t1+t2)

When working in a steady state, the output of the PWM filter is DC, that is, the amount of change is 0, and the duty cycle of the clock signal is a function of x and y.

ΔVout＝0←→t1*y＝t2*x

D=t1/(t1+t2)=x/(x+y)

It can be obtained from the above formula that when x=y, the duty cycle of the clock signal is 50%; when x=2y, the duty cycle of the clock signal is 66.7%. . . . The above calculations are obtained under ideal conditions. For actual circuits, due to the influence of leakage current and transistor matching, the results are slightly different.

FIG. 6 is a schematic diagram of a clock signal duty ratio detection and correction circuit composed of bipolar transistors. It can be seen from the comparison between FIG. 6 and the above-mentioned FIG. 5 that the MOS transistor 30' is replaced by the bipolar transistor T1, but the rest of the components are also composed of bipolar transistors and their circuit connections are the same, so the description will not be repeated.

Because bipolar transistors need to be driven by current, their control accuracy error is larger than that of MOS transistors.

Next, according to the schematic circuit diagram shown in FIG. 5 , a specific structure of a clock duty detection and correction circuit formed by MOS transistors is provided.

First, the structure of the detection circuit is described. As shown in FIG. 7, the circuit includes: an inverter, a pair of current switches, first, second and third current mirror circuits and a first bias circuit. The inverter is composed of a PMOS transistor M14 and an NMOS transistor M13 in series, that is, the source of the transistor M13 is grounded, its drain and gate are respectively connected to the drain and gate of the M14, and the source of the transistor M14 is connected to the power supply VCC is made. The current switch is composed of a pair of NMOS transistors M8 and M136. The gates of the transistors M8 and M136 input the clock signal Vin and the inverted clock signal output by the inverter respectively. The sources of the transistors M8 and M136 are connected to the NMOS The source and the drain of the transistor M19 are respectively connected to the drains of the PMOS transistors M27 and M10. The first current mirror circuit is composed of transistor M27 and PMOS transistor M26. The gate and drain of the transistor M27 are connected to the gate of M26, and its source is connected to the power supply VCC, while the drain of M26 is connected to the third current mirror circuit. The drain of the transistor M28, in addition, the gate of the transistor M28 is connected to the gate of M29, and the sources thereof are grounded to gnd. The second current mirror circuit is composed of transistor M10, PMOS transistor M9 and the third current mirror circuit is composed of NMOS transistors M29 and M28. The connection method is the same as that of the first current mirror circuit. Vbias2 provides gate bias voltage to M20. NMOS transistors M19 and M6 constitute a first bias circuit.

In addition, the drain of the above-mentioned transistor M8 outputs current to the correction circuit and is grounded through the capacitor C1 as a current-to-voltage converter. The current mirror circuit is used to convert the current when the clock signal is 1 to 1:1 and charge the capacitor C1. The constant current source formed by the NMOS transistors M34, M35 and M36, M37 can bias the current mirror to improve the response speed of the system. In addition, the PMOS transistor M25, the NMOS transistor M19, and M37 are common-cathode amplification (CASCODE) stages, and Vbias provides bias to their gates. This level of circuit can effectively reduce the channel length modulation effect.

The configuration of the correcting circuit portion having a current-to-voltage converter and a comparing circuit will be described below. The fourth current mirror circuit includes transistors M32 and M31. The gate and drain of the transistor M32 and M31 are connected, and the sources of the transistors are connected to the power supply. The NMOS transistor M30 is connected to the resistor R14, and the source of the NMOS transistor M33 is connected to the resistor R15 to form a second bias circuit. The drains of the transistors M33 and M30 are respectively connected to the drains of the PMOS transistors M32 and M31, and their gates are respectively connected to the gate of the PMOS transistor M25 and the drain of the M8, and the other ends of the two resistors R14 and R15 are grounded. The transistors M30 and M33 convert and compare the voltage to the current, and the difference current forms the threshold voltage of the hysteresis comparator on the resistor R13 to adjust the duty ratio of the clock signal.

The PMOS transistors M11, M24 and M12 are the third bias circuit, which provides a bias current, and its sources are connected to the power supply VCC, and its gate and the drain of M11 are connected to the drain of the NMOS transistor M22. The M24 and M12 The drain of the resistor R13 and the source of the PMOS transistor M25 are respectively connected. The source of the transistor M25 is connected to the drain of the PMOS transistor M12, its gate is connected to the reference voltage Verf, and its drain is connected to the drain of the NMOS transistor M23. The source of the transistor M23 is grounded, and its gate and drain are connected to the gate of the transistor M6 of the detection circuit.

Also, the current source generating circuit is composed of an operational amplifier, an NMOS transistor M22 and a resistor R12. The reference voltage Vref is added to the vin P terminal of the operational amplifier, the output terminal vout is connected to the gate of M22, the yin N terminal is connected to the source of M22 and one end of the resistor R12, and the other end of the resistor R12 is grounded to gnd.

And, the connection point between the drains of the PMOS transistors M24 and M33 and the resistor R13 outputs the Vout node as a DC level.

In the above circuit, the clock signal is input from Vin, and the clock signal and its inverted clock control the current switches of transistors M8 and M136 respectively. Transistors M26 and M27 convert the current when the clock signal is 1 to 1:1 and charge the capacitor C1 ; Transistors M10, M9 and M28, M29 convert the current when the clock signal is 0 to 1:1 and discharge the capacitor C1. The transistors M30 and M33 convert and compare the voltage to the current, and the difference current forms the threshold voltage of the hysteresis comparator on the resistor R13 to adjust the duty ratio of the clock signal.

The electric current in the setting transistor M6, M19 is 1, then when the clock signal is 1, the charging to electric capacity C1 is:

C1*(dV/dt)＝I*Duty

When the clock signal is 0, the discharge of the capacitor is:

C1*(dV/dt)＝I*(1-Duty)

In 1 clock signal period, the pure charging amount of the capacitor is:

C1*(dV/dt)＝I*(2*Duty-1) (5)

When the duty cycle of the clock signal is greater than 50%, the voltage on the capacitor is increasing; when the duty cycle of the clock signal is less than 50%, the voltage on the capacitor is decreasing. And, from the analysis of the above formula (5), in a steady state, DUTY=50%, the voltage on the capacitor remains stable.

It is assumed that the sine wave output changes slightly when the system is in a steady state, so as to deduce the small signal working principle and application formula of the circuit. The slight change of the system near the stable working state causes the slight change of the voltage on the capacitor to be:

C1*(dVc/dt)＝2*I*ΔDuty

A small change in the voltage on the capacitor causes the threshold voltage of the hysteretic comparator to change as:

ΔVcom=(ΔVc/R14)*R13

It is assumed that the change in the duty cycle of the clock signal is caused by a small change in the sine wave. From the previous analysis, the formula that causes the duty cycle of the clock signal to change is:

Δduty=ΔV/π*V

In the above formula, V is the amplitude of the sine wave signal.

When the system constitutes a closed loop, a small change in the sine wave voltage of any polarity will cause a small change in the same polarity, which appears at the input terminal N of the hysteresis comparator. The small change voltage is:

ΔVcom=K*ΔV

In the above formula, set the gain of the system loop as K, then the calculation formula of K is:

K＝{2*I/(f*C1*R14*π*V)}*R13

Regarding the value of K, there may be the following three situations.

1. K=1

In this case, any slight change in the duty cycle of the clock signal will be fully compensated in the next clock cycle, thereby restoring the duty cycle to the set value;

2. K<1

In this case, the adjustment of the duty cycle of the clock signal is carried out according to the ratio of geometric progression. If the accuracy of each adjustment is 90%, after two clock cycles, the adjustment accuracy can reach 1%;

3. K>1

In this case, an overshoot occurs to the duty cycle of the clock signal, and the duty cycle does not converge to the set value. If the duty cycle increases, the duty cycle will be smaller than the set value after the first adjustment, and will be greater than the set value after the second adjustment. And so on, the duty cycle of the clock signal will swing back and forth.

Example 2

Aiming at the bottleneck problem of parasitic capacitance on the response speed, the inventors adopted measures in the clock signal duty ratio adjustment circuit of Embodiment 2 to remove the influence of parasitic capacitance in the current conversion path, so that the system response speed was further improved. So that the circuit can be applied in the clock circuit of 100MHz to 400MHz.

Hereinafter, with reference to FIG. 8 , a clock signal duty ratio detection and correction circuit that eliminates the influence of parasitic capacitance will be described. In FIG. 8 , as in FIG. 5 , Vin is the clock signal input, and Vout is the output of the duty cycle detection and correction circuit, which is used as the threshold voltage of the hysteresis comparator.

The detection circuit includes: an inverter, a first current switch 1, a second current switch 2, M26" as a first current source circuit and M6" as a second current source circuit. The M26" input terminal of the first current source circuit is connected to the power supply VCC, and the output terminal is connected to the current switch 1. The M6" input terminal of the second current source circuit is connected to the switch 2, and the output terminal is grounded to GND. The current source circuit M26″ provides a current I1=m*I, and the current source circuit M6″ provides a bias current I2=n*I. One end of the first switch 1 is grounded to GND, the other end is connected to one end of the second switch 2, the other end of the switch 2 is connected to the power supply VCC, the clock signal input Vin and the inverted clock signal output by the inverter control the switch 1 and the switch 2 respectively working status. In addition, the common node of the switch 1 and the switch 2 is connected to a capacitor C as a current-voltage conversion circuit.

As for the correction circuit, it is completely the same as that in Fig. 5, so the description is omitted.

When Vin is at a high level, the switch 1 is turned on, and the capacitor C is charged with the output current I1 of the current source circuit M26", otherwise, the current I1 is connected to the ground; when Vin is at a low level, the switch 2 is turned on, Make the capacitor C discharge at the speed of the current I2 of the current source circuit M6", otherwise, connect the current I2 to VCC.

Set m=n=1, that is, set the duty cycle to 50% as an example to illustrate the operation of the above circuit.

When for some reason, the duty cycle of the clock signal increases, in each clock cycle, the charge injected by the current source circuit M26" will be greater than the charge released by the current source circuit M6"; due to the increase of the excess net charge, the capacitance The voltage on C will increase; the voltage carried by the capacitor C is connected to the gate of the transistor M30′, which causes the bias voltage of the transistor to increase, and the voltage carried by the resistor R1 increases; the increase in the voltage carried by the resistor R1 causes As the channel current increases in the transistor M30', the current I2 flowing through the current source circuit M6' increases; since M32' and M31' form a current mirror, its current I4 increases with the increase of I3; the current I4 The increase of the resistance R2' causes the carrying voltage of the resistor R2' to increase, that is, the output Vout increases; the output Vout is the threshold voltage of the comparator. According to Figure 10, the increased threshold voltage causes the clock signal duty cycle to drop; after several After the adjustment of one clock period, the duty ratio of the clock signal falls back to the set value, and at this time, the adjustment process ends. When the duty cycle of the clock signal decreases, the adjustment process is similar to the above, except that the change of the signal is opposite.

In the adjustment circuit of this embodiment, the duty cycle of the clock signal is determined by the values of m and n, and has nothing to do with other factors in the circuit. The following analysis gives the relationship between the duty cycle and m, n. For this reason, the time when the clock signal is at a high level is set as t1, the time when it is at a low level is t2, and the period of the clock signal is T=t1+t2. At this time, the voltage change on the capacitor in one clock cycle is:

ΔQ=I1*t1-I2*t2=(m*t1-n*t2)*I

Because ΔV=ΔQ/C, D=t1/(t1+t2), so in steady state operation, the duty cycle of the clock signal is:

D=n/(n+m)

Next, according to the schematic circuit diagram shown in FIG. 8 , a specific structure of a clock duty detection and correction circuit formed by MOS transistors is provided.

The clock signal duty ratio detection and correction circuit according to Embodiment 2 of the present invention is shown in FIG. 9 . Since the circuit structure of the correction circuit part is exactly the same as that of the correction circuit in Fig. 7 in Embodiment 1, and the response of the system is also the same as that described in Embodiment 1 above, so the explanation is omitted here.

Now, only the detection circuit of the present embodiment is carried out, as shown in Figure 6, the circuit includes: an inverter, the first and the second current switch, a current mirror circuit (that is, the above-mentioned equivalent to the first current source circuit) and a bias circuit (that is, equivalent to the above-mentioned second current source circuit). The inverter is composed of CMOS transistors M14 and M13, that is, the source of the transistor M13 is grounded, its drain and gate are respectively connected to the drain and gate of the M14, and the source of the transistor M14 is connected to the power supply VCC. The first and second current switch circuits are respectively OR gates composed of a pair of NMOS transistors M8, M136 and a pair of PMOS transistors M34, M35. The gates of the transistors M8 and M34 of the first switch are connected to the gates of the transistors M136 and M35 of the second switch, and the inverted clock signal output from the inverter and the clock signal Vin are respectively input. The M8 is connected to the drain of the M34, the drain of the M35 is grounded to GND, and the source of the M136 is connected to the power supply VCC. The sources of the M8 and M136 are connected to the drain of the PMOS transistor 19 together. The sources of the M34 and M35 are connected together to the drain of the PMOS transistor M26. The current mirror (source) circuit includes PMOS transistors M26 and M27, the gate of the M26 is connected to the gate and drain of the PMOS transistor M27, its source is connected to the power supply VCC, and the drain of M27 is connected to the drain of M37. The NMOS transistors M19 and M6 constitute a bias circuit, the gates of the M19 and M37 are connected to the bias voltage Vbias, and the sources thereof are respectively connected to the drains of the NMOS transistors M6 and M36. The gates of M23, M6 and M23 are connected together to the drain of the NMOS transistor M23 in the correction circuit section. In addition, the drain of the above-mentioned transistor M8 outputs a charging current to the capacitor C1 of the correction circuit, and is grounded to GND through the capacitor C1.

The correction circuit part is used to convert the current when the clock signal is 1 to 1:1 and charge the capacitor C1. Transistors M8 and M136 are current switching switches when the clock signal is 0; transistors M34 and M35 are current switching switches when the clock signal is 1. The bias circuit formed by transistors M34, M35 and M36, M37 can bias the current mirror to improve the response speed of the system. Moreover, the PMOS transistor M25, the NMOS transistor M19, and M37 are common-cathode amplification (CASCODE) stages, and this stage circuit can effectively reduce the channel length modulation effect.

Next, with reference to FIG. 10 , the process of fast adjustment of the duty ratio of the clock signal by the adjustment circuit of the present invention will be described.

The duty cycle variation of the clock signal is caused by factors such as temperature, unevenly distributed stress during packaging, and low-frequency noise. Since the factors that cause the change of the duty cycle change slowly, the duty cycle of the clock signal also changes slowly. In the improved circuit, the clock signal whose duty cycle changes slowly is considered as a pulse width modulation signal (abbreviated as PWM, that is, pulse width modulation). In a harsh application environment, the duty cycle of the clock signal will also change drastically, such as strong electromagnetic interference, and when the synchronous clock signal propagates in the medium, it will also cause severe jitter due to the sudden change of the medium property or distribution.

The duty cycle of the clock signal can be set to a definite value, and any deviation from this set value, including slow changes and sharp mutations, can be detected and corrected immediately, and the correction cycle is 1 to 2 clock signal periods. The duty cycle detection circuit of the present invention adopts two structures, and for the bottleneck problem of the fast response channel in the integrated circuit, the embodiment 1 adopts the method of equal constant current source for correction.

In the circuit of the present invention, the output of the clock signal is directly used in the duty cycle detection circuit, which eliminates the influence of the offset on the clock signal duty cycle caused by the matching of devices in integrated circuit manufacturing.

Figure 10 briefly depicts the response of the clock signal at two different fixed DC level components. It can be seen from the figure that the DC component of the sine wave is abrupt, and in practical applications, the same applies to the gradual change of the DC level component.

In Figure 10 shown, the DC component of the sine wave has a positive mutation at time T1. At this time, since the DC level of the hysteresis comparator does not follow the change immediately, the duty cycle of the clock signal will change suddenly, but the affected is just one clock cycle. At time T2, the threshold voltage of the hysteresis comparator has compensated the duty ratio change of the clock signal caused by the positive mutation of the DC component of the sine wave. Therefore, after only one clock cycle, the duty ratio of the clock signal will return to normal.

After the threshold voltage of the hysteresis comparator rises slightly due to the positive mutation of the DC component of the compensation sine wave, if the sudden component in the sine wave output remains unchanged, the threshold voltage of the hysteresis comparator also maintains its raised potential and remains remains unchanged, as shown in the waveform at time T2--T3 in Figure 10.

At time T3, the DC component of the sine wave output has a negative mutation. Since the DC level of the hysteresis comparator cannot follow the change immediately, the duty cycle of the clock signal will change suddenly. Since the DC component of the sine wave deviates from the positive direction, becomes deviated in the negative direction, so the affected clock signal may be 1 to 2 cycles (depending on the maximum step size that the clock signal duty cycle detection circuit may adjust). Also, the two clock signals affected are shown in FIG. 10, along with the T3--T4 period and the T4--T5 period.

At time T5, the change of the DC level of the hysteresis comparator has compensated the change of the duty cycle of the clock signal caused by the negative mutation of the DC component of the sine wave, so after time T5, the duty cycle of the clock signal will return to normal. At the same time, if the deviation component of the DC component of the negative sine wave remains unchanged, the deviation component of the DC level of the hysteresis comparator will also remain unchanged, as shown in FIG. 10 the waveform of the hysteresis comparator after time T5.

In the above introduction, the adjustment of the duty cycle of the clock signal is carried out for the sudden change of fast response; for the change of the duty cycle of the clock signal caused by the low-speed deviation, this circuit can also be adjusted and compensated.

In the circuit of the present invention, the low-pass filter that causes low-speed response has been removed, so the adjustment of the clock signal duty cycle is not affected by other parts of the circuit, but only with the clock signal duty cycle detection and adjustment circuit The device performance of the critical path is related.

In the above adjustment circuit, the error between the duty cycle of the clock signal and the required value is attenuated according to the exponential law. The adjustment range is set to be 80% each time, then after N times of adjustments, the error between the actual duty cycle of the clock signal and the set value is: (1-80%) ^N . If the adjustment error is set to 1%, then only 3 clock cycles are needed to complete the adjustment target under each adjustment range of 80%.

The above analysis is also applicable to the deviation of the DC component caused by factors such as temperature and device mismatch, no matter whether the DC deviation occurs at one end of the sine wave or the DC level end of the hysteresis comparator.

The clock signal duty cycle adjustment circuit according to the present invention can be used in almost all clock circuits to adjust the clock signal duty cycle. Due to the wide application of PLL and crystal oscillator in modern communication systems, the application of this clock duty ratio adjustment circuit will be very extensive. Can be widely used in digital communication systems, multimedia and other fields. The clock signal duty ratio adjustment circuit of the present invention has the characteristics of fast response speed and strong anti-electromagnetic interference ability, and can also be applied to electronic countermeasures, radar and other equipment.

Above, the preferred embodiments of the present invention have been disclosed with reference to the accompanying drawings, but the present invention is not limited to the details of the above-described embodiments. Those of ordinary skill in the art accept the inspiration of the present invention, and it is easy to make various improvements, modifications or replacements to the present invention, and these should not be regarded as having departed from the spirit scope of the present invention, and the protection scope of the patent of the present invention should be determined by the patent of the present invention. defined by the claims.

Claims (9)

1, a kind of long-delay clock pulse width regulating circuit is characterized in that, this circuit comprises:

A hysteresis comparator be used for the sine wave signal of an input end input and the threshold voltage of another input end input are compared, and output has the clock signal of regulation dutycycle;

A circuit for detecting, whether the described clock signal that is used to detect the described hysteresis comparator output of input exists floating sign, and according to floating sign output difference voltage; And

A correcting circuit is used for the difference voltage according to described circuit for detecting output, proofreaies and correct the described threshold voltage of the described hysteresis comparator of input.

2, long-delay clock pulse width regulating circuit according to claim 1 is characterized in that described circuit for detecting has a phase inverter, the clock signal of input is carried out anti-phase, output inversion clock signal; A current switch carries out switch according to clock signal and inversion clock signal; The 1st current mirroring circuit, described the 1st current mirroring circuit is connected with current switch one input end, when described clock signal is high level, the electric capacity of described correcting circuit is charged; The 2nd current mirroring circuit, described the 2nd current mirroring circuit is connected with another input end of described current switch; And the 3rd current mirroring circuit, described the 3rd current mirroring circuit is connected with the 2nd current mirroring circuit, when described clock signal is low level, the electric capacity of described correcting circuit is discharged.

3, long-delay clock pulse width regulating circuit according to claim 2 is characterized in that described circuit for detecting also has current source circuit, provides bias current to described current switch.

4, long-delay clock pulse width regulating circuit according to claim 1 is characterized in that described circuit for detecting has: a phase inverter, carry out anti-phasely to the clock signal of input, and the inversion clock signal is provided; Pair of series the 1st and the 2nd current switch carry out switch according to the inversion clock signal that clock signal and described phase inverter provide simultaneously; The 1st current source circuit, described the 1st current source circuit one termination power, another termination the 1st current switch when described clock signal is high level, charges to the electric capacity of described correcting circuit; And the 2nd current source circuit, described the 2nd current source circuit one termination the 2nd current switch, other end ground connection when described clock signal is low level, is discharged to the electric capacity of described correcting circuit.

5, according to claim 2,3 or 4 each described long-delay clock pulse width regulating circuits, it is characterized in that described current switch be constitute by two MOS transistor or the door.

6, according to claim 2,3 or 4 each described long-delay clock pulse width regulating circuits, it is characterized in that described current mirroring circuit is that drain electrode, the grid of a MOS transistor is connected with the grid of another MOS transistor, the source electrode of described two MOS transistor connects power supply, and the drain electrode of described another MOS transistor is an output terminal.

7,, it is characterized in that described correcting circuit is to be made of the change-over circuit and the comparator circuit of voltage to electric current according to each described long-delay clock pulse width regulating circuit of claim 1 to 4.

8, long-delay clock pulse width regulating circuit according to claim 7 is characterized in that described correcting circuit has the current source circuit that is made of operational amplifier, nmos pass transistor and resistance.

9, long-delay clock pulse width regulating circuit according to claim 7 is characterized in that comprising the circuit that MOS transistor and electric capacity are formed by described electric current to the change-over circuit of voltage.

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