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CN115207097B - Lateral AlN epitaxial Schottky diode and its fabrication process - Google Patents

Lateral AlN epitaxial Schottky diode and its fabrication process

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Publication number
CN115207097B
CN115207097B CN202210727041.5A CN202210727041A CN115207097B CN 115207097 B CN115207097 B CN 115207097B CN 202210727041 A CN202210727041 A CN 202210727041A CN 115207097 B CN115207097 B CN 115207097B
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layer
aln
metal layer
epitaxial
substrate
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CN115207097A (en
Inventor
刘国梁
方雪冰
樊永辉
许明伟
樊晓兵
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Shenzhen Huixin Communication Technology Co ltd
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Shenzhen Huixin Communication Technology Co ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/60Schottky-barrier diodes 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6738Schottky barrier electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/675Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503Nitride Group III-V materials, e.g. AlN or GaN
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/64Electrodes comprising a Schottky barrier to a semiconductor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/01Manufacture or treatment
    • H10D8/051Manufacture or treatment of Schottky diodes

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Abstract

本发明公开一种横向结构AlN外延的肖特基二极管及制作工艺,该二极管包括:衬底层,具有相对设置的第一表面和第二表面;背面电极,设置于衬底层的第一表面;AlN缓冲层、UID‑AlN层及N‑AlN层依次层叠设置于衬底层的第二表面;GaN保护层生长于N‑AlN层表面;隔离环,环设于UID‑AlN层、N‑AlN层和GaN保护层的边缘;欧姆接触金属层沉积于GaN保护层上;肖特基接触金属层沉积于GaN保护层上;SiO2钝化层沉积于欧姆接触金属层、肖特基接触金属层、隔离环和GaN保护层上。本发明旨在实现肖特基二极管满足更高击穿电压、更低导通压降以及在高频、低开关损耗的使用需求。

The present invention discloses a Schottky diode with a lateral AlN epitaxial structure and a manufacturing process. The diode comprises: a substrate layer having a first surface and a second surface arranged opposite each other; a back electrode disposed on the first surface of the substrate layer; an AlN buffer layer, a UID-AlN layer, and a N-AlN layer stacked in sequence on the second surface of the substrate layer; a GaN protective layer grown on the surface of the N-AlN layer; an isolation ring disposed at the edges of the UID-AlN layer, the N-AlN layer, and the GaN protective layer; an ohmic contact metal layer deposited on the GaN protective layer; a Schottky contact metal layer deposited on the GaN protective layer; and a SiO2 passivation layer deposited on the ohmic contact metal layer, the Schottky contact metal layer, the isolation ring, and the GaN protective layer. The present invention aims to achieve a Schottky diode that meets the requirements of higher breakdown voltage, lower on-state voltage drop, and high frequency and low switching loss.

Description

Schottky diode with AlN epitaxy of transverse structure and manufacturing process
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a Schottky diode with a transverse structure AlN epitaxy and a manufacturing process thereof.
Background
Along with the wide application of the power diode in electronic products such as high-frequency inverter, digital products, generators, televisions and the like, the power diode is generally provided with a common rectifying diode, a Schottky diode and a PIN diode, wherein the Schottky diode has the characteristics of low on-state voltage drop, large leakage current and almost zero reverse recovery time, and the conventional Schottky diode is generally made of semiconductor materials such as Si, siC or GaN and the like to make Schottky contact, so that the use requirements of higher breakdown voltage, lower on-state voltage drop and high frequency and low switching loss can not be met gradually.
Disclosure of Invention
The invention mainly aims to provide a Schottky diode with a transverse structure AlN epitaxy and a manufacturing process thereof, and aims to realize that the Schottky diode meets the use requirements of higher breakdown voltage, lower conduction voltage drop and high frequency and low switching loss.
In order to achieve the above purpose, the invention provides a schottky diode with a lateral structure AlN epitaxy and a manufacturing process thereof, comprising a substrate layer, a first substrate layer and a second substrate layer, wherein the substrate layer is provided with a first surface and a second surface which are oppositely arranged;
a back electrode arranged on the first surface of the substrate layer;
the AlN buffer layer, the UID-AlN layer and the N-AlN layer are sequentially laminated on the second surface of the substrate layer;
the GaN protection layer grows on the surface of the N-AlN layer;
The isolating ring is arranged at the edges of the UID-AlN layer, the N-AlN layer and the GaN protective layer in a surrounding manner;
the ohmic contact metal layer is deposited on the GaN protective layer and is arranged close to the isolating ring;
the Schottky contact metal layer is deposited on the GaN protective layer and is positioned at the center of the Schottky diode;
and the SiO2 passivation layer is deposited on the ohmic contact metal layer, the Schottky contact metal layer, the isolation ring and the GaN protection layer.
Optionally, the thickness of the UID-AlN layer is 100 nm-300 nm, and the thickness of the N-AlN layer is 1 μm-3 μm.
Optionally, the spacer is formed by implanting He and/or Ar and/or In particles.
Optionally, the ohmic contact metal layer is one or more of Ti, al, ni or Au.
Optionally, the ohmic contact metal layer comprises a first Ti metal layer, an Al metal layer, a second Ti metal layer and an Au metal layer which are sequentially formed on the surface of the N-AlN layer, wherein the thickness of the first Ti metal layer is 10 nm-30 nm, the thickness of the Al metal layer is 50 nm-150 nm, the thickness of the Ti metal layer is 3 nm-10 nm, and the thickness of the Au metal layer is 20 nm-80 nm.
Optionally, the schottky metal layer comprises a Pt metal layer and an Au metal layer which are sequentially formed on the surface of the N-AlN layer, wherein the thickness of the Pt metal layer is 10 nm-50 nm, and the thickness of the Au metal layer is 50 nm-300 nm.
Optionally, the interval between the ohmic contact metal layer and the Schottky contact metal layer is 15-20 μm.
Optionally, the substrate is a high-resistance sapphire substrate with a bevel angle of 0.1-0.5 degrees.
Optionally, the back electrode includes an Ag metal layer, a Ni metal layer, and a third Ti metal layer sequentially formed on the first surface of the substrate layer.
The invention provides a manufacturing process of a Schottky diode, which comprises the following steps:
Preparing a substrate;
coating an AlN material on the substrate to form an AlN buffer layer;
epitaxially growing on the AlN buffer layer to form an n-type AIN epitaxial barrier layer;
doping Si into the N-type AIN epitaxial barrier layer to divide the N-type AIN epitaxial barrier layer into a UID-AlN layer and an N-AlN layer;
epitaxially growing a GaN material on the n-AIN epitaxial barrier layer to form a GaN protection layer;
injecting He and/or Ar and/or In particles at the edges of the UID-AlN layer, the N-AlN layer and the GaN protective layer by adopting an ion implantation method to form an isolating ring;
forming ohmic contact and schottky contact on the GaN protection layer by physical vapor deposition;
Depositing on the ohmic contact metal layer, the Schottky contact metal layer, the isolation ring and the GaN protective layer to form a SiO2 passivation layer;
The substrate was thinned to 150 μm and the Ti/Ni/Ag ions evaporated to form a back electrode.
The invention provides an AlN epitaxial Schottky diode with a transverse structure, which comprises a substrate layer, a back electrode, an AlN buffer layer, a UID-AlN layer, an N-AlN layer, a GaN protective layer, an isolating ring, an ohmic contact metal layer, a Schottky contact metal layer, an SiO2 passivation layer and a GaN protective layer, wherein the substrate layer is provided with a first surface and a second surface which are oppositely arranged, the back electrode is arranged on the first surface of the substrate layer, the AlN buffer layer, the UID-AlN layer and the N-AlN layer are sequentially stacked on the second surface of the substrate layer, the GaN protective layer grows on the surface of the N-AlN layer, the isolating ring is arranged on the edges of the UID-AlN layer, the N-AlN layer and the GaN protective layer in a surrounding mode, the ohmic contact metal layer is deposited on the GaN protective layer and is close to the isolating ring, the Schottky contact metal layer is deposited on the GaN protective layer, the Schottky contact metal layer is positioned at the center of the Schottky contact metal layer, and the SiO2 passivation layer is deposited on the ohmic contact metal layer, the Schottky contact metal layer and the isolating ring. The AlN material has higher forbidden bandwidth than the material adopted by epitaxial growth in the prior art, the barrier layer with the same width has higher breakdown voltage, the current leakage of the device can be reduced, meanwhile, because the Schottky contact is only conductive, no charge storage effect can be used under the conditions of high frequency and low switching loss, and the use requirements of high breakdown voltage, high frequency and low switching loss can be met.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional view of an embodiment of an AlN-epitaxial schottky diode with a lateral structure according to the present invention;
fig. 2 is a top cross-sectional view of an embodiment of an AlN-epitaxial schottky diode of the present invention with a lateral structure;
Fig. 3 is a process flow diagram of an embodiment of a schottky diode manufacturing process according to the present invention;
Fig. 4 to fig. 9 are cross-sectional views of a device in a process of manufacturing a schottky diode with a vertical structure according to an embodiment of the present invention.
Reference numerals illustrate:
Reference numerals Name of the name Reference numerals Name of the name
10 Substrate layer 20 AlN buffer layer
21 UID-AlN layer 22 N-AlN layer
30 GaN protective layer 40 Isolation ring
50 Ohmic contact metal layer 51 Schottky contact metal layer
60 SiO2 passivation layer 70 Potential barrier region
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. It should be noted that, if directional indications (such as up, down, left, right, front, and rear are referred to in the embodiments of the present invention), the directional indications are merely used to explain the relative positional relationship, movement conditions, and the like between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
The utility model provides a lateral structure AlN epitaxial Schottky diode and manufacturing process, aim at realizing that Schottky diode satisfies higher breakdown voltage, lower conduction voltage drop and at high frequency, low switching loss's user demand.
Referring to fig. 1 and 2, in an embodiment of the present invention, the AlN-epitaxial schottky diode with a lateral structure includes:
A substrate layer 10 layer, the substrate layer 10 layer having oppositely disposed first and second surfaces;
A back electrode provided on the first surface of the substrate layer 10;
An AlN buffer layer 20, a UID-AlN layer 21 and an N-AlN layer 22 are sequentially laminated on the second surface of the substrate layer 10;
a GaN protection layer 30, wherein the GaN protection layer 30 is grown on the surface of the N-AlN layer 22;
A spacer ring 40, wherein the spacer ring 40 is arranged around edges of the UID-AlN layer 21, the N-AlN layer 22 and the GaN protection layer 30;
An ohmic contact metal layer 50, the ohmic contact metal layer 50 being deposited on the GaN protection layer 30 and disposed adjacent to the spacer 40;
A schottky contact metal layer 51, the schottky contact metal layer 51 being deposited on the GaN protection layer 30, and the schottky contact metal layer 51 being located at a central position of the schottky diode;
a SiO2 passivation layer 60, the SiO2 passivation layer 60 being deposited on the ohmic contact metal layer 50, the schottky contact metal layer 51, the spacer 40 and the GaN protection layer 30.
The existing schottky diode usually adopts Si, siC, gaN as an epitaxial material, AIN adopted in the embodiment is used for manufacturing the schottky diode by epitaxy, the AlN material has higher forbidden band width compared with Si, siC, gaN material, a barrier layer with the same width has higher breakdown voltage, the schottky contact provides lower conduction voltage drop during forward conduction, and meanwhile, because the schottky contact is only conductive to electrons, no charge storage effect can be used under the conditions of high frequency and low switching loss.
In this embodiment, the N-AlN layer 22 (N-type AIN epitaxial barrier layer) is grown on the substrate layer 10, and the AIN epitaxial barrier layer is a high-resistivity epitaxial layer, so that the schottky diode is guaranteed to have a high breakdown voltage, the current leakage of the device is reduced, the performance deterioration caused by the increase of the operating temperature of the device is prevented, that is, good thermal conductivity is achieved, the switching characteristics are optimized, the growth quality of other epitaxial layers on the device is guaranteed, and the performance is improved.
The UID-AlN layer 21 (unintentionally doped AlN layer) has a high resistance, typically on the order of microns in thickness, for forming a two-dimensional electron gas structure (2 DEG), and reduces background carrier concentrations to reduce drain current collapse caused by buffer layer trap effects. The epitaxy of the AlN layer needs a buffer layer, so that lattice mismatch and thermal mismatch between the III-nitride epitaxial layer and the substrate are effectively relieved, strain of the III-nitride epitaxial layer caused by stress is reduced, and dislocation and defect are reduced. In addition, the seed crystal layer is arranged between the substrate and the buffer layer, so that silicon can be effectively prevented from diffusing from the substrate into the III-nitride epitaxial layer.
The AlN buffer layer 20 can effectively relieve lattice mismatch and thermal mismatch between the N-AlN layer 22 and the substrate layer 10, reduce strain of the N-AlN layer 22 caused by stress, and reduce dislocation and defect.
The GaN protection layer 30 is mainly responsible for preventing the AlN material from oxidizing in order to prevent affecting the device performance.
Spacer 40 breaks the AlN material lattice by implanting inert ions to obtain a high resistance region.
The schottky contact forms a schottky barrier to increase the resistance value, and the ohmic contact is formed to decrease the resistance value, but the metal materials used for the schottky contact and the ohmic contact in this embodiment are not limited.
The SiO2 passivation layer 60 is deposited on the front side of the schottky diode to provide oxidation resistance and insulation.
The schottky diode in this embodiment adopts AlN material, forms the barrier layer in epitaxial growth of substrate layer 10, and AlN material has higher forbidden bandwidth than the material that epitaxial growth adopted in prior art, and the barrier layer of same width has higher breakdown voltage, can reduce device current leakage, prevents that device operating temperature from rising and arouses the performance deterioration, has good heat conductivity promptly, optimizes the switching characteristic, and schottky contact provides lower switching pressure drop when forward switching on simultaneously because schottky contact only electron is electrically conductive, does not have charge storage effect to use under high frequency, low switching loss's circumstances, can satisfy high breakdown voltage, high frequency, low switching loss's user demand.
The invention provides a Schottky diode with a transverse structure AlN epitaxy, which comprises a substrate layer 10 layer, a back electrode, an AlN buffer layer 20, a UID-AlN layer 21 and an N-AlN layer 22, a GaN protective layer 30, an isolating ring 40, an ohmic contact metal layer 50, a Schottky contact metal layer 51, an SiO2 passivation layer 60 and a SiOcontact metal layer 51, wherein the substrate layer 10 layer is provided with a first surface and a second surface which are oppositely arranged, the back electrode is arranged on the first surface of the substrate layer 10 layer, the AlN buffer layer 20, the UID-AlN layer 21 and the N-AlN layer 22 are sequentially stacked on the second surface of the substrate layer 10 layer, the GaN protective layer 30 grows on the surface of the N-AlN layer 22, the isolating ring 40 is annularly arranged on edges of the UID-AlN layer 21, the N-AlN layer 22 and the GaN protective layer 30, the ohmic contact metal layer 50 is deposited on the GaN protective layer 30 and is close to the isolating ring 40, the Schottky contact metal layer 51 is deposited on the GaN protective layer 30, the Schottky contact metal layer 51 is positioned on the central position of the Schottky contact metal layer 30, and the SiO2 passivation layer 60 is deposited on the ohmic contact metal layer 50 and the SiOcontact metal layer 40. The barrier layer is formed in the epitaxial growth of the substrate layer 10, the AlN material has a higher forbidden bandwidth than the material adopted in the epitaxial growth in the prior art, the barrier layer with the same width has a higher breakdown voltage, the current leakage of the device can be reduced, meanwhile, because the Schottky contact is only conductive to electrons, no charge storage effect can be used under the conditions of high frequency and low switching loss, and the use requirements of high breakdown voltage, high frequency and low switching loss can be met.
Referring to fig. 2, an SiO2 passivation layer 60 is deposited on the ohmic contact metal layer 50, the schottky contact metal layer 51, the spacer ring 40 and the GaN protection layer 30, and the SiO2 passivation layer 60 is disposed on the front surface of the schottky diode for protecting the entire schottky diode, thereby having oxidation resistance and insulation.
The barrier region 70 is composed of an AlN buffer layer 20, a UID-AlN layer 21, and an N-AlN and GaN protective layer 30.
The schottky contact forms a schottky barrier to increase the resistance value, and the ohmic contact is formed to decrease the resistance value, but the metal materials used for the schottky contact and the ohmic contact in this embodiment are not limited. A schottky contact is formed in the middle of the barrier region 70 and an ohmic contact is formed at the edge of the barrier region 70.
In one embodiment, the thickness of the UID-AlN layer 21 is 100 nm-300 nm, and the thickness of the N-AlN layer 22 is 1 μm-3 μm.
In one embodiment, the spacer 40 is formed by implanting He and/or Ar and/or In particles.
In this embodiment, edge protection of the barrier region 70 may use He and/or Ar and/or In particle implantation to disrupt the material lattice to obtain a high resistance region.
In one embodiment, the ohmic contact metal layer 50 is one or more of Ti, al, ni, or Au.
In an embodiment, the ohmic contact metal layer 50 includes a first Ti metal layer, an Al metal layer, a second Ti metal layer, and an Au metal layer sequentially formed on the surface of the N-AlN layer 22, wherein the thickness of the first Ti metal layer is 10nm to 30nm, the thickness of the Al metal layer is 50nm to 150nm, the thickness of the Ti metal layer is 3nm to 10nm, and the thickness of the Au metal layer is 20nm to 80nm.
In one embodiment, the schottky metal layer includes a Pt metal layer and an Au metal layer sequentially formed on the surface of the N-AlN layer 22, where the thickness of the Pt metal layer is 10nm to 50nm, and the thickness of the Au metal layer is 50nm to 300nm.
The GaN protection layer is a metal material for protecting the reaction during the schottky contact and the ohmic contact. Since the schottky contact and the ohmic contact are required to be completed at a higher temperature, and the schottky contact and the ohmic contact are both interface contacts, the GaN protection layer has an anti-oxidation effect for protecting the metal material participating in the reaction.
In one embodiment, the spacing between the ohmic contact metal layer 50 and the schottky contact metal layer 51 is 15 μm to 20 μm.
In one embodiment, the substrate layer 10 is a high-resistance sapphire substrate layer 10 with a bevel angle of 0.1-0.5 degrees.
In this embodiment, sapphire is an insulating material with excellent performance, the width of the band is as large as 10ev at normal temperature, and leakage current and parasitic capacitance are small. The AlN buffer layer 20 formed by taking high-resistance sapphire as a substrate layer has larger resistance and better insulativity.
The high-resistance sapphire substrate layer 10 adopted in the embodiment is matched with AlN lattice, so that good combination of a chip and a substrate is facilitated.
In one embodiment, the back electrode includes an Ag metal layer, a Ni metal layer, and a third Ti metal layer sequentially formed on the first surface of the substrate layer 10 layer.
The invention provides a manufacturing process of a Schottky diode.
Referring to fig. 3, the fabrication process includes the steps of:
Step S10, preparing a substrate layer 10, and coating an AlN material on the substrate layer 10 to form an AlN buffer layer 20;
Step S20, epitaxially growing on the AlN buffer layer 20 to form an n-type AIN epitaxial barrier layer;
Step S30, doping Si into the N-type AIN epitaxial barrier layer to divide the N-type AIN epitaxial barrier layer into a UID-AlN layer 21 and an N-AlN layer 22;
step S40, epitaxially growing on the n-type AIN epitaxial barrier layer to form a GaN protection layer 30;
Step S50, injecting He and/or Ar and/or In particles at the edges of the UID-AlN layer 21, the N-AlN layer 22 and the GaN protective layer 30 by adopting an ion implantation method to form a separation ring 40;
Step S60, forming ohmic contact and schottky contact on the GaN protection layer 30 by physical vapor deposition;
Step S70 of depositing on the ohmic contact metal layer 50, the schottky contact metal layer 51, the spacer 40, and the GaN protection layer 30 to form a SiO2 passivation layer 60;
Step S80, thinning the substrate layer 10 to 150 μm and evaporating Ti/Ni/Ag ions to form a back electrode.
In an embodiment of step S10, an N-type AIN epitaxial barrier layer, a1 μm-3 umUID-AlN21 layer (unintentionally doped AlN layer), a 100 nm-300 nm silicon doped N-AlN layer 22, and a1 nm-3 nmgan protection layer 30 are grown on a 0.1-0.5 degree bevel sapphire substrate by MOCVD (metal organic chemical vapor deposition), the sapphire substrate is a high-resistance substrate, and is lattice-matched with aluminum nitride, good bonding with a substrate is facilitated, the high-resistance epitaxial layer ensures a high breakdown voltage of a tube, reduces current leakage of a device, prevents performance deterioration caused by an increase in the operating temperature of the device, i.e., has good thermal conductivity, optimizes switching characteristics, ensures growth quality of other epitaxial layers thereon, and improves performance.
In steps S20 to S40, the UID-AlN layer 21 (unintentionally doped AlN layer) has high resistance, typically in the order of micrometers in thickness, for forming a two-dimensional electron gas structure (2 DEG), and reduces the background carrier concentration to reduce drain current collapse caused by buffer layer trap effects. The epitaxy of the AlN layer needs a buffer layer, so that lattice mismatch and thermal mismatch between the III-nitride epitaxial layer and the substrate are effectively relieved, strain of the III-nitride epitaxial layer caused by stress is reduced, and dislocation and defect are reduced. In addition, the seed crystal layer is arranged between the substrate and the buffer layer, so that silicon can be effectively prevented from diffusing from the substrate into the III-nitride epitaxial layer.
In an embodiment In step S50, edge protection may use He and/or Ar and/or In particle implantation to break the material lattice to obtain a high resistance region to form a cut-off ring.
In one embodiment of step S60, the key of the schottky contact is the interface contact, and the GaN protection layer 30 can prevent the oxidation damage.
In an embodiment of step S70, the SiO2 passivation layer covers the front surface of the schottky diode to play a role in oxidation resistance and insulation.
Referring to fig. 4, after steps S10 to S40 are performed, an AlN material is coated on the high-resistance sapphire substrate layer 10 to form an AlN buffer layer 20, an epitaxial barrier layer is epitaxially grown, and an N-AlN layer 22 and a UID-AlN layer 21 are formed on the epitaxial barrier layer by doping Si, wherein the Si-doped region is the N-AlN layer 22, the remaining regions are UID-AlN, and a GaN protection layer 30 is epitaxially grown on the N-AlN layer 22.
Referring to fig. 5, after step S50 is performed, the implanted particles form a spacer 40 at the edge of the schottky diode.
Referring to fig. 6 and 7, after step S60 is performed, the physical vapor deposition technique is used to form an ohmic contact and a schottky contact through high temperature annealing.
Referring to fig. 8, after step S70 is performed, a passivation layer is formed on the ohmic contact metal layer 50, the schottky contact metal layer 51, the spacer 40, and the GaN protection layer 30 to cover the front surface of the schottky diode.
Referring to fig. 9, after step S80 is performed, the substrate layer 10 forms a back electrode of a Ti, ni, ag three-layer metal layer. The back substrate was thinned to 150um and Ti/Ni/Ag was evaporated as a back electrode (ground).
The manufacturing process of the Schottky diode is used for manufacturing the AlN epitaxial Schottky diode with the transverse structure. The manufacturing process of the schottky diode of the present invention adopts all the technical solutions of all the embodiments, so that the schottky diode has at least all the beneficial effects brought by the technical solutions of the embodiments, and the details are not repeated here.
The foregoing description is only of the optional embodiments of the present invention, and is not intended to limit the scope of the invention, and all equivalent structural modifications made by the present description and accompanying drawings or direct/indirect application in other related technical fields are included in the scope of the present invention.

Claims (10)

1. A laterally structured AlN-epitaxial schottky diode comprising:
A substrate layer having oppositely disposed first and second surfaces;
a back electrode arranged on the first surface of the substrate layer;
the AlN buffer layer is epitaxially grown on the AlN buffer layer to form an N-type AIN epitaxial barrier layer, wherein the N-type AIN epitaxial barrier layer is an epitaxial layer with high resistivity, the N-type AIN epitaxial barrier layer is divided into a UID-AlN layer and an N-AlN layer, and the AlN buffer layer, the UID-AlN layer and the N-AlN layer are sequentially laminated on the second surface of the substrate layer;
the GaN protection layer grows on the surface of the N-AlN layer;
The isolating ring is arranged at the edges of the UID-AlN layer, the N-AlN layer and the GaN protective layer in a surrounding manner;
the ohmic contact metal layer is deposited on the GaN protective layer and is arranged close to the isolating ring;
the Schottky contact metal layer is deposited on the GaN protective layer and is positioned at the center of the Schottky diode;
and the SiO2 passivation layer is deposited on the ohmic contact metal layer, the Schottky contact metal layer, the isolation ring and the GaN protection layer.
2. A laterally structured AlN epitaxial schottky diode according to claim 1, wherein the UID-AlN layer has a thickness of 100nm to 300nm and the N-AlN layer has a thickness of 1 μm to 3 μm.
3. A laterally structured AlN epitaxial schottky diode according to claim 1, wherein the spacer rings are formed by injecting He and/or Ar and/or In particles.
4. A laterally structured AlN epitaxial schottky diode according to claim 1, wherein the ohmic contact metal layer is comprised of one or more of Ti, al, ni or Au.
5. The AlN epitaxial Schottky diode with the transverse structure according to claim 4, wherein the ohmic contact metal layer comprises a first Ti metal layer, an Al metal layer, a second Ti metal layer and an Au metal layer which are sequentially formed on the surface of the N-AlN layer, wherein the thickness of the first Ti metal layer is 10 nm-30 nm, the thickness of the Al metal layer is 50 nm-150 nm, the thickness of the Ti metal layer is 3 nm-10 nm, and the thickness of the Au metal layer is 20 nm-80 nm.
6. The AlN epitaxial Schottky diode with the transverse structure according to claim 1, wherein the Schottky contact metal layer comprises a Pt metal layer and an Au metal layer which are sequentially formed on the surface of the N-AlN layer, wherein the thickness of the Pt metal layer is 10 nm-50 nm, and the thickness of the Au metal layer is 50 nm-300 nm.
7. A laterally structured AlN epitaxial schottky diode according to claim 1, wherein the ohmic contact metal layer is spaced from the schottky contact metal layer by a distance of 15 μm to 20 μm.
8. A laterally structured AlN epitaxial schottky diode according to claim 1, wherein said substrate is a 0.1-0.5 degree beveled high-resistance sapphire substrate.
9. A laterally structured AlN epitaxial schottky diode according to claim 1, wherein said back electrode includes an Ag metal layer, a Ni metal layer and a third Ti metal layer formed in sequence on a first surface of said substrate layer.
10. The manufacturing process of the Schottky diode is characterized by comprising the following steps of:
Preparing a substrate;
coating an AlN material on the substrate to form an AlN buffer layer;
epitaxially growing on the AlN buffer layer to form an n-type AIN epitaxial barrier layer;
doping Si into the N-type AIN epitaxial barrier layer to divide the N-type AIN epitaxial barrier layer into a UID-AlN layer and an N-AlN layer;
epitaxially growing a GaN material on the n-AIN epitaxial barrier layer to form a GaN protection layer;
injecting He and/or Ar and/or In particles at the edges of the UID-AlN layer, the N-AlN layer and the GaN protective layer by adopting an ion implantation method to form an isolating ring;
forming an ohmic contact metal layer and a Schottky contact metal layer on the GaN protective layer through physical vapor deposition;
Depositing on the ohmic contact metal layer, the Schottky contact metal layer, the isolation ring and the GaN protective layer to form a SiO2 passivation layer;
The substrate was thinned to 150 μm and the Ti/Ni/Ag ions evaporated to form a back electrode.
CN202210727041.5A 2022-06-24 2022-06-24 Lateral AlN epitaxial Schottky diode and its fabrication process Active CN115207097B (en)

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JP2011210779A (en) * 2010-03-29 2011-10-20 Oki Electric Industry Co Ltd Schottky diode and method for manufacturing the same
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