CN115188403A - A memory chip and a control method for the memory chip - Google Patents

Abstract

The present application provides a memory chip and a control method for the memory chip. The memory chip includes a plurality of memory modules, each memory module includes a plurality of memory arrays, and each memory array includes: a first memory array, and the first memory array operates in a first memory array. a storage mode; a second storage array, the second storage array operates in the second storage mode; a control circuit is connected to the first storage array and the second storage array, and the control circuit is used to write at least part of the data in the second storage array into the first storage array In a storage array, an external device can read and write data to the first storage array; and at least part of the data in the first storage array is written into the second storage array for data backup. Specifically, the external device only reads and writes to the first storage array, so that the memory chip of the present application can have the characteristics of fast read and write speed and long service life, and the data in the first storage array can be backed up in the second storage array, It has the characteristics that data will not be lost after power failure.

Description

A memory chip and a control method for the memory chip

technical field

The present application relates to the field of chip technology, and in particular, to a memory chip and a control method for the memory chip.

Background technique

Dynamic random access memory (DRAM) stores information through the amount of charge on the capacitor in the storage unit, and belongs to volatile memory. to refresh the memory cells, and the data will be lost when the power is turned off.

SUMMARY OF THE INVENTION

The invention provides a memory chip and a control method for the memory chip, the memory chip has the characteristics of fast read and write speed, long life and no data loss after power off.

In a first aspect, the present application provides a memory chip, the memory chip includes: a plurality of memory modules, each memory module includes a plurality of memory arrays, and each memory array includes: a first memory array, and the first memory array works in the first storage mode; a second storage array, the second storage array works in the second storage mode; a control circuit, connecting the first storage array and the second storage array, the control circuit is used to write at least part of the data in the second storage array into the first storage array In the storage array, the external device reads and writes data to the first storage array; and at least part of the data in the first storage array is written into the second storage array for data backup.

The storage array includes: a first sense amplifier, connected to the first storage array, for reading and writing data of the first storage array; a second sense amplifier, connected to the second storage array, and used for reading and writing data of the second storage array.

The first memory array includes: a plurality of first memory cells, and each first memory cell includes: a first transistor, the control end of the first transistor is connected to the first word line, and the first end of the first transistor is connected to the first bit line; a first capacitor, the first end of the first capacitor is connected to the second end of the first transistor, and the second end of the first capacitor is connected to the first control line; the second storage array includes: a plurality of second storage units, each The second memory unit includes: a second transistor, the control end of the second transistor is connected to the second word line, the second end of the second transistor is connected to the second bit line; a second capacitor, the first end of the second capacitor is connected to the second transistor The first end of the second capacitor is connected to the second control line.

Wherein, the storage array further includes: a first switch circuit, the first switch circuit is connected between the first sense amplifier and the first storage array; a second switch circuit, the second switch circuit is connected between the second sense amplifier and the second storage array; A switch circuit is turned on to read data from the first storage array; the second switch circuit is turned on, and at least part of the data in the first storage array is written into the second storage array.

The first switch circuit includes: a first switch, the control end of the first switch is connected to the first drive line, the first end of the first switch and the second end of the first switch are connected to the first bit line; the second switch, the first drive line The control terminal of the second switch is connected to the first drive line, the first terminal of the second switch and the second terminal of the second switch are connected to the second bit line; the second switch circuit includes: a third switch, and the control terminal of the third switch is connected to the second bit line. Two drive lines, the first end of the third switch and the second end of the third switch are connected to the first line; the fourth switch, the control end of the fourth switch is connected to the second drive line, the first end of the fourth switch and the second drive line The second end of the quad switch is connected to the second bit line.

Wherein, the first sense amplifier includes: a first amplifier, the first amplifier is connected to the first bit line, the second bit line and the first enable line; the third switch circuit, the third switch circuit is connected to the first bit line, the second bit line and the first enable line; line, column selection line, first data line and second data line; fourth switch circuit, the fourth switch circuit is connected to the first bit line, the second bit line and the first precharge line.

Wherein, the second sense amplifier includes: a second amplifier, the second amplifier is connected to the first bit line, the second bit line and the second enable line; the fifth switch circuit, the fifth switch circuit is connected to the first bit line, the second bit line and the second enable line; line, column selection line, third data line and fourth data line; a sixth switch circuit, the sixth switch circuit connects the first bit line, the second bit line and the second precharge line; wherein, the first data line, the first The second data line, the third data line and the fourth data line are connected to the common data line.

Wherein, the storage module further includes: a column circuit, which is connected to the column selection line and the common data line; and a row circuit, which is connected to the first word line and the second word line.

Wherein, the row circuit further includes a word line driving circuit, and the word line driving circuit connects the first word line and the second word line.

In a second aspect, the present application provides a method for controlling a memory chip. The method for controlling a memory chip includes: writing at least part of data in the second storage array into the first storage array, so that an external device can read data from the first storage array. Write; write at least part of the data in the first storage array into the second storage array for data backup; wherein the first storage array works in the first storage mode, and the second storage array works in the second storage mode.

The beneficial effects of the present application are different from the situation in the prior art. Each storage array in the memory chip of the present application includes: a first storage array, the first storage array works in the first storage mode; the second storage array, the second storage array The array works in the second storage mode; the control circuit is connected to the first storage array and the second storage array, and the control circuit is used to write at least part of the data in the second storage array into the first storage array, so that the external device can The storage array reads and writes data; and writes at least part of the data in the first storage array into the second storage array for data backup. Specifically, the external device only reads and writes to the first storage array, so that the memory chip of the present application can have the characteristics of fast read and write speed and long service life, and the data in the first storage array can be backed up in the second storage array, It has the characteristics that data will not be lost after power failure.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, under the premise of no creative work, other drawings can also be obtained from these drawings, wherein:

FIG. 1 is a schematic structural diagram of a first embodiment of a memory chip of the present application;

Fig. 2 is the structural representation of memory module BANK in Fig. 2;

FIG. 3 is a schematic structural diagram of the first embodiment of the storage array in FIG. 2;

FIG. 4 is a schematic structural diagram of a second embodiment of the storage array in FIG. 2;

5 is a schematic diagram of the connection between the first data line, the second data line, the third data line and the fourth data line and the common data line;

6 is a schematic structural diagram of an embodiment of a word line driver circuit;

7 is a schematic flowchart of a first embodiment of a control method for a memory chip;

8 is a schematic diagram of the signal timing sequence for reading and writing to the first storage array;

Fig. 9 is the timing signal schematic diagram of step S71 in Fig. 7;

FIG. 10 is a schematic diagram of timing signals of step S72 in FIG. 7 .

Detailed ways

In order to make the technical problems solved by the present application, the technical solutions adopted and the technical effects achieved more clearly, the technical solutions of the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor a separate or alternative embodiment that is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. Furthermore, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally also includes For other steps or units inherent to these processes, methods, products or devices.

Please refer to FIG. 1 , which is a schematic structural diagram of a memory chip according to a first embodiment of the present application. Specifically, the memory chip 1 includes a plurality of memory modules BANK, and each memory module BANK is independent of each other. Please refer to FIG. 2 . FIG. 2 is a schematic structural diagram of a storage module BANK. Each storage module BANK includes a plurality of storage arrays 10 . Please refer to FIG. 3 , which is a schematic structural diagram of a storage array. Each storage array 10 includes a first storage array 11 , a second storage array 12 and a control circuit 13 . The first storage array 11 works in the first storage mode; the second storage array 12 works in the second storage mode. It can be understood that the first storage mode and the second storage mode are different. The control circuit 13 is connected to the first storage array 11 and the second storage array 12 , and the control circuit 13 is used to write at least part of the data in the second storage array 12 into the first storage array 11 , so that the external device can respond to the first storage array 11 . read and write data; and write at least part of the data in the first storage array 11 into the second storage array 12 for data backup.

Specifically, please refer to FIG. 2 , the control circuit is further connected to the column circuit COL and the XDEC circuit, which controls the word line, the sense amplifier and the data line switch through the XDEC circuit according to the row address, and also controls the signal of the column selection line CSL through COL according to the column address. and data transmission on the common data line MDQ. The XDEC circuit is a row decoder circuit.

It should be noted that the first storage array 11 is a DRAM storage array, and the second storage array 12 is a non-volatile storage array. Among them, DRAM stores information by the amount of charge on the capacitor in the storage unit, and belongs to volatile memory. The advantage is that the reading speed is fast, and the life of the storage unit is almost infinite, but the disadvantage is that the storage unit needs to be refreshed continuously, and Data will be lost after a power outage. The DRAM storage array and the non-volatile storage array are set on the memory chip at the same time. When the external device reads and writes data, the DRAM storage array can be directly read and written to inherit the fast read and write speed of the DRAM. , write at least part of the data stored in the DRAM storage array into the non-volatile storage array for data backup and avoid data loss, and after power-on, write at least part of the data backed up in the non-volatile storage array into the DRAM storage array In the array, to inherit the characteristics of non-volatile storage array that data will not be lost after power failure. In this way, the memory chip of the present application can have the characteristics of fast read and write speed, long life and no data loss after power off.

In the embodiment of the present application, the first memory array 11 and the second memory array 12 are provided in the same memory chip. Specifically, a plurality of memory chips are prepared on the same wafer, each memory chip is divided into two parts, one part prepares the first memory array 11 , and the other part prepares the second memory array 12 , that is, the first memory array 11 and the second memory array 12 are arranged on the same plane.

In one embodiment, the second storage array 12 may specifically be a ferroelectric randomaccess memory (FeRAM). The ferroelectric memory stores information through different polarization states of the ferroelectric capacitors in the storage cells, and is a kind of memory that does not store information when the power is turned off. Non-volatile memory that loses content, has the advantages of high speed, high density, low power consumption and radiation resistance. The disadvantage is that the read and write voltage is high, and the read and write speed is much slower than that of DRAM, and the life of the memory cell is limited.

In an embodiment of the present application, DRAM and FeRAM are integrated in the same chip. When the external device reads and writes data, it directly reads and writes data from the DRAM. The reading speed is fast. When the power is turned off, the data in the DRAM is written into the DRAM. In FeRAM, data will not be lost. After power-on or when a user command is received, the data in FeRAM is written into DRAM to facilitate reading and writing data from DRAM. It should be noted that, since the read and write speed of FeRAM is much slower than that of DRAM, in a preferred embodiment, the user can issue an instruction in advance to write the data of FeRAM into DRAM. Specifically, an instruction can be issued to write the FeRAM data into the DRAM during the idle time (the idle time refers to the time when the DRAM is not read or written). Compared with writing FeRAM data into DRAM when reading and writing to DRAM, the reading and writing time is greatly reduced and the reading and writing speed is improved.

In another embodiment of the present application, the second storage array 12 may also be other capacitive non-volatile memories, which are not limited herein.

Please refer to FIG. 4. FIG. 4 is a schematic structural diagram of a second embodiment of the memory array of the present application. On the basis of the first embodiment shown in FIG. 3, the memory array 10 further includes a first sense amplifier 14 and a second sense amplifier. Amplifier 15. The first sense amplifier 14 is connected to the first storage array 11 for reading and writing data of the first storage array 11 ; the second sense amplifier 15 is connected to the second storage array 12 and used for reading and writing data of the second storage array 12 .

It should be noted that the storage array 10 includes a plurality of first storage arrays 11 and a plurality of second storage arrays 12 , each first storage array 11 includes a plurality of first storage units 111 , and each second storage array 12 includes a plurality of first storage units 111 . a second storage unit 121 .

As shown in FIG. 4 , each of the first memory cells 111 includes: a first transistor Q1 and a first capacitor C1 . The control terminal of the first transistor Q1 is connected to the first word line WLA, and the first terminal of the first transistor Q1 is connected to the first bit line BL. The first end of the first capacitor C1 is connected to the second end of the first transistor Q1, and the second end of the first capacitor C1 is connected to the first control line PLA. Each second memory cell 121 includes a second transistor Q2 and a second capacitor C2, wherein the control terminal of the second transistor Q2 is connected to the second word line WLB, and the second terminal of the second transistor Q2 is connected to the second bit line BLN. The first end of the second capacitor C2 is connected to the first end of the second transistor Q2, and the second end of the second capacitor C2 is connected to the second control line PLB.

Please continue to refer to FIG. 4 , the first sense amplifier 14 includes: a first amplifier 141 , a third switch circuit 142 and a fourth switch circuit 143 . The first amplifier 141 is connected to the first bit line BL, the second bit line BLN and the first enable line SEA. The third switch circuit 142 connects the first bit line BL, the second bit line BLN, the column selection line CSL, the first data line LA and the second data line LAN.

The fourth switch circuit 143 connects the first bit line BL, the second bit line BLN and the first precharge line EQL. Specifically, the third switch circuit 142 includes a switch T1 and a switch T2, wherein the first end of the switch T1 is connected to the first bit line BL, the second end of the switch T1 is connected to the first data line LA, and the control end of the switch T1 is connected to the first data line LA. Column select line CSL. The fourth switch circuit 143 includes a switch T3 and a switch T4. The first end of the switch T3 is connected to the first bit line BL, and the control end of the switch T3 is connected to the first precharge line EQL. The first end of the switch T4 is connected to the second end of the switch T3, the second end of the switch T4 is connected to the second bit line BLN, and the control end of the switch T4 is connected to the first precharge line EQL.

The second sense amplifier 15 includes a second amplifier 151 , a fifth switch circuit 152 and a sixth switch circuit 153 . The second amplifier 151 connects the first bit line BL, the second bit line BLN and the second enable line SEB. The fifth switch circuit 152 connects the first bit line BL, the second bit line BLN, the column selection line CSL, the third data line LB and the fourth data line LBN. The sixth switch circuit 153 connects the first bit line BL, the second bit line BLN and the second precharge line RST. Specifically, the fifth switch circuit 152 includes a switch T5 and a switch T6. The first end of the switch T5 is connected to the first bit line BN, the second end of the switch T5 is connected to the third data line LB, and the control end of the switch T5 is connected to the column selection line. CSL. The first end of the switch T6 is connected to the fourth data line LBN, the second end of the switch T6 is connected to the second bit line BLN, and the control end of the switch T6 is connected to the column selection line CLS. The sixth switch circuit 153 includes a switch T7 and a switch T8. The first end of the switch T7 is connected to the first bit line BL, and the control end of the switch T7 is connected to the second precharge line RST. The first end of the switch T8 is connected to the second end of the switch T7, the second end of the switch T8 is connected to the second bit line BLN, and the control end of the switch T8 is connected to the second precharge line RST.

In an embodiment of the present application, the first data line LA, the second data line LAN, the third data line LB and the fourth data line LBN are connected to the common data line MDQ/MDQN. Please refer to FIG. 5 for details. FIG. 5 shows a part of the first sense amplifier 14 and the second sense amplifier 15 . Specifically, the first data line LA is connected to the common data line MDQ through the switch N1, and the second data line LAN is connected to the common data line MDQN through the switch N2. The first end of the switch N1 is connected to the first data line LA, the second end of the switch N1 is connected to the common data line MDQN, the control end of the switch N1 receives the signal MAS, and the signal MAS is used to control the on and off of the switch N1. The first end of the switch N2 is connected to the second data line LAN, the second end of the switch N2 is connected to the common data line MDQN, the control end of the switch N2 receives the signal MAS, and the signal MAS is used to control the on and off of the switch N2. That is, the switch N1 and the switch N2 are turned on and off at the same time. The third data line LB is connected to the common data line MDQ through the switch N3, and the fourth data line LBN is connected to the common data line MDQN through the switch N4. The first end of the switch N3 is connected to the third data line LB, the second end of the switch N3 is connected to the common data line MDQN, the control end of the switch N3 receives the signal MBS, and the signal MBS is used to control the on and off of the switch N3. The first end of the switch N4 is connected to the fourth data line LBN, the second end of the switch N4 is connected to the common data line MDQN, the control end of the switch N4 receives the signal MBS, and the signal MBS is used to control the on and off of the switch N4. That is, the switch N3 and the switch N4 are turned on and off at the same time.

Please continue to refer to FIG. 4 , the memory array 10 further includes a first switch circuit 16 and a second switch circuit 17 . The first switch circuit 16 is connected to the first sense amplifier 14 and the first storage array 11 ; the second switch circuit 17 is connected to the second sense amplifier 15 and the second storage array 12 . The first switch circuit 16 is turned on to read data from the first storage array 11 ; the second switch circuit 17 is turned on, and at least part of the data in the first storage array 11 is written into the second storage array 12 . Specifically, the first switch circuit 16 includes: a first switch M1 and a second switch M2, the control terminal of the first switch M1 is connected to the first driving line SAT, the first terminal of the first switch M2 and the second switch M2 terminal is connected to the first bit line BL. The control end of the second switch M2 is connected to the first driving line SAT, and the first end of the second switch M2 and the second end of the second switch M2 are connected to the second bit line BLN. The second switch circuit 17 includes: a third switch M3 and a fourth switch M4, the control end of the third switch M3 is connected to the second drive line SBC, the first end of the third switch M3 and the second end of the third switch M3 are connected to the A bit line BL; the control end of the fourth switch M4 is connected to the second drive line SBC, the first end of the fourth switch M4 and the second end of the fourth switch M4 are connected to the second bit line BLN.

In one embodiment, as shown in FIG. 2 , the memory array 10 further includes row circuits and column circuits 19 , wherein the row circuits connect the first word line WLA and the second word line WLB. The row circuit includes the word line driving circuit 18 and the XDEC. Please refer to FIG. 6 for details. FIG. 6 is a schematic structural diagram of an embodiment of the word line driving circuit. The word line driving circuit includes a switch A1, a switch A2 and a switch A3. One end receives the signal WLDV, the second end of the switch A1 is connected to the word line WL, the first end of the switch A2 is connected to the word line WL, the control end of the switch A2 and the control end of the switch A1 receive the global word line signal MWLN, and the first end of the switch A2 is connected to the word line WL. The two terminals are connected to the low level of the word line. The first end of the switch A3 is connected to the word line WL, and the second end of the switch A3 is connected to the low level of the word line. The control terminal of switch A3 receives the signal WLRST. When the signal MWLN is valid, WLDV is valid and WLRST is invalid, the word line WL is valid, otherwise WL is invalid and is at a low level. It should be noted that the word line WL connects the first word line WLA and the second word line WLB. The word line of the memory array 10, the first enable line of the first amplifier and the second enable line of the second amplifier are connected to the XDEC circuit, the XDEC circuit generates an enable signal, and the first enable line and the second enable line are used to connect the XDEC circuit. The enable signal is transmitted to the first amplifier and the second amplifier. The XDEC circuit is connected to the control circuit 13 and controlled by it, and the XDEC circuit is a row decoder circuit. The column circuit 19 connects the column selection line CSL and the common data line MDQ/MDQN.

The memory chip of the present application is divided into two working modes, namely, working in the first memory array 11 and working in the second memory array 12 . When working in the first memory array 11, the signal output by the first drive line SAT is valid, the switch M1 and the switch M2 are turned on, the signal output by the second drive line SBC is invalid, and the switch M3 and the switch M4 are turned off. At this time, the first memory array 11 is connected to the first bit line BL and the second bit line BLN, and the first memory cell 111 controlled by the first word line WLA can be read and written. Assuming that the first memory array 11 is a DRAM, during the activation operation, the signal output by the first precharge line EQL is invalid, the first word line WLA is turned on, and the potential of the first bit line BL is based on the level of the charge stored in the first memory cell 111 . changes somewhat, while the second bit line BLN remains unchanged as a reference potential. As the voltage difference between the first bit line BL and the second bit line BLN is established, the output signal of the first enable line SEA is valid, the first amplifier 141 starts to work, and the voltage on the first bit line BL and the second bit line BLN The difference is amplified and the write-back of the capacitance of the first storage unit 111 is completed.

When working in the second memory array 12, the signal output by the first driving line SAT is invalid, the switch M1 and the switch M2 are turned off, the signal output by the second driving line SBC is valid, and the switch M3 and the switch M4 are turned on. At this time, the second memory array 12 is connected to the first bit line BL and the second bit line BLN, and the read and write operations can be performed on the second memory cell 121 controlled by the second word line WLB. Assuming that the second memory array 12 is FeRAM, during the read operation, the signal output by the second precharge line RST is wireless, the second word line WLB is turned on, and the signal output by the second control line PLB is rising. The polarization states of the capacitors generate different amounts of polarization charges on the second bit line BLN, causing a change in its own potential, and the first bit line BL is the reference potential. As the voltage difference between the first bit line BL and the second bit line BLN is established, the signal output by the second enable line SEB is valid, the second amplifier starts to work 151, and the first bit line BL and the second bit line BLN are connected to the first bit line BL and the second bit line BLN. The voltage difference is amplified.

In an embodiment of the present application, DRAM and FeRAM are integrated in the same chip. When the external device reads and writes data, it directly reads and writes data from the DRAM. The reading speed is fast. When the power is turned off, the data in the DRAM is written into the DRAM. In FeRAM, data will not be lost. After power-on or when a user command is received, the data in FeRAM is written into DRAM to facilitate reading and writing data from DRAM. It should be noted that, since the read and write speed of FeRAM is much slower than that of DRAM, in a preferred embodiment, the user can issue an instruction in advance to write the data of FeRAM into DRAM. Specifically, an instruction can be issued to write the FeRAM data into the DRAM during the idle time (the idle time refers to the time when the DRAM is not read or written). Compared with writing FeRAM data into DRAM when reading and writing to DRAM, the reading and writing time is greatly reduced and the reading and writing speed is improved.

Please refer to FIG. 7 , which is a schematic flowchart of a first embodiment of a method for controlling a memory chip according to the present invention, which specifically includes:

Step S71: Write at least part of the data in the second storage array into the first storage array, so that the external device can read and write data to the first storage array.

Specifically, the first storage array works in the first storage mode, and the second storage array works in the second storage mode.

The control method of the present application further includes reading and writing data to the first storage array. The first memory array may be a DRAM. That is, data read and write to the first storage array is to read and write data to the DRAM, which has the advantages of fast read and write speed and long life of the capacitor.

At this time, please refer to FIG. 8 , which is a timing diagram of signals for reading and writing to the first memory array. The signal output by the first drive line SAT is valid, the switch M1 and the switch M2 are turned on, and the first storage array and the first sense amplifier are turned on; the signal output by the second drive line SBC is invalid, the switch M3 and the switch M4 are turned off, and the first storage array is turned on. The second memory array is disconnected from the second sense amplifier. Receive read and write commands, activate the selected page according to the row address in the read and write commands, including:

In the stage t1, the signal output by the first precharge line EQL is valid, the switch T3 and the switch T4 are turned on, and the first bit line BL and the second bit line BLN are connected to the reference potential.

In the t2 stage, the signal output by the first precharge line EQL is invalid, the first word line WLA is turned on, the potential of the first bit line BL changes according to the amount of stored charge in the first memory cell, and the second bit line BLN is used as a reference The potential remains unchanged.

In the stage t3, as the voltage difference between the first bit line BL and the second bit line BLN is established, the signal output by the first enable line SEA is valid. The first amplifier starts to work, amplifies the voltage difference between the first bit line BL and the second bit line BLN, and completes the write-back of the capacitance in the first memory cell. At this time, the first amplifier acts as the data buffer of the selected page. Select a specific first amplifier according to the column address in the read and write command to read and write data, which specifically includes: the signal MSA is valid, the switch N1 and the switch N2 are turned on, the first data line LA of the first amplifier and the The two data lines LAN are connected to the common data line MDQ/MDQN through switches N1 and N2, the signal output by the column selection first CSL is valid, the switches T1 and T2 are turned on, and the selected first amplifier is connected to the first amplifier through switches T1 and T2. The data line LA and the second data line LAN, the row circuit accesses the data in the first amplifier through the common data line MDQ/MDQN, the first data line LA and the second data line LAN.

In stage t4, after the first amplifier completes data transmission and write-back, the signal output by the first enable line SEA is invalid, the signal output by the first precharge line EQL is valid, the first amplifier, the first bit line BL and the second The bit line BLN is reset to the initial state.

When powered on, or the user controls to write at least part of the data in the second storage array into the first storage array, so that the external device can read and write to the first storage array. Specifically, this step is completed by the read operation of the second storage array and the write operation of the first storage array. For details, please refer to FIG. 9 , which is a signal timing diagram of step S71 . The first is the read operation of the second storage array. During the read operation of the second storage array, the signal output by the first drive line SAT is invalid, the switch M1 and the switch M2 are turned off, and the first sense amplifier is disconnected from the first storage array. ; The signal output by the second drive line SBC is invalid, the switch M3 and the switch M4 are turned on, and the second sense amplifier is connected to the second storage array. Specifically include:

In the t1 stage, the signal output by the second precharge line RST is valid, the first bit line BL and the second bit line BLN are reset to a low level, and then RST is invalid.

In the t2 stage, the second word line WLB is turned on, the signal output by the second control line PLB rises, and the second memory cell generates different amounts of polarization charges to the second bit line BLN according to the polarization state of the ferroelectric capacitor, causing itself The potential changes, and the first bit line BL is the reference potential, and the voltage difference between the first bit line BL and the second bit line BLN is established.

In stage t3, the signal output by the second enable line SEB is valid, and the second amplifier starts to work to amplify the voltage difference between the first bit line BL and the second bit line BLN.

In stage t4, the signal output by the second control line PLB drops, and if the signal output by the first bit line BL is at a high level, the polarization direction of the ferroelectric capacitor in the second memory cell is rewritten, which is recorded as data "1" ; If the signal output by the first bit line BL is at a low level, the polarization direction of the ferroelectric capacitor in the second storage unit remains unchanged, and is still data "0".

In stage t5, the second word line WLB is turned off, and the write-back of the second memory array is completed. At this time, the second amplifier is still turned on, and the level of the first bit line indicates corresponding data "0" and "1".

During the write operation of the first storage array, it specifically includes:

In stage t6, the first word line WLA is turned on, the first memory cell of the first memory array is connected to the first bit line BL, and the capacitor in the first memory cell is charged according to the level of the first bit line BL.

In stage t7, the first word line WLA is turned off, the write-back of the first memory array is completed, then the signal output by the second enable line SEB is invalid, the second amplifier is turned off, the signal output by the second precharge line RST is valid, and the first The two amplifiers, the first bit line BL and the second bit line BLN are reset to the initial state.

Step S72: Write at least part of the data in the first storage array into the second storage array for data backup.

Writing at least part of the data in the first storage array into the second storage array for data backup. Specifically, in an embodiment, after the power is turned off, or under user control, at least part of the data in the first storage array is written into the second storage array for data backup. Writing at least part of the data in the first storage array into the second storage array includes a read operation of the first storage array and a write operation of the second storage array.

In the read operation of the first memory array, data is first read from the memory cells of the first memory array to the first amplifier. During this process, the signal output by the first drive line SAT is valid, and the switch M1 and the switch M2 are turned on. , the first storage array is turned on with the first sense amplifier; the signal output by the second drive line SBC is invalid, the switch M3 and the switch M4 are turned off, and the second storage array is disconnected from the second sense amplifier. Please refer to FIG. 10 for details. FIG. 10 is a signal timing diagram of step S72, which specifically includes:

In the stage t1, the signal output by the first precharge line EQL is valid, the switch T3 and the switch T4 are turned on, and the first bit line BL and the second bit line BLN are connected to the reference potential.

In stage t2, the signal output by the first precharge line EQL is invalid, the row circuit activates the selected first word line WLA according to the row address, and the potential of the first bit line BL changes according to the amount of charge stored in the first memory cell, The second bit line BLN is used as a reference voltage to keep the potential unchanged.

In the stage t3, with the establishment of the voltage difference between the first bit line BL and the second bit line BLN, the signal output by the first enable line SEA is valid. The first amplifier starts to work, amplifies the voltage difference between the first bit line BL and the second bit line BLN and completes the write-back of the capacitance of the first memory cell, and then the first word line WLA is turned off.

Then, the data is moved from the first amplifier to the second amplifier. During this process, the signal output by the first drive line SAT is invalid, the switch M1 and the switch M2 are closed, and the first storage array is disconnected from the first sense amplifier; the third The signals output by the two drive lines SBC are valid, the switch M3 and the switch M4 are turned on, and the second storage array and the second sense amplifier are turned on.

In stage t4, the signal output by the first enable line SEA is invalid, the first amplifier is turned off, the first bit line BL and the second bit line BLN are disconnected from the first amplifier and turned on with the second amplifier. At this time, the first bit line BL and the second bit line BLN still maintain a high level or a low level. The signal output by the second enable line SEB is valid, the second amplifier starts to work, realizes the movement of data, and further amplifies the voltage difference between the first bit line BL and the second bit line BLN to the level required for the operation of the second memory array. high and low level.

Finally, write data from the second amplifier to the second storage array, including:

In the t5 stage, the second word line WLB is turned on, and the signal output by the second control line PLB rises. If the first bit line BL is at a low level, the polarization direction of the ferroelectric capacitor in the second memory cell is changed, which is recorded as "data" 0".

In stage t6, the signal output by the second control line PLB drops, and if the first bit line BL is at a high level, the polarization direction of the ferroelectric capacitor in the second memory cell is changed to another direction, which is marked as "1".

In stage t7, the second word line WLB is turned off, the signal output by the second enable line SEB is invalid, the second amplifier is turned off, the signal output by the second precharge line RST is valid, and the second amplifier, the first bit line BL and the first The two bit lines BLN are reset to the initial state.

The control method for a memory chip proposed in this application combines two different modes of memory arrays. On the one hand, it has the characteristics of low power consumption, which is embodied in that it does not need to be refreshed after data is stored in the second memory array; On the one hand, it has the characteristics of fast read and write speed, which is manifested in that the read and write speed of the first storage array is faster than that of the second storage array; Completed in the working mode of the first storage array, the capacitor of the second storage array will not be damaged, and a service life comparable to that of the first storage array is achieved; The data in the first storage array can still be stored in the second storage array, and then restored to the first storage array after power-on. Further, it also has the advantages of low latency and high bandwidth. Low latency is embodied in that the operations of the first storage array and the second storage array are automatically and continuously completed inside the memory chip, without user intervention, and the latency is low. The high bandwidth is embodied in that data is moved between the first amplifier of the first storage array and the second amplifier of the second storage array in units of pages, and only one operation is required to complete the movement of all data of the entire page.

The above are only the embodiments of the present application, and are not intended to limit the scope of the patent of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present application, or directly or indirectly applied in other related technical fields, All are similarly included in the scope of patent protection of the present application.

Claims (10)

1. A memory chip, comprising: a plurality of memory modules, each memory module comprising a plurality of memory arrays, each of the memory arrays comprising: a first storage array, the first storage array operates in a first storage mode; a second storage array, the second storage array operates in a second storage mode; A control circuit is connected to the first storage array and the second storage array, and the control circuit is used to write at least part of the data in the second storage array into the first storage array, so that an external device can The first storage array reads and writes data; and at least part of the data in the first storage array is written into the second storage array for data backup. 2. The memory chip according to claim 1, wherein the memory array comprises: a first sense amplifier, connected to the first storage array, and used for data reading and writing of the first storage array; The second sense amplifier is connected to the second storage array, and is used for reading and writing data of the second storage array. 3. The memory chip according to claim 2, characterized in that, The first storage array includes: a plurality of first storage units, and each of the first storage units includes: a first transistor, the control end of the first transistor is connected to the first word line, and the first end of the first transistor is connected to the first bit line; a first capacitor, the first end of the first capacitor is connected to the second end of the first transistor, and the second end of the first capacitor is connected to the first control line; The second storage array includes: a plurality of second storage units, each of the second storage units includes: a second transistor, the control end of the second transistor is connected to the second word line, and the second end of the second transistor is connected to the second bit line; The second capacitor, the first end of the second capacitor is connected to the first end of the second transistor, and the second end of the second capacitor is connected to the second control line. 4. The memory chip according to claim 3, wherein the memory array further comprises: a first switch circuit, the first switch circuit is connected between the first sense amplifier and the first storage array; a second switch circuit, the second switch circuit is connected between the second sense amplifier and the second storage array; The first switch circuit is turned on to read data from the first storage array; the second switch circuit is turned on, and at least part of the data in the first storage array is written into the second storage array. 5. The memory chip according to claim 4, wherein the first switch circuit comprises: a first switch, the control end of the first switch is connected to the first drive line, and the first end of the first switch and the second end of the first switch are connected to the first bit line; a second switch, the control end of the second switch is connected to the first drive line, and the first end of the second switch and the second end of the second switch are connected to the second bit line; The second switch circuit includes: a third switch, the control end of the third switch is connected to the second drive line, the first end of the third switch and the second end of the third switch are connected to the first line; a fourth switch, the control end of the fourth switch is connected to the second drive line, and the first end of the fourth switch and the second end of the fourth switch are connected to the second bit line. 6. The memory chip according to claim 5, wherein the first sense amplifier comprises: a first amplifier, the first amplifier is connected to the first bit line, the second bit line and the first enable line; a third switch circuit, the third switch circuit is connected to the first bit line, the second bit line, the column select line, the first data line and the second data line; a fourth switch circuit, the fourth switch circuit is connected to the first bit line, the second bit line and the first precharge line. 7. The memory chip according to claim 6, wherein the second sense amplifier comprises: a second amplifier, the second amplifier is connected to the first bit line, the second bit line and the second enable line; a fifth switch circuit, the fifth switch circuit is connected to the first bit line, the second bit line, the column selection line, the third data line and the fourth data line; a sixth switch circuit, the sixth switch circuit is connected to the first bit line, the second bit line and the second precharge line; Wherein, the first data line, the second data line, the third data line and the fourth data line are connected to a common data line. 8. The memory chip according to claim 6 or 7, wherein the memory module further comprises: a column circuit connecting the column select line and the common data line; and a row circuit connecting the first word line and the second word line. 9 . The memory chip of claim 8 , wherein the row circuit further comprises a word line driving circuit, and the word line driving circuit connects the first word line and the second word line. 10 . 10. A control method for a memory chip, wherein the method comprises: writing at least part of the data in the second storage array into the first storage array, so that an external device can read and write data to the first storage array; writing at least part of the data in the first storage array into the second storage array for data backup; Wherein, the first storage array works in the first storage mode, and the second storage array works in the second storage mode.

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