CN115168126A - Channel characteristic testing method and system, electronic device and readable storage medium - Google Patents
Channel characteristic testing method and system, electronic device and readable storage medium Download PDFInfo
- Publication number
- CN115168126A CN115168126A CN202210901175.4A CN202210901175A CN115168126A CN 115168126 A CN115168126 A CN 115168126A CN 202210901175 A CN202210901175 A CN 202210901175A CN 115168126 A CN115168126 A CN 115168126A
- Authority
- CN
- China
- Prior art keywords
- test
- line
- communicator
- connector
- communication
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention relates to the technical field of communication test, and discloses a channel characteristic test method, a system, electronic equipment and a readable storage medium.
Description
Technical Field
The present invention relates to the field of communication testing technologies, and in particular, to a channel characteristic testing method, a channel characteristic testing system, an electronic device, and a readable storage medium.
Background
At present, with the rapid development of the electronic industry, a serial interface with higher speed gradually replaces a traditional parallel interface, and is widely applied to video display, digital image and data transmission systems of automobiles. Since the functional safety and information safety of the automobile, which are one of the most critical indexes of the automobile, are directly affected by the transmission reliability of the serial interface, it is very important to test the serial interface. And because the dynamic test of the high-speed signal is unpredictable, the signal is statically tested in many cases, the obtained channel characteristic parameters do not consider the specific form of the interconnection structure, the interconnection structure is used as a black box, all the behavior characteristics of the interconnection structure can be completely described only through the parameters at the port, and the method is widely applied in the high-frequency field and is seen to become an important tool essential for signal integrity analysis and design.
The existing static test instrument needs to be directly connected with a PIN foot of a communication chip through an instrument coaxial line so as to perform static test on signals of the communication chip, but because a bonding pad of the chip is small, the chip is connected through a professional clamp, and a connector matched with the instrument coaxial line cannot be welded, so that tools needed by channel characteristic test are numerous, and the static test efficiency is reduced.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended to be a prelude to the more detailed description that is presented later.
In view of the above drawbacks of the prior art, the present invention discloses a method, a system, an electronic device and a readable storage medium for testing channel characteristics, so as to simplify the tool for testing channel characteristics and improve the efficiency of testing channel characteristics.
The invention discloses a channel characteristic testing method, which comprises the following steps: the method comprises the steps of obtaining a first communicator and a second communicator, wherein the first communicator comprises a first transmission line and a first communication chip, the first transmission line is used for establishing an interconnection channel between the first communicator and the second communicator, and the first communication chip is used for communicating with the second communicator through the interconnection channel; performing line analysis on the first transmission line according to a preset line parameter type to obtain a first line parameter corresponding to the first transmission line, and establishing a first test line in the first communicator according to the first line parameter, wherein a first test interface is arranged at a first end of the first test line; connecting a second end of the first test line to the second communicator to establish a test channel between the first communicator and the second communicator; and performing channel characteristic test on the test channel through the first test interface to obtain channel characteristic parameters corresponding to the test channel, and determining the channel characteristic parameters as channel characteristic test results of the interconnection channels.
Optionally, an interconnection channel between the first communicator and the second communicator is established by: the first communicator further comprises a first communication connector, wherein the communication connector is connected with the first communication chip through the first transmission line; the second communicator comprises a second communication connector, a second transmission line and a second communication chip, wherein the second communication connector is connected with the second communication chip through the second transmission line; and arranging a communication wiring harness between the first communication connector and the second communication connector, so that the first communication chip is connected with the second communication chip through the first transmission line, the first communication connector, the communication wiring harness, the second communication connector and the second transmission line in sequence.
Optionally, after the first communicator and the second communicator are obtained, before the second end of the first test line is connected to the second communicator, the method further includes: performing line analysis on the second transmission line according to a preset line parameter type to obtain a second line parameter corresponding to the second transmission line; and establishing a second test line in the second communicator according to the second line parameter, wherein a second test interface is arranged at the first end of the second test line.
Optionally, connecting the second end of the first test line to the second communicator, comprising: arranging a first test connector at the second end of the first test line, and arranging a second test connector at the second end of the second test line; and arranging a test wire harness between the first test connector and the second test connector, so that the first test interface is connected with the second test interface through the first test wire, the first test connector, the test wire harness, the second test connector and the second test wire in sequence.
Optionally, the method further comprises at least one of: arranging a first circuit board in the first communicator, wherein the first circuit board is used for loading the first communication chip, the first transmission line, the first communication connector, the first test interface, the first test line and the first test connector; and arranging a second circuit board in the second communicator, wherein the second circuit board is used for loading the second communication chip, the second transmission line, the second communication connector, the second test interface, the second test line and the second test connector.
Optionally, the first test interface and/or the second test interface comprises an IPEX connector.
Optionally, the line parameter type includes one or more of a reference layer line, a corresponding layer line, a transmission line length, a transmission line width, a transmission line via number, a transmission line via position, and an overall line shape.
The invention discloses a channel characteristic test system, comprising: the system comprises an acquisition module, a first communication module and a second communication module, wherein the first communication module comprises a first transmission line and a first communication chip, the first transmission line is used for establishing an interconnection channel between the first communication module and the second communication module, and the first communication chip is used for communicating with the second communication module through the interconnection channel; the test line establishing module is used for performing line analysis on the first transmission line according to a preset line parameter type to obtain a first line parameter corresponding to the first transmission line, and establishing a first test line in the first communicator according to the first line parameter, wherein a first end of the first test line is provided with a first test interface; a test channel establishing module, configured to connect a second end of the first test line to the second communicator, so as to establish a test channel between the first communicator and the second communicator; and the test module is used for carrying out channel characteristic test on the test channel through the first test interface to obtain channel characteristic parameters corresponding to the test channel, and determining the channel characteristic parameters as channel characteristic test results of the interconnection channels.
The invention discloses an electronic device, comprising: a processor and a memory; the memory is used for storing computer programs, and the processor is used for executing the computer programs stored by the memory so as to enable the electronic equipment to execute the method.
The invention discloses a computer-readable storage medium, on which a computer program is stored: which when executed by a processor implements the method described above.
The invention has the beneficial effects that:
the method comprises the steps of carrying out line analysis on a first transmission line in a first communicator to obtain first line parameters by obtaining the first communicator and a second communicator, establishing a first test line in the first communicator according to the first line parameters, connecting a second end of the first test line with the second communicator to establish a test channel between the first communicator and the second communicator, and carrying out channel characteristic test on the test channel through a first test interface to obtain channel characteristic parameters. Like this, replace first transmission line through first test wire, establish the test passageway between first communicator and the second communicator to set up first test interface at the first end of first test wire, make test equipment carry out the channel characteristic test through first test interface, compare in carrying out the centre gripping test through professional anchor clamps, simplified the instrument of channel characteristic test, improve the efficiency of testing of channel characteristic.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
FIG. 1 is a schematic diagram of a communication device connection according to an embodiment of the present invention;
FIG. 2 is a flow chart of a channel characteristic testing method according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a channel characteristic testing system for implementing a channel characteristic testing method according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of another channel characteristic testing system according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an electronic device in an embodiment of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that, in the following embodiments and examples, subsamples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In the following description, numerous details are set forth to provide a more thorough explanation of embodiments of the present invention, however, it will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details, and in other embodiments, well-known structures and devices are shown in block diagram form, rather than in detail, to avoid obscuring embodiments of the present invention.
The terms "first," "second," and the like in the description and in the claims, and the above-described drawings of embodiments of the present disclosure, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged as appropriate for the embodiments of the disclosure described herein. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
The term "plurality" means two or more, unless otherwise specified.
In the embodiment of the present disclosure, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. For example, a and/or B, represents: a or B, or A and B.
It should be noted that the first communicator and the second communicator in the embodiment of the present disclosure are established based on the Serdes interface technology. The Serdes interface technology adopts low-voltage differential signals for data transmission, is a time division multiplexing and point-to-point communication technology, has the characteristics of low power consumption, strong anti-interference capability, high speed and the like, is the mainstream of a high-speed serial interface, and is widely applied to internal communication of automobiles. When high-speed signals are transmitted through the Serdes interface, technicians need to reasonably design a circuit and test the signal integrity of the circuit through a communication test so as to fully know the performance of the Serdes interface and determine the reliability margin of data transmission.
As shown in fig. 1, communicators established based on Serdes interface technology include a Serializer and a Deserializer, and the connection modes between them generally include three types, i.e., PCB + PCB, PCB + connector + PCB, or PCB + connector + harness + connector + PCB.
Based on the above connection method, the communication test corresponding to the Serdes interface technology includes a dynamic test and a static test, the dynamic test mainly tests the detailed performance of the signals in the interconnection channel, and is usually evaluated by using an eye diagram, but if the signal rate reaches a certain rate, even if the high-speed serial bus is configured with an equalizer for signal equalization, the eye diagram of the signals received by the receiving end is not open, so that the signals become undetectable, and at this time, the static test is very important.
The static test mainly tests physical characteristics of the interconnection channel, including transmission lines, vias, connectors, cables, and the like on the interconnection channel, so as to obtain static test parameters representing the physical characteristics of the interconnection channel, including TDR (Time domain reflectometry) impedance and S parameters (scattering parameters), where the TDR impedance may be obtained through S parameter conversion. Generally, equipment manufacturers corresponding to the wire harness, the connector and the PCB board provide single static test parameters, but after a plurality of single equipment are connected, the single static test parameters cannot represent the overall performance of the interconnection channel due to the problems that the contact matching of the connector is unreliable, the simple sum of the single loss does not represent the overall loss of the interconnection channel, the provided report is not completely accurate, and the like, so that the comprehensive evaluation of the interconnection channel formed by the PCB board, the connector and the wire harness is necessary.
The interconnection channel is usually tested statically by a testing instrument, and specifically, SMA (miniature a connector) or a dedicated adapter is used as a coaxial line of the testing instrument to connect with a Test object (DUT). However, the transmission line on the PCB is led out by the pad corresponding to the PIN of the chip, and there is no connector connected to the coaxial line, and in addition, since the chip pad is smaller, the connector matched with the coaxial cable cannot be soldered, and needs to be connected by a professional clamp, resulting in numerous testing tools and complicated testing steps, and reducing the testing efficiency of the channel characteristics.
Based on the above, with reference to fig. 2, an embodiment of the present disclosure provides a channel characteristic testing method, including:
step S201, a first communicator and a second communicator are obtained;
the first communicator comprises a first transmission line and a first communication chip, the first transmission line is used for establishing an interconnection channel between the first communicator and the second communicator, and the first communication chip is used for communicating with the second communicator through the interconnection channel;
step S202, performing line analysis on the first transmission line according to a preset line parameter type to obtain a first line parameter corresponding to the first transmission line, and establishing a first test line in the first communicator according to the first line parameter;
the first end of the first test line is provided with a first test interface;
step S203, connecting the second end of the first test line with the second communicator to establish a test channel between the first communicator and the second communicator;
step S204, channel characteristic test is carried out on the test channel through the first test interface to obtain channel characteristic parameters corresponding to the test channel, and the channel characteristic parameters are determined as channel characteristic test results of the mutually communicated channels.
By adopting the channel characteristic testing method provided by the embodiment of the disclosure, the first line parameter is obtained by obtaining the first communicator and the second communicator, the first transmission line in the first communicator is subjected to line analysis, the first testing line is established in the first communicator according to the first line parameter, the second end of the first testing line is further connected with the second communicator so as to establish the testing channel between the first communicator and the second communicator, and the channel characteristic testing is performed on the testing channel through the first testing interface so as to obtain the channel characteristic parameter. Like this, replace first transmission line through first test wire, establish the test passageway between first communicator and the second communicator to set up first test interface at the first end of first test wire, make test equipment carry out the channel characteristic test through first test interface, compare in carrying out the centre gripping test through professional anchor clamps, simplified the instrument of channel characteristic test, improve the efficiency of testing of channel characteristic. And, replace first transmission line through first test wire, need not set up first communicator and just can carry out different sample tests, reduced the expense of drawing a design to reduce test cost.
Optionally, the interconnection channel between the first communicator and the second communicator is established by: the first communicator also comprises a first communication connector, wherein the communication connector is connected with the first communication chip through a first transmission line; the second communicator comprises a second communication connector, a second transmission line and a second communication chip, wherein the second communication connector is connected with the second communication chip through the second transmission line; and arranging a communication wiring harness between the first communication connector and the second communication connector, so that the first communication chip is connected with the second communication chip through the first transmission line, the first communication connector, the communication wiring harness, the second communication connector and the second transmission line in sequence.
Optionally, after the first communicator and the second communicator are obtained, before the second end of the first test line is connected to the second communicator, the method further includes: performing line analysis on the second transmission line according to a preset line parameter type to obtain a second line parameter corresponding to the second transmission line; and establishing a second test line in the second communicator according to the second line parameter, wherein a first end of the second test line is provided with a second test interface.
Optionally, connecting the second end of the first test line to the second communicator, comprises: arranging a first test connector at the second end of the first test line, and arranging a second test connector at the second end of the second test line; and arranging a test wire harness between the first test connector and the second test connector, so that the first test interface is connected with the second test interface sequentially through the first test wire, the first test connector, the test wire harness, the second test connector and the second test wire.
Optionally, after disposing the test harness between the first test connector and the second test connector, the method further comprises: and performing channel characteristic test on the test channel through the second test interface to obtain channel characteristic parameters corresponding to the test channel, and determining the channel characteristic parameters as channel characteristic test results of the mutually communicated channels.
Optionally, the method further comprises at least one of: arranging a first circuit board in the first communicator, wherein the first circuit board is used for loading a first communication chip, a first transmission line, a first communication connector, a first test interface, a first test line and a first test connector; and arranging a second circuit board in the second communicator, wherein the second circuit board is used for loading a second communication chip, a second transmission line, a second communication connector, a second test interface, a second test line and a second test connector.
In some embodiments, after a communicator Main board (M-PCB, main-PCB) is designed, a Test Main board (T-PCB) specially used for testing channel characteristic parameters is added to a board edge of the communicator Main board, wherein the communicator Main board comprises a first communication chip, a first transmission line and a first communication connector, and the Test Main board comprises a first Test interface, a first Test line and a first Test connector; the test mainboard is spliced on the communicator mainboard, or the test mainboard and the communicator mainboard are arranged on the same circuit board.
In some embodiments, the channel characteristic parameters include TDR impedance and S parameters, and the S parameters include S11 parameters, S21 parameters, S12 parameters, and S22 parameters.
Therefore, the test mainboard and the communicator mainboard are arranged on the same circuit board, namely, the test mainboard and the communicator mainboard are processed by adopting the same circuit board process, so that the lamination thickness, the dielectric constant Dk, the dielectric loss Df, the solder resist material, the thickness, the etching process and the like after the PCB is pressed are all kept consistent, the channel characteristic performance of the test mainboard and the communicator mainboard is unified, and the test accuracy is improved.
Optionally, the first test interface and/or the second test interface comprises an IPEX connector.
Therefore, the IPEX connector is a microminiature coaxial cable connector, the first test interface and/or the second test interface are/is connected with a static test instrument or a network analyzer through the IPEX connector and a feeder line patch cord (namely an SMA-to-IPEX patch cord), so that the test is convenient, meanwhile, the size of a pad of the IPEX connector is small and is close to that of a chip pad, an IPEX connection area is fully shielded, and the IPEX can ensure that the impedance at the joint of the IPEX connector and a T-PCB is continuous and has no reflection, so that the attenuation of the whole interconnection channel is minimum, and the test accuracy is improved.
Optionally, the line parameter types include one or more of a reference layer line, a corresponding layer line, a transmission line length, a transmission line width, a transmission line via number, a transmission line via position, and an overall line shape.
Referring to fig. 3, an embodiment of the present disclosure provides a channel characteristic testing system for implementing a channel characteristic testing method, including a first communicator 301 and a second communicator 302; the first communicator 301 includes a first communication chip 3011, a first transmission line 3012, a first communication connector 3013, a first test interface 3014, a first test line 3015, a first test connector 3016, and a first circuit board 3017; the second communicator 302 includes a second communication chip 3021, a second transmission line 3022, a second communication connector 3023, a second test interface 3024, a second test line 3025, a second test connector 3026, and a second circuit board 3027; connecting a first communication chip with a second communication chip through a first transmission line, a first communication connector, a communication harness, a second communication connector and a second transmission line in sequence to serve as an interconnection channel; connecting a first test interface with a second test interface as a test channel through a first test wire, a first test connector, a test wire harness, a second test connector and a second test wire in sequence; the first test interface and/or the second test interface are/is used for carrying out channel characteristic test on the test channel to obtain channel characteristic parameters corresponding to the test channel, and the channel characteristic parameters are determined as channel characteristic test results of the mutually communicated channels.
By adopting the channel characteristic testing system for implementing the channel characteristic testing method provided by the embodiment of the disclosure, by obtaining the first communicator and the second communicator, the first transmission line in the first communicator is subjected to line analysis to obtain the first line parameter, the first testing line is established in the first communicator according to the first line parameter, and then the second end of the first testing line is connected with the second communicator to establish the testing channel between the first communicator and the second communicator, and the testing channel is subjected to channel characteristic testing through the first testing interface to obtain the channel characteristic parameter, so that the channel characteristic testing system has the advantages that:
firstly, a first transmission line is replaced by a first test line, a test channel between a first communicator and a second communicator is established, and a first test interface is arranged at the first end of the first test line, so that the test equipment can carry out channel characteristic test through the first test interface, compared with the clamping test through a professional clamp, the tool for channel characteristic test is simplified, and the test efficiency of channel characteristics is improved;
secondly, the first testing line replaces the first transmission line, different sample tests can be carried out without arranging a first communicator, and the proofing cost is reduced, so that the testing cost is reduced;
thirdly, the test mainboard and the communicator mainboard are arranged on the same circuit board, namely, the test mainboard and the communicator mainboard are processed by adopting the same circuit board process, so that the lamination thickness, the dielectric constant Dk, the dielectric loss Df, the solder resist material and thickness, the etching process and the like after the PCB is laminated are all kept consistent, the channel characteristic performance of the test mainboard and the communicator mainboard is unified, and the test accuracy is improved;
fourthly, as the IPEX connector is a microminiature coaxial cable connector, the first test interface and/or the second test interface are/is connected with a static test instrument or a network analyzer through the IPEX connector and the feeder line patch cord, so that the test is convenient;
and fifthly, the size of a bonding pad of the IPEX connector is smaller and is close to that of a bonding pad of a chip, an IPEX connection area is fully shielded, and the IPEX can ensure that the impedance of a joint of the IPEX connector and the T-PCB is continuous and has no reflection, so that the attenuation of the whole interconnection channel is minimum, and the test accuracy is improved.
As shown in fig. 4, an embodiment of the present disclosure provides a channel characteristic testing system, which includes an obtaining module 401, a test line establishing module 402, a test channel establishing module 403, and a test module 404. The obtaining module 401 is configured to obtain a first communicator and a second communicator, where the first communicator includes a first transmission line and a first communication chip, the first transmission line is used to establish an interconnection channel between the first communicator and the second communicator, and the first communication chip is used to communicate with the second communicator through the interconnection channel; the test line establishing module 402 is configured to perform line analysis on the first transmission line according to a preset line parameter type to obtain a first line parameter corresponding to the first transmission line, and establish a first test line in the first communicator according to the first line parameter, where a first end of the first test line is provided with a first test interface; the test channel establishing module 403 is configured to connect a second end of the first test line to the second communicator, so as to establish a test channel between the first communicator and the second communicator; the test module 404 is configured to perform a channel characteristic test on the test channel through the first test interface to obtain a channel characteristic parameter corresponding to the test channel, and determine the channel characteristic parameter as a channel characteristic test result of the mutually connected channels.
By adopting the channel characteristic testing system provided by the embodiment of the disclosure, the first line parameter is obtained by performing line analysis on the first transmission line in the first communicator by obtaining the first communicator and the second communicator, the first testing line is established in the first communicator according to the first line parameter, and then the second end of the first testing line is connected with the second communicator so as to establish the testing channel between the first communicator and the second communicator, and the channel characteristic testing is performed on the testing channel through the first testing interface so as to obtain the channel characteristic parameter. Like this, replace first transmission line through first test wire, establish the test passageway between first communicator and the second communicator to set up first test interface at the first end of first test wire, make test equipment carry out the channel characteristic test through first test interface, compare in carrying out the centre gripping test through professional anchor clamps, simplified the instrument of channel characteristic test, improve the efficiency of testing of channel characteristic. And, replace first transmission line through first test wire, need not set up first communicator and just can carry out different sample tests, reduced the expense of drawing a design to reduce test cost.
FIG. 5 illustrates a schematic structural diagram of a computer system suitable for use to implement the electronic device of the embodiments of the subject application. It should be noted that the computer system 500 of the electronic device shown in fig. 5 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present application.
As shown in fig. 5, the computer system 500 includes a Central Processing Unit (CPU) 501, which can perform various appropriate actions and processes, such as executing the methods in the above-described embodiments, according to a program stored in a Read-Only Memory (ROM) 502 or a program loaded from a storage section 508 into a Random Access Memory (RAM) 503. In the RAM 503, various programs and data necessary for system operation are also stored. The CPU 501, ROM 502, and RAM 503 are connected to each other via a bus 504. An Input/Output (I/O) interface 505 is also connected to bus 504.
The following components are connected to the I/O interface 505: an input portion 506 including a keyboard, a mouse, and the like; an output section 507 including a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, a speaker, and the like; a storage portion 508 including a hard disk and the like; and a communication section 509 including a Network interface card such as a LAN (Local Area Network) card, a modem, or the like. The communication section 509 performs communication processing via a network such as the internet. The driver 510 is also connected to the I/O interface 505 as necessary. A removable medium 511 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 510 as necessary, so that a computer program read out therefrom is mounted into the storage section 508 as necessary.
In particular, according to embodiments of the application, the processes described above with reference to the flow diagrams may be implemented as computer software programs. For example, embodiments of the present application include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising a computer program for performing the method illustrated by the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network through the communication section 509, and/or installed from the removable medium 511. The computer program executes various functions defined in the system of the present application when executed by a Central Processing Unit (CPU) 501.
It should be noted that the computer readable media shown in the embodiments of the present application may be computer readable signal media or computer readable storage media or any combination of the two. The computer readable storage medium may be, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a Read-Only Memory (ROM), an Erasable Programmable Read-Only Memory (EPROM), a flash Memory, an optical fiber, a portable Compact Disc Read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present application, a computer-readable signal medium may comprise a propagated data signal with a computer-readable computer program embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. The computer program embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the foregoing.
Embodiments of the present disclosure also provide a computer-readable storage medium on which a computer program is stored, which when executed by a processor implements any of the methods in the embodiments.
The computer-readable storage medium in the embodiments of the present disclosure may be understood by those skilled in the art as follows: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with a computer program. The aforementioned computer program may be stored in a computer readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
The electronic device disclosed in this embodiment includes a processor, a memory, a transceiver, and a communication interface, where the memory and the communication interface are connected to the processor and the transceiver and perform mutual communication, the memory is used to store a computer program, the communication interface is used to perform communication, and the processor and the transceiver are used to run the computer program, so that the electronic device performs the steps of the above method.
In this embodiment, the Memory may include a Random Access Memory (RAM), and may also include a non-volatile Memory (non-volatile Memory), such as at least one disk Memory.
The Processor may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, or a discrete hardware component.
The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and subsamples of some embodiments may be included in or substituted for portions and subsamples of other embodiments. Furthermore, the words used in the specification are words of description for example only and are not limiting upon the claims. As used in the description of the embodiments and the claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, the terms "comprises," "comprising," and variations thereof, when used in this application, specify the presence of stated sub-samples, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other sub-samples, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising one of 8230" does not exclude the presence of additional identical elements in the process, method or device comprising the element. In this document, each embodiment may be described with emphasis on differences from other embodiments, and the same and similar parts between the respective embodiments may be referred to each other. For methods, products, etc. of the embodiment disclosure, reference may be made to the description of the method section for relevance if it corresponds to the method section of the embodiment disclosure.
Those of skill in the art would appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software may depend upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments. It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the apparatus and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the embodiments disclosed herein, the disclosed methods, products (including but not limited to devices, apparatuses, etc.) may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit may be merely a division of a logical function, and an actual implementation may have another division, for example, a plurality of units or components may be combined or may be integrated into another system, or some subsamples may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to implement the present embodiment. In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two sequential operations or steps may in fact be executed substantially concurrently, or they may sometimes be executed in the reverse order, depending upon the functionality involved. Each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Claims (10)
1. A channel characteristic testing method, comprising:
the method comprises the steps of obtaining a first communicator and a second communicator, wherein the first communicator comprises a first transmission line and a first communication chip, the first transmission line is used for establishing an interconnection channel between the first communicator and the second communicator, and the first communication chip is used for communicating with the second communicator through the interconnection channel;
performing line analysis on the first transmission line according to a preset line parameter type to obtain a first line parameter corresponding to the first transmission line, and establishing a first test line in the first communicator according to the first line parameter, wherein a first test interface is arranged at a first end of the first test line;
connecting a second end of the first test line to the second communicator to establish a test channel between the first communicator and the second communicator;
and performing channel characteristic test on the test channel through the first test interface to obtain channel characteristic parameters corresponding to the test channel, and determining the channel characteristic parameters as channel characteristic test results of the interconnection channels.
2. The method of claim 1, wherein the interconnection channel between the first communicator and the second communicator is established by:
the first communicator further comprises a first communication connector, wherein the communication connector is connected with the first communication chip through the first transmission line;
the second communicator comprises a second communication connector, a second transmission line and a second communication chip, wherein the second communication connector is connected with the second communication chip through the second transmission line;
and arranging a communication wiring harness between the first communication connector and the second communication connector, so that the first communication chip is connected with the second communication chip through the first transmission line, the first communication connector, the communication wiring harness, the second communication connector and the second transmission line in sequence.
3. The method of claim 2, wherein after acquiring the first communicator and the second communicator and before connecting the second end of the first test line to the second communicator, the method further comprises:
performing line analysis on the second transmission line according to a preset line parameter type to obtain a second line parameter corresponding to the second transmission line;
and establishing a second test line in the second communicator according to the second line parameter, wherein a second test interface is arranged at the first end of the second test line.
4. The method of claim 3, wherein connecting the second end of the first test line to the second communicator comprises:
arranging a first test connector at the second end of the first test line, and arranging a second test connector at the second end of the second test line;
and arranging a test wire harness between the first test connector and the second test connector, so that the first test interface is connected with the second test interface through the first test wire, the first test connector, the test wire harness, the second test connector and the second test wire in sequence.
5. The method of claim 4, further comprising at least one of:
arranging a first circuit board in the first communicator, wherein the first circuit board is used for loading the first communication chip, the first transmission line, the first communication connector, the first test interface, the first test line and the first test connector;
and arranging a second circuit board in the second communicator, wherein the second circuit board is used for loading the second communication chip, the second transmission line, the second communication connector, the second test interface, the second test line and the second test connector.
6. The method as recited in claim 5, wherein the first test interface and/or the second test interface comprises an IPEX connector.
7. The method of any one of claims 1 to 6, wherein the line parameter types include one or more of a reference layer line, a corresponding layer line, a transmission line length, a transmission line width, a transmission line via number, a transmission line via location, and an overall line shape.
8. A channel characteristic testing system, comprising:
the system comprises an acquisition module, a first communication module and a second communication module, wherein the first communication module comprises a first transmission line and a first communication chip, the first transmission line is used for establishing an interconnection channel between the first communication module and the second communication module, and the first communication chip is used for communicating with the second communication module through the interconnection channel;
the test line establishing module is used for performing line analysis on the first transmission line according to a preset line parameter type to obtain a first line parameter corresponding to the first transmission line, and establishing a first test line in the first communicator according to the first line parameter, wherein a first end of the first test line is provided with a first test interface;
a test channel establishing module, configured to connect a second end of the first test line to the second communicator, so as to establish a test channel between the first communicator and the second communicator;
and the test module is used for carrying out channel characteristic test on the test channel through the first test interface to obtain channel characteristic parameters corresponding to the test channel, and determining the channel characteristic parameters as channel characteristic test results of the interconnection channels.
9. An electronic device, comprising: a processor and a memory;
the memory is configured to store a computer program and the processor is configured to execute the computer program stored by the memory to cause the electronic device to perform the method of any of claims 1 to 7.
10. A computer-readable storage medium having stored thereon a computer program, characterized in that:
the computer program when executed by a processor implements the method of any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210901175.4A CN115168126A (en) | 2022-07-28 | 2022-07-28 | Channel characteristic testing method and system, electronic device and readable storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210901175.4A CN115168126A (en) | 2022-07-28 | 2022-07-28 | Channel characteristic testing method and system, electronic device and readable storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115168126A true CN115168126A (en) | 2022-10-11 |
Family
ID=83477002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210901175.4A Pending CN115168126A (en) | 2022-07-28 | 2022-07-28 | Channel characteristic testing method and system, electronic device and readable storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115168126A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117452185A (en) * | 2023-10-31 | 2024-01-26 | 海光信息技术(成都)有限公司 | Chip connector high frequency electrical characteristics testing device and method |
-
2022
- 2022-07-28 CN CN202210901175.4A patent/CN115168126A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117452185A (en) * | 2023-10-31 | 2024-01-26 | 海光信息技术(成都)有限公司 | Chip connector high frequency electrical characteristics testing device and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6785625B1 (en) | Characterizing multi-port cascaded networks | |
| CN113347067B (en) | Method, device and device for determining bandwidth of PCIe signal | |
| US20100277197A1 (en) | System and method implementing short-pulse propagation technique on production-level boards with incremental accuracy and productivity levels | |
| CN109406839B (en) | Signal test fixture, system and test method | |
| CN101645030A (en) | Method for measuring signal integrality based on SAS storage system | |
| CN119001538A (en) | Signal testing device, signal testing method and display fault detection method | |
| CN114994576B (en) | Device and method for testing net insertion loss of board-end radio frequency connector | |
| CN106950488A (en) | A kind of circuit board and detection method | |
| CN115168126A (en) | Channel characteristic testing method and system, electronic device and readable storage medium | |
| CN117743053A (en) | High-speed signal processing method, device, equipment and system | |
| US11169194B2 (en) | Technologies for verifying a de-embedder for interconnect measurement | |
| CN113014339A (en) | Quality test method, device and equipment for PCIe external plug-in card receiving channel | |
| CN117191340A (en) | S parameter testing method for high-speed light emission TO-type device | |
| CN107562587A (en) | A kind of method of assessment signal link load | |
| CN104280639B (en) | Test device and method of high-speed video bus connectors | |
| CN214278926U (en) | Device and system for testing physical signal electrical characteristics of central processing unit | |
| CN113268390A (en) | Test fixture, system and method for mSATA interface | |
| CN114706718B (en) | A PCIe signal integrity verification method, device, equipment and medium | |
| US9417275B2 (en) | Cable measuring device and method | |
| CN119689230A (en) | Method for detecting integrity of full-link simulation signals of backboard and sub-board combined backboard | |
| CN219872360U (en) | PCIE TX signal quality testing device | |
| CN101667150A (en) | SATA signal testing method based on storage subsystem | |
| CN116319475A (en) | A signal analysis method, device, equipment and storage medium | |
| CN202102419U (en) | Serial connection small-sized computer system interface equipment detection system | |
| CN101667151A (en) | Signal integrity testing method based on server PCI-Express |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |