CN1151050A - bridge between system buses - Google Patents
bridge between system buses Download PDFInfo
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- CN1151050A CN1151050A CN95119635A CN95119635A CN1151050A CN 1151050 A CN1151050 A CN 1151050A CN 95119635 A CN95119635 A CN 95119635A CN 95119635 A CN95119635 A CN 95119635A CN 1151050 A CN1151050 A CN 1151050A
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- bus
- dma
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/404—Coupling between buses using bus bridges with address mapping
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
- G06F12/0623—Address space extension for memory modules
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bus Control (AREA)
- Memory System (AREA)
Abstract
一个配置两总线间的桥接器的计算机系统，该系统具有不同存储器寻址容量的两根总线和一个产生M位地址的第一总线主机。为产生用于第二总线的N位地址，在桥接器上的一个直接存储器存取(DMA)控制器产生P位，这里P+M＝N。该P位同M位链接，以形成在第二总线上访问存储器所用的N位地址。P位的这种附加将可由M位寻址的存储段重新分配到可由N位地址寻址的存储器映象范围内的任何位置。
A computer system configured with a bridge between two buses, the system has two buses with different memory addressing capacities and a first bus master generating M-bit addresses. To generate the N-bit address for the second bus, a direct memory access (DMA) controller on the bridge generates P bits, where P+M=N. The P bit is linked with the M bit to form the N bit address used to access the memory on the second bus. This addition of P bits reallocates memory segments addressable by M bits to anywhere within the range of the memory map addressable by N bits of addresses.
Description
The present invention relates to the digital computing system field, and relate more specifically to one have two or more in the system of multibus to the access procedure of memory section.
In computer system, electronic chip and Ji Ta component interconnect each other by bus.Thereby all components can be connected to bus provide link bus all the device between intercommunication.It is a kind of that to have obtained the bus that industry member accepts extensively be industrial standard system (ISA) bus.Isa bus has 24 (24) root memory address lines, thereby the storage support up to ten six (16) megabyte is provided.This acceptable widely of isa bus caused occupying very big number percent for being used in the equipment of making on the isa bus.Yet the higher speed input-output apparatus the Video Controller in being generally used for the current computer system requires bus faster.
Solution for the general considerations that transmits and receive data from processor to any high speed input equipment is a local bus.Do not resemble the isa bus of operating relatively slowly from finite bandwidth, a local bus is communicated by letter and transmitted with 32 under system speed is the data block of unit.Local bus scheme (Local bus schemes) is removed such as storer from main system bus, and display and (magnetic) disk drive etc. need those interfaces of fast-response.A this local bus that obtains accepting extensively in computer industry is the peripheral component interconnect (pci) bus.Pci bus can be 32 or the path, 64-position that is used for high-speed data transfer.In essence, pci bus is a parallel data path that is provided with except that isa bus.System processor and storer can for example directly or by a main bridge be linked pci bus, and such as image display adapter, other equipment of (magnetic) disk controller etc. also can directly be linked pci bus.
The communication of equipment room is coupling between pci bus and the isa bus bridge chip on the double bus in order to provide.This bridge chip becomes pci bus circulation with the isa bus cyclic transformation and vice versa in fact.
Linking many in the equipment of pci bus and isa bus is to be independent of the main equipment that bus or other equipment are handled.Receive order and response host requests from (genus) or target device.
Pci bus has 32 (32) bit addressing abilities of the memory access that four (4) GB are provided.The storage unit in the storer is possible on the pci bus though the main frame on the isa bus gone to visit, but because 24 bit addressing capacity of this isa bus main frame are, the isa bus main frame is limited to usually only visits on the pci bus from zero memory block to 16 megabyte.This makes the major part of 32 storage mappings to be visited by the ISA-bus host.In addition, low 16 megabyte of some operating system allocate memory are used for the purposes except that the isa bus main frame.
A kind of device of being devoted to address this problem, the highest significant position that utilizes external circuit that 32 PCI addresses are set when detecting host signal on isa bus is height.This just will redistribute to give to one above minimum 16 megabyte in storage mapping and decide in the district the memory access of specific 16 megabyte sections (or piece).Some shortcomings of this method comprise the requirement of external circuit and ineffective activity because 16 byte storage block will be redistributed to this restriction of same memory cell in the 4 GB storage mappings.
Need to provide in the storage mapping scope of a kind of like this device in the first and second different bus systems of storage access scope are arranged reallocation able to programme to memory block.
This and other all needs are all satisfied by the present invention, promptly the invention provides a kind of bridge, be used to connect all buses interface of a computer system, this system has first bus---and it has M bit memory addressing capacity, be coupled to first bus host that first bus produces the M bit address that is used for memory access, be coupled to first bus and second bus of N bit memory addressing capacity (wherein N is greater than M) is arranged, and the second bus driver target that is coupled to second bus.This bridge comprises direct memory access (DMA) (DMA) controller that is coupled to first bus.This dma controller has the register that is used to store the P position, N=M+P wherein, and be used for and will deposit the logical circuit of the P position of register with the M bit address link that produces by first bus host in, to form a N bit address, so that visit the storer in second bus storage target on second bus.
Above-mentioned needs also can be met by another embodiment of the present invention, this embodiment provides a computer system that comprises with the lower part: first bus that M bit memory addressing capacity is arranged, be coupled to first bus host that first bus produces the M bit address that is used for memory access, be coupled to first bus and second bus of N bit memory addressing capacity (N is greater than M here) is arranged, be coupled to the second bus driver target of second bus, and direct memory access (DMA) (DMA) controller that is coupled to first bus.This dma controller has the register that is used to store the P position, N=M+P wherein, and be used for will deposit in the P position of register with the logical circuit of the M bit address link that produces by first bus host, to form a N bit address so that visit the storer in second bus storage target on second bus.
The present invention has and need not external circuit and go to provide to can be by the advantage of the visit more than the lower megabyte of M bit address addressable memory.But some positions that only will deposit a register in can be visited the N-bit memory address of arbitrary storage unit with the link of M bit address to form.And prior art has been eliminated with the link of M bit address in many positions one memory paragraph has been redistributed to the restriction aspect storage unit in the memory map only.
In some most preferred embodiment, this register is programmable respectively each designated value of P position is deposited in storage unit in the register.This characteristic makes memory paragraph can dynamically be re-assigned to different storage unit in the memory map.
With regard to another aspect of the present invention, be provided with a computer system, this system comprises: first bus that M bit memory addressing capacity is arranged; Be coupled to first bus and produce first bus host that is used for the X-byte of storer is carried out the M bit address of memory access; Be coupled to first bus and second bus of N bit memory addressing capacity (N is greater than M here) is arranged, carry out memory access in order to the Y-byte to storer, Y is greater than X here; Be coupled to the second bus driver target of second bus, and the logical circuit that is used for indicating the X-byte length storage block of arbitrary assigned address in the first bus host reference-to storage Y bytes range able to programmely.
From below in conjunction with will clearer above-mentioned and other purposes, characteristic, various aspects and various advantages of the present invention the accompanying drawing detailed description of the present invention.
Fig. 1 is the skeleton view of a computer system of the present invention.
Fig. 2 is the block scheme by Fig. 1 computer system of one embodiment of the invention formation.
Fig. 3 is the memory map block scheme with memory paragraph of redistributing by prior art.
Fig. 4 is the block scheme with memory map of the memory paragraph of redistributing by the present invention.
Fig. 5 is the block scheme of each several part of the present invention.
Fig. 6 is an example embodiment calcspar by the dma controller of one embodiment of the invention formation.
Now referring to all accompanying drawings, especially with reference to Fig. 1, label is that 10 traditional computer or PC promptly belong to and make the useful especially environment of the present invention.Computing machine 10 is best, but unessential, is with IBM type personal computer or similar system, comprises a control desk shell 12,---the circuit board of necessary circuitry such as comprising microprocessor and BIOS chip is housed, random access memory and other hardware in it.This computing machine also will comprise video display 14 and the keyboard 16 of linking shell 12 by cable 18.A large amount of mediums comprise the hard disk drive in the impalpable shell of user, the floppy disk that can contact with the user, and optional CD- ROM drive 20 and 22.
Fig. 2 is a kind of block scheme of prior art configuring computer system.Local bus 30 such as peripheral controllers interconnection (PCI) bus 30 has the PCI slave storage 40 of pci bus of being coupled to 30.This computer system also has second bus as expansion bus 32.Expansion bus 32 can (for example) be industrial standard system (ISA) bus.Though isa bus 32 than pci bus 30 slowly many because many current available devices that are coupled to isa bus 32 all can not carry out and the suitable speed of pci bus 30 speed, so isa bus 32 is useful.Therefore the structure of Fig. 2 provides a permission first bus 30 of using high-speed equipment and second bus 32 that allows to use than low-speed device.
Bridge chip 34 is provided with an interface between pci bus 30 and the isa bus 32.A plurality of IAS bus hosts 36 and ISA are coupled to isa bus 32 from storer 38.
Bridge chip 34 provides the interface between pci bus 30 and the isa bus 32.Isa bus interface 42 in the bridge chip 34 becomes the system bus circulation to pass through bridge chip 34 for using the isa bus cyclic transformation.Pci bus interface 46 will become to be used for the system bus circulation of bridge chip 34 from the pci bus cyclic transformation of pci bus 30.A dma controller circuit 50 provides system scope interior DMA control to storage access.Dma controller circuit 50 provides a plurality of independently DMA passages, the memory access that relates to each ISA main frame 36 respectively on these passages by UNICOM.Dma control circuit 50 also provides system's arbitration to it when isa bus main frame 36 needs to carry out the DMA conversion.
As stating more already, the addressing capacity of pci bus 30 provides the memory addressing capacity of 4 GB.Fig. 3 is the map figure of 4 gigabit storeies and is illustrated in the 4 GB scopes by the reallocation of prior art to 16 megabyte of storer.Because isa bus main frame 36 only can produce 24 bit address, so be limited to the interior storer of visit 16 megabyte segment limits.Be shown low 16 megabyte of storer among Here it is Fig. 3.Have now found that the storer of preferably reorientating this low 16 megabyte sections top.When prior art measures host signal with the highest significant position of 32 PCI addresses with external circuit on isa bus 32, be set at height and solve.As shown in Figure 3, this of storer 16 megabyte are redistributed into a diverse location in the storer 4 GB scopes.Yet the all-access by the storer on 36 pairs of pci buss 30 of isa bus main frame all is the visits to this same reallocation.
Otherwise,, the invention provides storer 16 megabyte sections with 16 megabyte memory paragraph dynamic reallocation arbitrary regulation to the storer 4 GB scopes as Fig. 4 finding.Each independently isa bus main frame 36 in the storer 4 GB scopes one independently storer 16 megabyte section can be arranged.By the present invention the exemplary distribution of 16 megabyte sections is depicted in the memory map of Fig. 4.
For ease of explanation, only will be depicted in the block scheme of Fig. 5 by some part of the system of the present invention of Fig. 2.Shown in single isa bus main frame 36 linked bridge chip 34 by isa bus 32.Single subordinate PCI storer 40 is coupled to bridge chip 34 via pci bus 30.
The dma controller circuit 50 that is positioned on the bridge chip 34 comprises high page register 66, and register 66 comprises the high byte (after a while will according to an example embodiment of Fig. 5 and 6 more detailed description dma controllers 50) of isa bus main memory address.As known in the art, when the DMA passage being placed cascade system following time, this means: a certain given DMA passage of dma controller circuit 50 will be used for system's arbitration via isa bus main frame 36.When dma controller circuit 50 detects when this cascade system channel request DMA arbitrated, dma controller circuit 50 attempts to obtain the system's control to isa bus main frame 36.In case given control to the cascade system passage, dma controller 50 just will transmit counter 68 to the content of high page or leaf (high page) register of this special modality DMA that packs into.When dma controller circuit 50 was asserted a confirmation signal, isa bus main frame 36 was sent to the PCI32 bit memory with beginning and sends from the PCI32 bit memory.Be included in the high byte that transmits in the counter 68 and link, to form complete 32 PCI storage addresss with 24 isa bus host addresses.
Isa bus main frame 36 is operated in a conventional manner, to visit 16 megabyte.Memory addressing more than the 16 megabyte limit is passed straight through to isa bus main frame 36 and carried out so that a high byte is linked to the isa bus host address by bridge 34 usefulness dma controllers 50.
Before describing the concrete one exemplary embodiment to be used to provide 32 PCI addresses, the brief overview of dma controller is described as follows than the dma controller of high eight-bit.In a digital machine, institute's deposit data in the microprocessor processes primary memory.Because primary memory has physical length restriction, also be provided with the memory device of the large storage capacity that appends to primary memory and separate with primary memory.Be stored in when microprocessor will utilize, for example, during data in the mass storage of hard disk and so on, data moved into the primary memory from hard disk.This is very time-consuming process the mobile of computer-internal storage block, and if microprocessor itself goes the control store transfer can seriously hinder performance of computer systems.
For alleviating the mobile burden of microprocessor control computer internal memory blocks, adopted a direct memory access (DMA) (DMA) controller.Dma controller receives from the relevant initial home position that will mobile byte of microprocessor, the information of address that these bytes should be sent to and the byte number that moves.In case this is by the microprocessor programmed, dma controller is the transfer of supervisory computer internal system memory data just.The data that common dma operation is used between I/O (I/O) equipment and the storer move.
Commercially available dma controller is the 8237DMA controller that Intel Company makes.Each 8237DMA controller provides the DMA passage of four separations that can be used for memory transfer independently.Some well-known computer system, for example IBM PC/AT design comprises two 8237DMA controllers.Fig. 5 and 6 dma controller circuit 50 use these traditional dma controllers 60,62 as known in the prior art, and a passage of first dma controller 60 is used for cascade second dma controller 62.Therefore this provides seven DMA passages altogether to dma controller 60,62, promptly provides four passages by first controller 60 and second controller 62 provides three passages.
Among Fig. 6 and not shown such as some unlike signals such as clock signals so that the present invention can clearly be described.Yet, one skilled in the art will realize that and in fact used these classical signal.
When dma controller 60,62 served as bus host, first and second dma controllers 60,62 produced 16 bit memory addresses for pci bus 30.Dma controller circuit 50 also has a low page register 64 and a high page register 66.Low page register 64 has been used for prior art design (such as IBM PC/AT) so that eight (8) s in addition of memory addressing capacity to be provided), generation is 24 (24) bit addressing capacity, i.e. 16 megabyte altogether.The present invention provides eight in addition of memory addressing capacity for total 32 (32) bit addressing capacity or 4 GB.These additional 8 when isa bus main frame 36 obtains control to the DMA passage,, be set on the pci bus 30 by high page register 66 (with storage address low 24 link).The content of high page register 66 may be different to each of seven different DMA passages so that seven isa bus main frames 36 can be on pci bus 30 seven differences, the 16 GB sections of access memory 4 GB scope internal storage.High page register 66 is programmable, therefore can change to one independently bus host 36 be used for the distribution of a specific memory storage unit of 16 megabyte sections.
Make for the additional high page register of existing structure of used dma controller circuit in the IBM PC/AT computer system to carry out 32 to pci bus and seek and pulling, that uses simultaneously that technology well-known and after tested goes to provide storage address hangs down 24.
Though now the present invention has been done to describe in detail and diagram, obviously, foregoing only is diagram and is not that the spirit and scope of the present invention only are subjected to every restriction of appended claims as restriction for example.
Claims (23)
1. bridge, be used to connect all buses interface of a computer system, this system has that first bus-it has M bit memory addressing capacity, be coupled to first bus host that first bus produces the M bit address that is used for memory access, be coupled to first bus and second bus of N bit memory addressing capacity (wherein N is greater than M) is arranged, and the second bus driver target that is coupled to second bus, this bridge comprises:
Be coupled to direct memory access (DMA) (DMA) controller of first bus.This dma controller has the register that is used to store high-order P position, N=M+P wherein, and be used for and deposit the logical circuit of register high-order P position in the M bit address link that produces by first bus host, to form a N bit address, so that visit the storer in second bus storage target on second bus.
2. bridge as claimed in claim 1, it is characterized in that: there are a plurality of first bus hosts in this system, and dma controller has a plurality of DMA passages, storage address just transmits on these passages, each first bus host communicates on different DMA passages, register has a plurality of storage unit, and each storage unit is corresponding to different DMA passages.
3. bridge as claimed in claim 2 is characterized in that: described register is for depositing in the independent storage unit P position designated value programmable respectively.
4. bridge as claimed in claim 3, it is characterized in that: the designated value of described P position is different in each independent storage unit, so that for the formed N bit address of independent first bus host is different, thereby the different storage blocks in the access second memory target.
5. the bridge of claim 4 is characterized in that: described first bus is that industrial standard system (ISA) bus and second bus are peripheral component interconnection (PCI) buses.
6. the bridge of claim 5, it is characterized in that: M is 24, N be 32 and P be 8
7. the bridge of claim 6, it is characterized in that: dma controller is the dma controller of a cascade
8. computer system comprises:
First bus that M bit memory addressing capacity is arranged;
Be coupled to first bus and produce first bus host that is used for the X byte of storer is carried out the M bit address of memory access;
Be coupled to first bus and second bus of N bit memory addressing capacity (N is greater than M here) is arranged, carry out memory access in order to the Y byte to storer, Y is greater than X here;
Be coupled to the target of second bus driver of second bus: and
Be used for indicating the logical circuit of the X byte length storage block of arbitrary assigned address in the first bus host reference-to storage Y bytes range able to programmely.
9. the system of claim 8, it is characterized in that: described logical circuit comprises direct memory access (DMA) (DMA) controller that is coupled to first bus, dma controller has one to be used to store the register of P position, here N=M+P, and the P position that is used for this register is stored is with the M bit address link that is produced by first bus host, to be formed for the logical circuit of addressing N bit address of the storer in the second bus driver target on second bus.
10. the described system of claim 9 is characterized in that: the Memory Storage Unit in the described M position access X byte length piece scope, and the designated memory cell of the X byte length piece in the access memory Y bytes range of P position.
11. the system of claim 10, it is characterized in that: also comprise: a plurality of first bus hosts, wherein dma controller has a plurality of DMA passages, on these passages, transmit storage address, the communication on a different DMA passage of each first bus host has the register of a plurality of storage unit, and each storage unit is corresponding to different DMA passages.
12. the system of claim 11 is characterized in that: described register is to can be to deposit P position designated value in independent storage unit respectively and programmable.
13. the system of claim 12 is characterized in that: P position designated value is different in each independent storage unit, so that for the N bit address of independent first bus host formation is different, thereby the different masses of the storer in the energy access second memory target.
14. the system of claim 13 is characterized in that: first bus is industrial standard system (ISA) bus, and second bus is the peripheral component interconnect (pci) bus.
15. the system of claim 14 is characterized in that: M is 24, N be 32 and P be 8.
16. the system of claim 15 is characterized in that: dma controller is the dma controller of a cascade.
17. a computer system comprises:
First bus that M bit memory addressing capacity is arranged;
Be coupled to first bus host that first bus produces the M bit address that is used for memory access;
Be coupled to first bus and second bus of N bit memory addressing capacity (N is greater than M here) is arranged;
Be coupled to the second bus driver target of second bus; And
Be coupled to direct memory access (DMA) (DMA) controller of first bus.This dma controller has the register that is used to store high-order P position, N=M+P wherein, and be used for will deposit in the high-order P position of register with the logical circuit of the M bit address link that produces by first bus host, to form a N bit address so that visit the storer in second bus storage target on second bus.
18. the system of claim 17 is characterized in that: also comprise a plurality of first bus hosts, wherein dma controller has a plurality of DMA passages that transmit storage address thereon.Each first bus host communicates on different DMA passages, and described register has a plurality of storage unit, and each storage unit is corresponding to different DMA passages.
19. the system of claim 18 is characterized in that: described register is programmable for depositing P position designated value in each storage unit respectively.
20. the system of claim 19 is characterized in that: P position designated value is different in each independent storage unit, and it is different causing the N bit address that forms for independent first bus host, visits the different masses of storer in the second storage target whereby.
21. the system of claim 20 is characterized in that: first bus is industrial standard system (ISA) bus, and second bus is the peripheral component interconnect (pci) bus.
22. the system of claim 21 is characterized in that: M is 24, N be 32 and P be 8.
23. the system of claim 22 is characterized in that: dma controller is the dma controller of a cascade.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US35119194A | 1994-11-30 | 1994-11-30 | |
| US351,191 | 1994-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1151050A true CN1151050A (en) | 1997-06-04 |
Family
ID=23379952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN95119635A Pending CN1151050A (en) | 1994-11-30 | 1995-11-17 | bridge between system buses |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP0795159A1 (en) |
| JP (1) | JPH08235105A (en) |
| KR (1) | KR960018940A (en) |
| CN (1) | CN1151050A (en) |
| BR (1) | BR9505209A (en) |
| CA (1) | CA2160499A1 (en) |
| PL (1) | PL320022A1 (en) |
| WO (1) | WO1996017304A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102331978A (en) * | 2011-07-07 | 2012-01-25 | 曙光信息产业股份有限公司 | DMA (Direct Memory Access) controller access implementation method for Loongson blade large-memory address devices |
| CN103516458A (en) * | 2012-06-27 | 2014-01-15 | Nxp股份有限公司 | Communications apparatus, system and method with error mitigation |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH103447A (en) * | 1996-06-18 | 1998-01-06 | Matsushita Electric Ind Co Ltd | Bus bridge device |
| US5857080A (en) * | 1996-09-10 | 1999-01-05 | Lsi Logic Corporation | Apparatus and method for address translation in bus bridge devices |
| US6163818A (en) * | 1998-08-27 | 2000-12-19 | Xerox Corporation | Streaming memory controller for a PCI bus |
| US6457077B1 (en) * | 1999-06-10 | 2002-09-24 | International Business Machines Corporation | System for executing a current information transfer request even when current information transfer request exceeds current available capacity of a transit buffer |
| AU2002328037A1 (en) * | 2002-09-23 | 2004-04-08 | Telefonaktiebolaget Lm Ericsson (Publ) | Computer system and method for accessing external peripheral devices in a computer system |
| US10284247B2 (en) | 2013-06-10 | 2019-05-07 | Nxp B.V. | System and method for bit processing in a central network component |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4878166A (en) * | 1987-12-15 | 1989-10-31 | Advanced Micro Devices, Inc. | Direct memory access apparatus and methods for transferring data between buses having different performance characteristics |
| US5214767A (en) * | 1989-02-07 | 1993-05-25 | Compaq Computer Corp. | Full address and odd boundary direct memory access controller which determines address size by counting the input address bytes |
| DE69020212T2 (en) * | 1989-04-07 | 1996-04-04 | Tektronix Inc | Bus-to-bus interface system with lock conversion. |
-
1995
- 1995-10-13 CA CA002160499A patent/CA2160499A1/en not_active Abandoned
- 1995-11-17 BR BR9505209A patent/BR9505209A/en not_active Application Discontinuation
- 1995-11-17 CN CN95119635A patent/CN1151050A/en active Pending
- 1995-11-27 WO PCT/GB1995/002744 patent/WO1996017304A1/en not_active Ceased
- 1995-11-27 EP EP95937979A patent/EP0795159A1/en not_active Withdrawn
- 1995-11-27 PL PL95320022A patent/PL320022A1/en unknown
- 1995-11-28 JP JP7308852A patent/JPH08235105A/en active Pending
- 1995-11-29 KR KR1019950044780A patent/KR960018940A/en not_active Ceased
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102331978A (en) * | 2011-07-07 | 2012-01-25 | 曙光信息产业股份有限公司 | DMA (Direct Memory Access) controller access implementation method for Loongson blade large-memory address devices |
| CN103516458A (en) * | 2012-06-27 | 2014-01-15 | Nxp股份有限公司 | Communications apparatus, system and method with error mitigation |
| CN103516458B (en) * | 2012-06-27 | 2016-01-20 | Nxp股份有限公司 | There is communicator, system and method that mistake alleviates |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960018940A (en) | 1996-06-17 |
| PL320022A1 (en) | 1997-09-01 |
| BR9505209A (en) | 1997-09-16 |
| CA2160499A1 (en) | 1996-05-31 |
| WO1996017304A1 (en) | 1996-06-06 |
| EP0795159A1 (en) | 1997-09-17 |
| JPH08235105A (en) | 1996-09-13 |
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