CN115085680B - Amplifier - Google Patents
AmplifierInfo
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- CN115085680B CN115085680B CN202110266449.2A CN202110266449A CN115085680B CN 115085680 B CN115085680 B CN 115085680B CN 202110266449 A CN202110266449 A CN 202110266449A CN 115085680 B CN115085680 B CN 115085680B
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- amplifier
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- gain
- transistor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
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- Nonlinear Science (AREA)
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Abstract
An amplifier includes an amplifier circuit and a gain adjustment circuit. The amplifier circuit has a design gain and an actual gain, and outputs an output signal according to an input signal and the actual gain. The gain adjusting circuit is coupled to the amplifier circuit and is used for receiving the input signal to compare a voltage of the input signal with a first reference voltage, wherein when the voltage of the input signal exceeds the first reference voltage, the gain adjusting circuit increases the actual gain of the amplifier circuit so that the actual gain approaches the design gain.
Description
Technical Field
The present disclosure relates to an amplifier, and more particularly, to an amplifier with a gain adjustment circuit.
Background
In general, assuming that the gain of an amplifier circuit is 0dB, when the input signal to the amplifier circuit is a small signal (e.g., 70 mV), the magnitude of the output signal of the amplifier circuit is approximately equal to the magnitude of the input signal. However, when the input signal is a large signal (e.g., 1000 mV), the gain of the amplifier circuit is difficult to maintain at 0dB due to the characteristics of the transistors in the amplifier circuit, resulting in an output signal that is smaller than the input signal. In short, conventional amplifier circuits often suffer from nonlinear amplification when receiving large input signals, causing the back-end circuit to receive distorted signals. Therefore, there is a need for an improvement over conventional amplifier circuits.
Disclosure of Invention
One aspect of the present disclosure is an amplifier. The amplifier includes an amplifier circuit and a gain adjustment circuit. The amplifier circuit has a design gain and an actual gain, and outputs an output signal according to an input signal and the actual gain. The gain adjusting circuit is coupled to the amplifier circuit and is used for receiving the input signal to compare a voltage of the input signal with a first reference voltage, wherein when the voltage of the input signal exceeds the first reference voltage, the gain adjusting circuit increases the actual gain of the amplifier circuit so that the actual gain approaches the design gain.
In summary, by designing the gain adjustment circuit, the amplifier of the present disclosure can adjust the actual gain of the amplifier circuit when the input signal exceeds the first reference voltage, so that the actual gain approaches the design gain originally designed for the amplifier circuit. In this way, the amplifier can maintain the same gain when receiving input signals with different magnitudes (i.e., the amplifier can maintain the linearity of amplification even if the amplifier is affected by the transistor characteristics), so that the back-end circuit receives undistorted signals.
Drawings
Fig. 1 is a block diagram of an amplifier according to some embodiments of the present disclosure.
Fig. 2 is a schematic diagram showing a design gain, an actual gain before adjustment, and an actual gain after adjustment of an amplifier circuit in an amplifier according to some embodiments of the present disclosure.
Fig. 3 is a schematic circuit diagram of an amplifier according to some embodiments of the present disclosure.
Fig. 4 is a schematic circuit diagram of an amplifier according to some embodiments of the present disclosure.
Fig. 5 is a circuit diagram of another amplifier according to another embodiment of the present disclosure.
Fig. 6 is a circuit diagram of another amplifier according to another embodiment of the present disclosure.
Fig. 7 is a circuit diagram of another amplifier according to another embodiment of the present disclosure.
Detailed Description
The following detailed description of exemplary embodiments is provided in connection with the accompanying drawings, but the specific embodiments described are for illustration purposes only and are not intended to limit the scope of the invention, which is defined by the appended claims, in which the description of the structure and operation is not intended to limit the order in which the elements may be rearranged to produce a device with equivalent efficiency.
The words (terms) used throughout this specification and claims have the ordinary meaning in the art, within the context of this invention and in the specific context, unless otherwise indicated.
In addition, as used herein, "coupled" or "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and may also mean that two or more elements are in operation or action with each other.
Referring to fig. 1, one embodiment of the present disclosure relates to an amplifier 100. The amplifier 100 includes an amplifier circuit 102 and a gain adjustment circuit 104.
In the present embodiment, the amplifier circuit 102 is designed to have a design gain Ad. Referring to fig. 2, in an ideal case, the amplifier circuit 102 outputs an output signal Vout according to an input signal Vin and a design gain Ad, and the relationship between the input signal Vin and the output signal Vout is linear. For example, the design gain Ad is obtained by dividing the magnitude of the output signal Vout by the magnitude of the input signal Vin, regardless of the magnitude of the input signal Vin.
In practical applications, the amplifier circuit 102 outputs the output signal Vout according to the input signal Vin and an actual gain Ar. However, when the magnitude of the input signal Vin exceeds a first reference voltage Vref, the relationship between the input signal Vin and the output signal Vout cannot be maintained in linearity due to the transistor characteristics. Specifically, when the magnitude of the input signal Vin (e.g., 70 mV) does not exceed the first reference voltage Vref (e.g., 500 mV), the actual gain Ar is substantially equal to the design gain Ad, but when the magnitude of the input signal Vin (e.g., 1000 mV) exceeds the first reference voltage Vref, the actual gain Ar becomes smaller than the design gain Ad, and as the magnitude of the input signal Vin increases, the difference between the actual gain Ar and the design gain Ad increases.
Specifically, the amplifier circuit 102 may be a differential amplifier, and the input signal Vin may be a differential signal. Referring to fig. 3, the amplifier circuit 102 includes a first amplifying transistor 121, a second amplifying transistor 122, a first current source 123, a second current source 124, a first impedance element Z1, a second impedance element Z2, and a third impedance element Z3. The input signal Vin has a positive input signal Vin+ and a negative input signal Vin-.
The control terminal (e.g., gate) of the first amplifying transistor 121 is coupled to the negative input terminal of the amplifier circuit 102 and is used for receiving the negative input signal Vin-, and the control terminal (e.g., gate) of the second amplifying transistor 122 is coupled to the positive input terminal of the amplifier circuit 102 and is used for receiving the positive input signal vin+. The first end (e.g., drain) of the first amplifying transistor 121 is coupled to the positive output terminal of the amplifier circuit 102, and the first end (e.g., drain) of the second amplifying transistor 122 is coupled to the negative output terminal of the amplifier circuit 102. The two ends of the first impedance element Z1 are coupled to the second end (e.g., source) of the first amplifying transistor 121 and the second end (e.g., source) of the second amplifying transistor 122, respectively. The two ends of the second impedance component Z2 are coupled to the first end of the first amplifying transistor 121 and the system high voltage Vcc, respectively, and the two ends of the third impedance component Z3 are coupled to the first end of the second amplifying transistor 122 and the system high voltage Vcc, respectively. The first current source 123 is coupled to the second terminal of the first amplifying transistor 121 and a ground voltage GND for providing a first bias current Ibias1, and the second current source 124 is coupled to the second terminal of the second amplifying transistor 122 and the ground voltage GND for providing a second bias current Ibias2.
As further shown in fig. 1, the gain adjustment circuit 104 is coupled to the amplifier circuit 102. In this embodiment, the gain adjustment circuit 104 includes a comparator 141 and a processing circuit 143. The comparator 141 is coupled to the positive input terminal and the negative input terminal of the amplifier circuit 102, the processing circuit 143 is coupled to the output terminal of the comparator 141, and the output terminal of the processing circuit 143 is coupled to the first impedance component Z1 of the amplifier circuit 102.
In operation, the comparator 141 is configured to receive the input signal Vin and the first reference voltage Vref, which are input to the amplifier circuit 102, and compare the voltage of the input signal Vin with the first reference voltage Vref. Specifically, the first reference voltage Vref includes a positive first reference voltage Vref+ and a negative first reference voltage Vref-. The comparator 141 is used for comparing the voltage of the positive input signal Vin+ with the positive first reference voltage Vref+, and comparing the voltage of the negative input signal Vin-with the negative first reference voltage Vref-. When the voltage of the positive input signal Vin+ (e.g., 600 mV) is detected to be Yu Zhengdi + larger than a reference voltage Vref+ (e.g., 500 mV) and the voltage of the negative input signal Vin-is detected to be less than the negative first reference voltage Vref- (e.g., -600 mV), the comparator 141 outputs a detection signal DS to the processing circuit 143.
In this embodiment, the processing circuit 143 is configured to reduce the resistance of the first impedance element Z1 according to the detection signal DS. Based on the small signal model, the gain of the amplifier circuit 102 satisfies the following equation (1):
Ar=gm*Rd/(1+gm*Rs/2)...(1)
Where Ar is the actual gain of the amplifier circuit 102, gm is the transduction of the first amplifying transistor 121 or the second amplifying transistor 122, rd is the resistance value of the second impedance component Z2 or the third impedance component Z3, and Rs is the resistance value of the first impedance component Z1.
As can be seen from this, when the processing circuit 143 decreases the resistance value of the first impedance element Z1, the actual gain Ar of the amplifier circuit 102 increases, and the conventional design gain Ad approaches. In other words, when the comparator 141 detects that the voltage of the input signal Vin exceeds the first reference voltage Vref (at this time, the actual gain Ar is less than the design gain Ad due to the influence of the transistor characteristics), the processing circuit 143 decreases the resistance value of the first impedance component Z1 to increase the actual gain Ar of the amplifier circuit 102, and then the actual gain Ar approaches the design gain Ad.
In another embodiment, the comparator 141 is configured to receive a second reference voltage (not shown) greater than the first reference voltage Vref in addition to the input signal Vin and the first reference voltage Vref. After the processing circuit 143 increases the actual gain Ar of the amplifier circuit 102, if the voltage of the input signal Vin increases again and exceeds the second reference voltage, the comparator 141 will output the detection signal DS to the processing circuit 143 again, so that the processing circuit 143 decreases the resistance value of the first impedance component Z1 again, so as to increase the actual gain Ar of the amplifier circuit 102 again. It is understood that the comparator 141 can receive more reference voltages (e.g., a third reference voltage (not shown) greater than the second reference voltage) as required, so that the processing unit 143 can continuously increase the actual gain Ar of the amplifier circuit 102 as the magnitude of the input signal Vin increases. In this way, the adjusted actual gain Ar' (as shown in fig. 2) will have a higher linearity than the actual gain Ar before adjustment.
Referring to fig. 3 and fig. 4 together, specifically, the first impedance component Z1 in the amplifier circuit 102 includes a plurality of first transistors M1 a-M1 c, a plurality of first resistors R1 a-R1 c, and a plurality of second resistors R2 a-R2 c. The first ends (e.g., drains) of the first transistors M1 a-M1 c are coupled to the second ends (e.g., sources) of the second amplifying transistors 122 and the second current source 124 through the second resistors R2 a-R2 c, the second ends (e.g., sources) of the first transistors M1 a-M1 c are coupled to the second ends (e.g., gates) of the first amplifying transistors 121 and the first current source 123 through the first resistors R1 a-R1 c, and the processing circuit 143 of the gain adjusting circuit 104 is coupled to the control ends (e.g., gates) of the first transistors M1 a-M1 c.
It is assumed that only the first transistor M1a is turned on before the processing unit 143 receives the detection signal DS, and at this time, the first transistors M1 b-M1 c are turned off, and the equivalent resistance value of the first impedance component Z1 is approximately equal to the resistance value of the first resistor R1a plus the resistance value of the second resistor R2 a. When receiving the detection signal DS, the processing circuit 143 outputs a plurality of first control signals CS1 to the control terminals of the first transistors M1 a-M1 c, so that the first transistor M1a is kept in an on state, and the first transistors M1 b-M1 c are switched from an off state to an on state. In this way, the equivalent resistance value of the first impedance element Z1 is reduced because three series resistors (the first resistor R1a and the second resistor R2a, the first resistor R1b and the second resistor R2b, and the first resistor R1c and the second resistor R2 c) are connected in parallel.
In another embodiment, the first impedance component Z1 may only include the first transistor M1a (i.e., the first transistors M1 b-M1 c, the first resistors R1 a-R1 c, and the second resistors R2 a-R2 c in fig. 4 are omitted), wherein the first terminal of the first transistor M1a is coupled to the second terminal of the second amplifying transistor 122 and the second current source 124, the second terminal of the first transistor M1a is coupled to the second terminal of the first amplifying transistor 121 and the first current source 123, and the processing circuit 143 is coupled to the control terminal of the first transistor M1 a. It is noted that the first transistor M1a is biased in the linear region (or omu region). In this way, when the detection signal DS is received, the processing circuit 143 can control the voltage level of the first control signal CS1 output to the control terminal of the first transistor M1a, so that the equivalent resistance value of the first impedance element Z1 is reduced (as the first transistor M1a biased in the linear region behaves like a voltage-controlled resistor).
In another embodiment, when the detection signal DS is received, the processing circuit 143 is configured to output a plurality of third control signals (not shown) to adjust the resistance value of the second impedance element Z2 and the resistance value of the third impedance element Z3, so as to increase the actual gain Ar of the amplifier circuit 102. Based on the above formula (1), when the resistance value of the second impedance component Z2 and the resistance value of the third impedance component Z3 are adjusted by the processing circuit 143 to be increased, the actual gain Ar of the amplifier circuit 102 is increased, and the conventional design gain Ad approaches. Specifically, the second impedance element Z2 and the third impedance element Z3 may be implemented as variable resistors, or as transistors as the first impedance element Z1, which are not described herein.
Referring to fig. 5, fig. 5 is a schematic circuit diagram of an amplifier 200 according to still another embodiment of the present disclosure, wherein the same or similar components of the amplifier 200 as the amplifier 100 (e.g., the comparator 141 and the processing circuit 143 of the gain adjusting circuit 104, the first amplifying transistor 121, and the second amplifying transistor 122) are not repeated. During operation of the amplifier 200, the processing circuit 143 adjusts the first bias current Ibias1 provided by the first current source 223 and the second bias current Ibias2 provided by the second current source 224 according to the detection signal DS to increase the actual gain Ar of the amplifier circuit 102. Specifically, the first current source 223 includes a first current mirror (composed of the second transistors M2a and M2 b), a second current mirror (composed of the second transistors M2a and M2 c), and a third current mirror (composed of the second transistors M2a and M2 d), wherein the output terminal Mo1 of the first current mirror is directly coupled to the second terminal of the first amplifying transistor 121, and the output terminal Mo2 of the second current mirror and the output terminal Mo3 of the third current mirror are respectively coupled to the second terminal of the first amplifying transistor 121 through the first switch components SW1 and SW 2.
It is assumed that only the first current mirror provides a first current I1 according to a first reference current Iref before the processing unit 143 receives the detection signal DS, and the first bias current Ibias1 provided by the first current source 223 is the first current I1. When the detection signal DS is received, the processing circuit 143 of the gain adjusting circuit 104 can output a plurality of second control signals CS2 to the first switch components SW1 and SW2 to turn on the output terminal Mo2 of the second current mirror and the second terminal of the first amplifying transistor 121, and turn on the output terminal Mo3 of the third current mirror and the second terminal of the first amplifying transistor 121. In this way, the first current I1, the second current I2 (the second current mirror is provided according to the first reference current Iref) and the third current I3 (the third current mirror is provided according to the first reference current Iref) are provided simultaneously, so that the first bias current Ibias1 provided by the first current source 223 is increased. It is understood that the second current source 224 may be implemented as a plurality of current mirrors (not shown) like the first current source 223, which is not described herein.
Since the transconductance gm of the first amplifying transistor 121 (or the second amplifying transistor 122) is proportional to the square root of the first bias current Ibias1 (or the second bias current Ibias 2), the transconductance gm of the first amplifying transistor 121 (or the second amplifying transistor 122) increases when the first bias current Ibias1 (or the second bias current Ibias 2) is adjusted by the processing circuit 143 to increase. As a result, based on the above formula (1), when the transconductance gm of the first amplifying transistor 121 (or the second amplifying transistor 122) is increased, the actual gain Ar of the amplifier circuit 102 is increased, and the conventional design gain Ad is close.
Referring to fig. 6, fig. 6 is a schematic circuit diagram of an amplifier 300 according to still another embodiment of the present disclosure, wherein the same or similar components of the amplifier 300 as those of the amplifier 100 are not repeated. During the operation of the amplifier 300, the processing circuit 143 adjusts the first bias current Ibias1 provided by the first current source 323 and the second bias current Ibias2 provided by the second current source 324 according to the detection signal DS to increase the actual gain Ar of the amplifier circuit 102. Specifically, the first current source 323 includes a first current mirror (composed of second transistors M2e and M2 f) and a first variable resistor Rv1, wherein an output terminal Mo1 of the first current mirror is directly coupled to the second terminal of the first amplifying transistor 121, and the first variable resistor Rv1 is respectively coupled to an input terminal Mi1 of the first current mirror and the system high voltage Vcc.
When receiving the detection signal DS, the processing circuit 143 can output the second control signal CS2 to the first variable resistor Rv1 to decrease the resistance of the first variable resistor Rv1, so as to increase the first reference current Iref flowing into the input terminal Mi1 of the first current mirror. The first current mirror increases the supply of the first current I1 according to the increased first reference current Iref, so that the first bias current Ibias1 supplied by the first current source 323 increases. In this way, the actual gain Ar of the amplifier circuit 102 is increased, and the conventional design gain Ad is close. It is understood that the second current source 324 may be implemented as a second current mirror (not shown) and a second variable resistor (not shown) like the first current source 323, which are not described herein.
Referring to fig. 7, fig. 7 is a schematic circuit diagram of an amplifier 400 according to still another embodiment of the present disclosure, wherein the same or similar components of the amplifier 400 as those of the previous embodiment are not repeated. The amplifier circuit 402 in the amplifier 400 is a single-ended amplifier, wherein the first impedance component Z1 is coupled to the second end of the first amplifying transistor 121 and the ground voltage GND, respectively. In the operation process of the amplifier 400, when the processing circuit 143 receives the detection signal DS, the processing circuit 143 outputs the first control signal CS1 to adjust the resistance value of the first impedance component Z1, so as to increase the actual gain Ar of the amplifier circuit 502, which is close to the conventional design gain Ad. It is understood that the processing circuit 143 in the amplifier 400 may also be configured to output a second control signal (not shown) to adjust the first bias current Ibias1 provided by the first current source 123, or to output a third control signal (not shown) to adjust the resistance of the second impedance component Z2.
In the present embodiment, the first amplifying transistor 121, the second amplifying transistor 122, the first transistors M1 a-M1 c and the second transistors M2 a-M2 f are N-type metal oxide semiconductors, however, the disclosure is not limited thereto. In other embodiments, the first amplifying transistor 121, the second amplifying transistor 122, the first transistors M1 a-M1 c and the second transistors M2 a-M2 f can be implemented by P-type metal oxide semiconductor or bipolar transistors.
In summary, by designing the gain adjustment circuit 104, the amplifiers 100 to 400 according to the present disclosure can adjust the actual gain Ar of the amplifier circuits 102 and 402 when the input signal Vin exceeds the first reference voltage Vref, so that the actual gain Ar approaches the design gain Ad originally designed for the amplifier circuits 102 and 402. In this way, the amplifiers 100-400 can maintain the same gain when receiving the input signals Vin with different magnitudes (i.e., the amplifiers 100-400 can maintain the linearity of amplification even if they are affected by the transistor characteristics), so that the back-end circuit can receive undistorted signals.
Although the present invention has been described with reference to the above embodiments, it should be understood that the present invention is not limited thereto, and that various changes, modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the present invention, and therefore, the scope of the present invention is to be defined by the appended claims.
Reference numerals illustrate:
100,200,300,400 amplifier
102,402 Amplifier circuit
104 Gain adjusting circuit
121 First amplifying transistor
122 A second amplifying transistor
123,223,323 First current source
124,224,324: A second current source
141 Comparator
143 Processing circuit
Vin: input signal
Vin +: positive input signal
Vin-negative input signal
Vout output signal
Vref: first reference voltage
Vref+: positive first reference voltage
Vref-negative first reference voltage
Vcc: system high Voltage
GND ground voltage
Actual gain of Ar, ar'
Ad design gain
Z1 first impedance component
Z2 second impedance component
Z3 third impedance component
M1a, M1b, M1c: first transistor
R1a, R1b, R1c is a first resistor
R2a, R2b, R2c is a second resistor
M2a, M2b, M2c, M2d, M2e, M2f, second transistor
Mi1 input terminal
Mo1, mo2 and Mo3, output end
SW1, SW2 first switch assembly
Rv1 first variable resistor
Iref first reference current
I1 first current
I2 second current
I3 third current
DS detection signal
CS1 first control Signal
CS2 second control Signal
Ibias1 first bias current
Ibias2, second bias current
Claims (7)
1. An amplifier, comprising:
An amplifier circuit having a design gain and an actual gain and configured to output an output signal according to an input signal and the actual gain, wherein the amplifier circuit comprises an amplifying transistor and a current source coupled to a second end of the amplifying transistor and configured to provide a bias current, the current source comprises a first current mirror and a second current mirror, an output end of the first current mirror is coupled to the second end of the amplifying transistor, the first current mirror is configured to provide a first current according to a reference current, an output end of the second current mirror is coupled to the second end of the amplifying transistor through a switch element, and the second current mirror is configured to output a second current according to the reference current
A gain adjusting circuit coupled to the amplifier circuit and configured to receive the input signal and compare a voltage of the input signal with a first reference voltage;
Wherein when the voltage of the input signal exceeds the first reference voltage, the gain adjustment circuit increases the actual gain of the amplifier circuit so that the actual gain approaches the design gain;
the gain adjusting circuit is coupled to the switch assembly and is configured to turn on the output terminal of the second current mirror and the second terminal of the amplifying transistor by outputting a second control signal to the switch assembly, so that the first current and the second current are provided simultaneously, thereby increasing the bias current provided by the current source and further increasing the actual gain of the amplifier circuit.
2. The amplifier of claim 1, wherein the amplifier circuit further comprises a first impedance element, a control terminal of the amplifying transistor is configured to receive the input signal, a first terminal of the amplifying transistor is coupled to an output terminal of the amplifier circuit, and the second terminal of the amplifying transistor is coupled to the first impedance element.
3. The amplifier of claim 2, wherein the first impedance element comprises a first transistor, a first terminal or a second terminal of the first transistor is coupled to the second terminal of the amplifying transistor, and the gain adjusting circuit is coupled to a control terminal of the first transistor and is configured to output a first control signal to the control terminal of the first transistor, so as to reduce a resistance value of the first impedance element and thereby increase the actual gain of the amplifier circuit.
4. The amplifier of claim 3, wherein the first impedance component further comprises a first resistor coupled to the first terminal or the second terminal of the first transistor.
5. The amplifier of claim 1, wherein the gain adjustment circuit comprises a comparator and a processing circuit, the comparator is configured to receive the input signal and the first reference voltage, and when the voltage of the input signal exceeds the first reference voltage, the comparator is configured to output a detection signal to the processing circuit, the processing circuit is configured to increase the actual gain of the amplifier circuit according to the detection signal.
6. The amplifier of claim 1, wherein the gain adjustment circuit is further configured to compare the voltage of the input signal with a second reference voltage greater than the first reference voltage, the gain adjustment circuit again increasing the actual gain of the amplifier circuit when the voltage of the input signal exceeds the second reference voltage.
7. The amplifier of claim 1, wherein the amplifier circuit further comprises another amplifier transistor and a first impedance component, the input signal having a positive input signal and a negative input signal, a control terminal of the amplifier transistor receiving the negative input signal, a first terminal of the amplifier transistor being coupled to a positive output terminal of the amplifier circuit, a control terminal of the other amplifier transistor receiving the positive input signal, a first terminal of the other amplifier transistor being coupled to a negative output terminal of the amplifier circuit, the first impedance component being coupled to the second terminal of the amplifier transistor and a second terminal of the other amplifier transistor.
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| CN202110266449.2A CN115085680B (en) | 2021-03-11 | 2021-03-11 | Amplifier |
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| CN202110266449.2A CN115085680B (en) | 2021-03-11 | 2021-03-11 | Amplifier |
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| CN115085680A CN115085680A (en) | 2022-09-20 |
| CN115085680B true CN115085680B (en) | 2025-10-31 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101242162A (en) * | 2007-02-08 | 2008-08-13 | 联发科技（新加坡）私人有限公司 | Variable Gain Amplifier Circuit |
| CN106656086A (en) * | 2016-12-20 | 2017-05-10 | 北京中电华大电子设计有限责任公司 | Automatic gain amplifier circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006132036A1 (en) * | 2005-06-10 | 2006-12-14 | Matsushita Electric Industrial Co., Ltd. | A/d converter |
| US7592869B2 (en) * | 2007-09-17 | 2009-09-22 | Finisar Corporation | Variable gain amplifier having dual gain control |
| KR100937951B1 (en) * | 2008-09-05 | 2010-01-21 | 주식회사 하이닉스반도체 | Calibration circuit, on die termination device, and semiconductor memory device |
| KR101281628B1 (en) * | 2011-11-17 | 2013-07-03 | 고려대학교 산학협력단 | Adaptive equalizer and control method thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101242162A (en) * | 2007-02-08 | 2008-08-13 | 联发科技（新加坡）私人有限公司 | Variable Gain Amplifier Circuit |
| CN106656086A (en) * | 2016-12-20 | 2017-05-10 | 北京中电华大电子设计有限责任公司 | Automatic gain amplifier circuit |
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