CN115061948A - Method and system for verifying non-aligned access in multi-core system - Google Patents

Abstract

The invention relates to the technical field of processors, in particular to a method and system for verifying non-aligned access in a multi-core system, including an access instruction information collector, a storage instruction information collector, an access instruction controller, a storage instruction controller, and an access instruction queue , which stores the instruction queue, memory model, and comparator. The present invention is suitable for multi-core systems. In the multi-core system, there are multiple cores performing non-aligned access, and to ensure data consistency, the verification method can well solve the problem of data consistency. , to verify whether the data consistency of the hardware is correct. For the present invention, if the address attribute of non-aligned access is cacheable, the data can be read from the cache of the core, and the write data is also written into the cache of the core. Read and write data is finally written to the peripheral, and supports unaligned access verification of different address attributes.

Description

Verification method and system for non-aligned access in multi-core system

technical field

The present invention relates to the technical field of processors, in particular to a method and system for verifying unaligned access in a multi-core system.

Background technique

When the processor accesses memory, the address can be aligned or unaligned. Different processor architectures have different operations on unaligned access. The ARM architecture provides control over whether the register configuration supports unaligned access, and the X86 architecture supports unaligned access. The RSICV architecture allows for microarchitectural customization. Address alignment means that when the access size is one word, the lower two bits of the address must be 0. When the access size is two bytes, the lower one bit of the address must be 0. When the access size is one byte, the address is not required.

Address misalignment refers to addresses that do not conform to the above rules. Architectures that do not support unaligned access will generally generate unaligned exceptions when encountering unaligned access, which will be handled by software. Architectures that support unaligned access will generally split unaligned access into multiple aligned accesses. operation, merge the data after obtaining all the data, if it is a write operation, split the write data and write the aligned addresses respectively.

Therefore, the purpose of providing a method in this paper is to verify whether the read data is correct in the process of splitting the unaligned access into multiple accesses, and whether the write data is correctly written into the memory or cache, and at the same time, it supports whether the address attribute is cacheable or uncacheable. Validation of unaligned accesses.

SUMMARY OF THE INVENTION

In view of the deficiencies of the prior art, the present invention discloses a method and system for verifying non-aligned access in a multi-core system, which is used to solve the problem of performing simulation on top-level modeling in a multi-core system, but this method requires a golden model to execute For memory access instructions, for the access instructions after unaligned access splits, it is not easy to grasp the time point of calling the golden model, which may easily cause the problem of premature or over-complete execution of memory access instructions.

The present invention is achieved through the following technical solutions:

In a first aspect, the present invention provides a verification system for non-aligned access in a multi-core system, comprising:

The access command information collector is used to monitor the update of information such as the transmission information, address, access size, address attribute, address alignment and other information of the access command in the DUT;

The storage instruction information collector is used to monitor the update of information such as transmission information, address, write data, access size, address attribute, address alignment and other information of storage instructions in the DUT;

The access command controller is used to control the execution of the access command, and when the controller receives a new access command, the access command is stored in the access command queue;

The storage instruction controller is used to control the execution of the access instruction, and when the controller receives a new storage instruction, the storage instruction is stored in the storage instruction queue;

The access instruction queue is used to store the access instructions executed in the DUT, and the update of the instruction information is kept synchronized with the DUT;

The storage instruction queue is used to store the storage instructions executed in the DUT, and the update of the instruction information is synchronized with the DUT;

The memory model is used to read data from the memory model during read operations, and update data into the memory model during write operations;

The comparator is used to compare whether the data of the access command of the DUT and the verification system are consistent when the access command is submitted, and print the comparison result. When the storage command writes the data to the cache or peripheral, compare the data written by the DUT and the verification system. Write whether the data is consistent, and print the comparison result.

Further, when the access command controller receives the access command information update, it updates the information to the corresponding unit in the access command queue. If the address of the access command is unaligned, the command will be split into two alignments. In the access operation, the address of the access instruction in the DUT will be updated twice, and the controller will record the information of the two addresses and the two access sizes in the access instruction queue.

Further, when the access instruction controller receives the information that the access instruction obtains the data, it first judges that the access is the number of times the data is obtained by the unaligned access. Access the memory model, obtain the first data, store it in the corresponding unit of the access command queue, and save the DUT data at the same time; if the data is obtained for the second time, the controller accesses the memory model according to ma2_addr and the access size, obtains the second data, and The first data and the second data are spliced together, stored in the corresponding unit of the access command queue, and the DUT data is saved at the same time;

Further, when the access command controller receives the access command submission information, it selects the corresponding unit from the access command queue, calls the comparator to compare the data, and deletes the access command from the access command queue after the comparison is completed.

Further, when the storage instruction controller receives the storage instruction information update, it updates the information to the corresponding unit in the storage instruction queue. If the address of the storage instruction is unaligned, the instruction will be split into two alignments. In the storage operation, the address of the storage instruction in the DUT will be updated twice, and the controller will record the information of the two addresses and the two storage sizes in the storage instruction queue.

Further, when the storage instruction controller receives the information that the storage instruction writes data into the cache or peripherals, it first determines that the write operation is the second write operation of the unaligned access. If it is the first write operation, the control The controller writes the corresponding data into the memory model according to ma1_addr and storage size, and calls the comparator to compare the write data of the current DUT to verify whether the write data of the system is the same; if it is the second write operation, the controller according to ma2_addr and storage size, will The corresponding data is written into the memory model, and the comparator is called to compare the write data of the current DUT to verify whether the write data of the system are the same.

In a second aspect, the present invention provides a method for verifying non-aligned access in a multi-core system, the method uses the verification system for non-aligned access in a multi-core system described in the first aspect, and the method is used for non-aligned access instruction verification and unaligned store instruction validation.

Further, when the method performs unaligned access instruction verification, the following steps are included:

The access command information collector monitors the information of the DUT access command, and if it is a newly launched access command, it is stored in the access command queue; if it is the update information of the access command, the information is updated to the corresponding unit in the access command queue;

Determine whether the access is an unaligned access according to the updated address and access size information. If the access size is 2 words, but the lower three bits of the address are not 0, or the access size is 1 word, but the lower two bits of the address are not 0 , or the access size is 2bytes, but the lower one of the address is not 0, these three cases meet the conditions of unaligned access. If it is an unaligned access, go through the unaligned access verification process, if it is an aligned access, go through the aligned access verification process. Under unaligned access, the instruction will be split into two accesses, and the addresses are ma1_addr and ma2_addr, which are recorded in the access instruction queue;

When the access instruction is an unaligned access, the controller judges whether it is a cacheable attribute according to the address attribute. If it is a cacheable attribute, it means that the access data is obtained from the cache. If it is a non-cacheable attribute, it means that the access data is obtained from the peripheral device. ;

When the address attribute is cacheable, the controller monitors the data output signal of the memory access unit in the DUT, and performs the following operations:

a) When monitoring the output of access data, according to the information in the DUT, it is judged that the current output data is obtained by the number of accesses, and the controller selects the corresponding command from the access command queue. If it is the first access, the controller will ma1_addr to access the memory model and get the first data;

b) The controller continues to monitor the access data output, and if it is judged to be the second access, the controller accesses the memory model according to ma2_addr to obtain the second data;

c) The controller merges the first data and the second data together to obtain the data of the final access instruction;

d) Compare the data finally output by the DUT memory access unit and the final data in the verification system, and print the comparison result;

When the address attribute is not cacheable, the controller monitors the access request of the peripheral and performs the following operations:

a) When monitoring the read request of the peripheral device, the controller searches for the access command that initiates the request from the access command queue according to the access address and core id. If the command address is not aligned and no valid data has been obtained, this The second request is the first access, and the controller accesses the memory model according to ma1_addr to obtain the first data;

b) The controller continues to monitor the read request of the peripheral device, and also searches for the corresponding command from the access command queue. If the command address is not aligned and the first data is obtained, this request is the second access. ma2_addr accesses the memory model and obtains the second data;

c) The controller merges the first data and the second data together to obtain the data of the final access instruction;

d) Compare the data finally output by the DUT memory access unit and the final data in the verification system, and print the comparison result;

When the controller detects that the memory access instruction is submitted, it finds the corresponding instruction unit in the access instruction queue, and deletes the unit.

Further, when the method performs unaligned storage instruction verification, the following steps are included:

The access instruction information collector monitors the information of the DUT storage instruction, and if it is a newly launched storage instruction, it is stored in the storage instruction queue; if it is the update information of the storage instruction, the information is updated to the corresponding unit in the storage instruction queue;

Determine whether the access is an unaligned access according to the updated address and access size information. If the access size is 2 words, but the lower three bits of the address are not 0, or the access size is 1 word, but the lower two bits of the address are not 0 , or the access size is 2bytes, but the lower one of the address is not 0, these three cases meet the conditions of unaligned access. If it is an unaligned access, go through the unaligned access verification process, if it is an aligned access, go through the aligned access verification process. Under unaligned access, the instruction will be split into two accesses, the addresses are ma1_addr and ma2_addr, which are recorded in the storage instruction queue;

When the storage instruction is an unaligned access, the controller determines whether it is a cacheable attribute according to the address attribute. If it is a cacheable attribute, it means that the last data needs to be written into the cache; if it is a non-cacheable attribute, it means that the last data needs to be written to the external Assume;

When the address attribute is cacheable, the controller monitors the write request of the L1 cache in the DUT. When the address attribute is not cacheable, the controller monitors the write request of the peripherals in the DUT, and performs the following operations:

a) The controller finds the corresponding instruction from the storage instruction queue according to the address and access size of the write request. If the instruction address is not aligned and has not been written to the cache, the controller writes part of the data into the memory model according to ma1_addr. At the same time, compare the data written by the DUT and verify whether the data written by the system is consistent;

b) The controller continues to monitor the write request of the first-level cache and peripherals. If the corresponding instruction in the storage instruction queue has written data once, the current write request is the second write, and the controller writes another part of the data according to ma2_addr In the memory model, while writing, compare the data written by the DUT and verify whether the data written by the system is consistent;

When the storage instruction is submitted, the controller finds out the corresponding instruction from the storage instruction queue according to the instruction identifier, and deletes the instruction.

The beneficial effects of the present invention are:

The present invention is suitable for multi-core systems. In the multi-core system, there are multiple cores performing non-aligned access, and to ensure data consistency, the verification method can well solve the problem of data consistency. , to verify that the data consistency of the hardware is correct.

For the present invention, if the address attribute of non-aligned access is cacheable, the data can be read from the cache of the core, and the write data is also written into the cache of the core. Read and write data is finally written to the peripheral, and supports unaligned access verification of different address attributes.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

Fig. 1 is the structure diagram of the verification system of the present invention;

2 is a flow chart of the verification of an unaligned access instruction according to an embodiment of the present invention;

FIG. 3 is a flow chart of verification of an unaligned storage instruction according to an embodiment of the present invention.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Example 1

Referring to FIG. 1 , this embodiment provides a verification system for non-aligned access in a multi-core system, including

The access instruction information collector monitors the update of information such as the launch information, address, access size, address attribute, address alignment and other information of the access instruction in the DUT.

In a further embodiment, the time point at which the data can be read in the multi-core system and the time point at which the access command is submitted can be determined, and these information are sent to the access command controller.

The storage instruction information collector monitors the update of the transmission information, address, write data, access size, address attribute, address alignment and other information of the storage instruction in the DUT.

In a further embodiment, the time point at which the write data of the storage instruction is visible to other cores and the time point at which the storage instruction is submitted is stored, and these information are sent to the storage instruction controller.

The access command controller is used to control the execution of the access command. When the controller receives a new access command, it stores the access command in the access command queue.

In this embodiment, when the controller receives the update of the access instruction information, it updates the information to the corresponding unit in the access instruction queue. If the address of the access instruction is not aligned, the instruction will be split into two aligned access operations, and the DUT The address of the access instruction will be updated twice, and the controller will record the two addresses (ma1_addr and ma2_addr) and the information of the two access sizes in the access instruction queue.

In this embodiment, when the controller receives the information that the access instruction obtains the data, it firstly judges that the access is the number of times the data is obtained by the unaligned access. If the data is obtained for the first time, the controller accesses the memory model according to the ma1_addr and the access size, Obtain the data for the first time, store it in the corresponding unit of the access command queue, and save the DUT data at the same time; if the data is obtained for the second time, the controller accesses the memory model according to ma2_addr and the access size, obtains the data for the second time, and stores the data for the first time. The data and the second data are spliced together, stored in the corresponding unit of the access command queue, and the DUT data is saved at the same time.

In this embodiment, when the controller receives the access command submission information, it selects the corresponding unit from the access command queue, calls the comparator to compare the data, and deletes the access command from the access command queue after the comparison is completed.

The storage instruction controller is used to control the execution of the access instruction. When the controller receives a new storage instruction, the storage instruction is stored in the storage instruction queue.

In this embodiment, when the controller receives the update of the storage instruction information, it updates the information to the corresponding unit in the storage instruction queue. If the address of the storage instruction is not aligned, the instruction will be split into two aligned storage operations, and the DUT The address of the storage instruction will be updated twice, and the controller will record the two addresses (ma1_addr and ma2_addr) and the information of the two storage sizes in the storage instruction queue.

In this embodiment, when the controller receives the information that the storage instruction writes data into the cache or the peripheral device, it firstly judges that the write operation is the second write operation of the unaligned access. Storage size, write the corresponding data into the memory model, and call the comparator to compare the write data of the current DUT to verify whether the write data of the system is the same; if the second write operation, the controller writes the corresponding data according to ma2_addr and storage size Memory model, and call the comparator to compare the write data of the current DUT to verify whether the write data of the system is the same.

In this embodiment, when the controller receives the storage instruction submission information, the controller deletes the instruction from the storage instruction queue.

The access instruction queue is used to store the access instructions executed in the DUT. The update of the instruction information is synchronized with the DUT, and at the same time, the result of the verification system executing the access instruction is saved. Each core has an independent access instruction queue.

The storage instruction queue is used to store the storage instructions executed in the DUT. The update of the instruction information is synchronized with the DUT, and at the same time, the result of the verification system executing the storage instruction is saved. Each core has an independent store instruction queue.

Memory model, verify the memory model in the system, read operations read data from the memory model, and write operations update data into the memory model.

The comparator, when the access command is submitted, compares the data of the DUT and the verification system's access command, and prints the comparison result; when the storage command writes the data to the cache or peripheral, compares the DUT's write data and the verification system's write data. Whether it is consistent, and print the comparison result.

The verification system in this embodiment verifies the memory access instructions whose addresses are not aligned, and can verify the correctness of each split instruction, including the correctness of the data obtained by the access instruction and the correctness of the data written by the storage instruction.

The verification system of this embodiment supports the verification of unaligned memory access instructions whose address attributes are cacheable and non-cacheable. Under different address attributes, the monitored instruction perform time points are different. For cacheable memory access instructions, the perform time point is the read-write cache. Time, for non-cacheable memory access instructions, the perform time point is the time when the peripheral receives the read request.

In this embodiment, the verification system is suitable for a multi-core system, and the number of cores can be configured. While verifying the correctness of data, the principle of cache consistency is followed.

Example 2

Referring to FIG. 2 , this embodiment provides an unaligned access instruction verification process, which is as follows:

1. The access command information collector monitors the information of the DUT access command. If it is a newly launched access command, it will be stored in the access command queue; if it is the update information of the access command, it will update the information to the corresponding unit in the access command queue.

2. The controller judges whether the access is an unaligned access according to the updated address and access size information. If the access size is 2 words, but the lower three bits of the address are not 0, or the access size is 1 word, but the address is two lower. The bit is not 0, or the access size is 2bytes, but the lower one of the address is not 0, these three cases meet the conditions of unaligned access.

In this embodiment, if the access is unaligned, the unaligned access verification process is performed, and if the access is aligned, the aligned access verification process is performed.

In this embodiment, under unaligned access, the instruction is split into two accesses, and the addresses are respectively ma1_addr and ma2_addr, which are recorded in the access instruction queue.

3. When the access instruction is an unaligned access, the controller judges whether it is a cacheable attribute according to the address attribute. If it is a cacheable attribute, it means that the access data is obtained from the cache. If it is a non-cacheable attribute, it means that the access data is obtained from the peripheral device. obtained in.

4. When the address attribute is cacheable, the controller monitors the data output signal of the memory access unit in the DUT, and performs the following operations:

a) When monitoring the output of access data, according to the information in the DUT, it is judged that the current output data is obtained by the number of accesses, and the controller selects the corresponding command from the access command queue. If it is the first access, the controller will ma1_addr to access the memory model and get the first data;

b) The controller continues to monitor the access data output, and if it is judged to be the second access, the controller accesses the memory model according to ma2_addr to obtain the second data;

c) The controller merges the first data and the second data together to obtain the data of the final access instruction;

d) Compare the final output data of the DUT memory access unit with the final data in the verification system, and print the comparison result.

5. When the address attribute is not cacheable, the controller monitors the access request of the peripheral and performs the following operations:

a) When monitoring the read request of the peripheral device, the controller searches for the access command that initiates the request from the access command queue according to the access address and core id. If the command address is not aligned and no valid data has been obtained, this The second request is the first access, and the controller accesses the memory model according to ma1_addr to obtain the first data;

b) The controller continues to monitor the read request of the peripheral device, and also searches for the corresponding command from the access command queue. If the command address is not aligned and the first data is obtained, this request is the second access. ma2_addr accesses the memory model and obtains the second data;

c) The controller merges the first data and the second data together to obtain the data of the final access instruction;

d) Compare the final output data of the DUT memory access unit with the final data in the verification system, and print the comparison result.

6. When the controller detects that the memory access instruction is submitted, it finds the corresponding instruction unit in the access instruction queue, and deletes the unit.

Example 3

Referring to FIG. 3 , the present embodiment provides an unaligned storage instruction verification process as follows:

1. The access instruction information collector monitors the information of the DUT storage instruction. If it is a newly launched storage instruction, it will be stored in the storage instruction queue; if it is the update information of the storage instruction, the information will be updated to the corresponding unit in the storage instruction queue.

2. The controller judges whether the access is an unaligned access according to the updated address and access size information. If the access size is 2 words, but the lower three bits of the address are not 0, or the access size is 1 word, but the address is two lower. The bit is not 0, or the access size is 2bytes, but the lower one of the address is not 0, these three cases meet the conditions of unaligned access.

In this embodiment, if the access is unaligned, the unaligned access verification process is performed, and if the access is aligned, the aligned access verification process is performed.

In this embodiment, under unaligned access, the instruction will be split into two accesses, and the addresses are respectively ma1_addr and ma2_addr, both of which are recorded in the storage instruction queue.

3. When the storage instruction is an unaligned access, the controller determines whether it is a cacheable attribute according to the address attribute. If it is a cacheable attribute, it means that the last data needs to be written into the cache. If it is a non-cacheable attribute, it means that the last data needs to be written. into the peripheral.

4. When the address attribute is cacheable, the controller monitors the write request of the first-level cache in the DUT. When the address attribute is not cacheable, the controller monitors the write request of the peripherals in the DUT, and performs the following operations:

a) The controller finds the corresponding instruction from the storage instruction queue according to the address and access size of the write request. If the instruction address is not aligned and has not been written to the cache, the controller writes part of the data into the memory model according to ma1_addr. At the same time, compare the data written by the DUT and verify whether the data written by the system is consistent;

b) The controller continues to monitor the write request of the first-level cache and peripherals. If the corresponding instruction in the storage instruction queue has written data once, the current write request is the second write, and the controller writes another part of the data according to ma2_addr In the memory model, while writing, compare the data written by the DUT and verify whether the data written by the system is consistent;

5. When the storage instruction is submitted, the controller finds out the corresponding instruction from the storage instruction queue according to the instruction identifier, and deletes the instruction.

To sum up, the present invention is suitable for multi-core systems. In a multi-core system, there are situations where multiple cores are accessing non-aligned access, and to ensure data consistency, this verification method can well solve the problem of data consistency. While accessing, verify whether the data consistency of the hardware is correct.

For the present invention, if the address attribute of non-aligned access is cacheable, the data can be read from the cache of the core, and the write data is also written into the cache of the core. Read and write data is finally written to the peripheral, and supports unaligned access verification of different address attributes.

The above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The recorded technical solutions are modified, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (9)

1. A verification system for non-aligned access in a multi-core system includes

The access instruction information collector is used for monitoring the updating of information such as emission information, address, access size, address attribute, address alignment and the like of an access instruction in the DUT;

the storage instruction information collector is used for monitoring the updating of information such as transmission information, addresses, write data, access sizes, address attributes, address alignment and the like of storage instructions in the DUT;

the access instruction controller is used for controlling the execution of the access instruction and storing the access instruction into an access instruction queue when the controller receives a new access instruction;

the storage instruction controller is used for controlling the execution of the access instruction and storing the storage instruction into the storage instruction queue when the controller receives a new storage instruction;

the access instruction queue is used for storing access instructions executed in the DUT, and updating of instruction information keeps synchronization with the DUT;

the storage instruction queue is used for storing storage instructions executed in the DUT, and updating of instruction information keeps synchronization with the DUT;

the memory model is used for reading data from the memory model during read operation and updating the data into the memory model during write operation;

and the comparator is used for comparing whether the data of the access instructions of the DUT and the verification system are consistent or not when the access instructions are submitted and printing the comparison result, and comparing whether the data written by the DUT is consistent with the data written by the verification system or not when the data are written into the cache or the peripheral by the storage instructions and printing the comparison result.

2. The system of claim 1, wherein the access instruction controller receives an access instruction information update, updates information to a corresponding unit in the access instruction queue, if the address of the access instruction is not aligned, the access instruction is disassembled into two aligned access operations, the address of the access instruction in the DUT is updated twice, and the controller records the two addresses and the two access size information in the access instruction queue.

3. The system according to claim 2, wherein when the access command controller receives information that the access command obtains data, it first determines that the access is the data obtained for the second time of the non-aligned access, and if the access obtains data for the first time, the controller accesses the memory model according to ma1_ addr and the access size to obtain the first data, and stores the first data in the corresponding unit of the access command queue, and stores DUT data; if the data are obtained for the second time, the controller accesses the memory model according to the ma2_ addr and the access size to obtain the second data, splices the first data and the second data together, stores the first data and the second data into corresponding units of the access instruction queue, and simultaneously stores DUT data.

4. The system according to claim 2, wherein when the access instruction controller receives the access instruction submission information, the access instruction controller selects the corresponding unit from the access instruction queue, invokes the comparator to compare the data, and deletes the access instruction from the access instruction queue after the comparison is completed.

5. The system of claim 1, wherein the store instruction controller receives an update of store instruction information, updates a corresponding location in the store instruction queue with the information, if the address of the store instruction is not aligned, the store instruction is disassembled into two aligned store operations, the address of the store instruction in the DUT is updated twice, and the controller records the two addresses and the two store sizes in the store instruction queue.

6. The system according to claim 1, wherein when the storage instruction controller receives the information that the storage instruction writes data into the cache or the peripheral device, it first determines that the write operation is the second write operation of the non-aligned access, and if the write operation is the first write operation, the controller writes the corresponding data into the memory model according to ma1_ addr and the storage size, and invokes the comparator to compare whether the write data of the current DUT is the same as the write data of the verification system; if the data is written for the second time, the controller writes corresponding data into the memory model according to the ma2_ addr and the storage size, and calls the comparator to compare whether the write data of the current DUT is the same as the write data of the verification system.

7. A method for verifying non-aligned access in a multi-core system, the method using the system for verifying non-aligned access in a multi-core system according to any one of claims 1 to 6, wherein the method is used for verification of non-aligned access instructions and verification of non-aligned storage instructions.

8. The method for verifying non-aligned access in a multi-core system according to claim 7, wherein the method comprises the following steps when verifying a non-aligned access instruction:

monitoring information of the DUT access instruction by the access instruction information collector, and storing the information into an access instruction queue if the access instruction is newly transmitted; if the access instruction is updated, updating the information to a corresponding unit in the access instruction queue;

and judging whether the access is a non-aligned access according to the updated address and the access size information, wherein if the access size is 2 words, but the lower three bits of the address are not 0, or the access size is 1 word, but the lower two bits of the address are not 0, or the access size is 2bytes, but the lower one bit of the address is not 0, the three conditions are in accordance with the conditions of the non-aligned access. And if the access is the non-aligned access, the non-aligned access verification process is carried out, and if the access is the aligned access, the aligned access verification process is carried out. Under the non-aligned access, the instruction is divided into two accesses, addresses are respectively ma1_ addr and ma2_ addr, and the addresses are recorded in an access instruction queue;

when the access instruction is non-aligned access, the controller judges whether the access instruction is a cacheable attribute according to the address attribute, if the access instruction is the cacheable attribute, the access instruction indicates that the access data is obtained from a cache, and if the access instruction is a non-cacheable attribute, the access instruction indicates that the access data is obtained from an external device;

when the address attribute is cacheable, the controller monitors the data output signal of the memory access unit in the DUT, and the following operations are carried out:

a) when monitoring that the access data are output, judging that the current output data are obtained by accessing for the second time according to the information in the DUT, simultaneously selecting a corresponding instruction from an access instruction queue by a controller, and if the current output data are obtained by accessing the memory model according to ma1_ addr to obtain first data if the current output data are the first access;

b) the controller continuously monitors the access data output, and if the access data output is judged to be the second access, the controller accesses the memory model according to the ma2_ addr to obtain second data;

c) the controller combines the first data and the second data together to obtain the data of the final access instruction;

d) comparing the data finally output by the DUT memory access unit with the data finally output by the verification system, and printing a comparison result;

when the address attribute is not cacheable, the controller monitors the access request of the peripheral equipment and performs the following operations:

a) when a peripheral read request is monitored, the controller searches an access instruction for initiating the request from an access instruction queue according to an access address and a core id, if the instruction addresses are not aligned and effective data are not obtained yet, the request is accessed for the first time, and the controller accesses the memory model according to ma1_ addr to obtain first data;

b) the controller continuously monitors the read request of the peripheral equipment, the corresponding instruction is searched from the access instruction queue in the same way, if the instruction address is not aligned and the first data is obtained, the request is accessed for the second time, and the controller accesses the memory model according to the ma2_ addr to obtain the second data;

c) the controller combines the first data and the second data together to obtain the data of the final access instruction;

d) comparing the data finally output by the DUT memory access unit with the data finally output by the verification system, and printing a comparison result;

when the controller monitors that the access instruction is submitted, the corresponding instruction unit is found in the access instruction queue, and the unit is deleted.

9. The method for verifying non-aligned access in a multi-core system according to claim 7, wherein the method comprises the following steps when verifying the non-aligned storage instruction:

the access instruction information collector monitors information of a DUT storage instruction, and if the information is a newly transmitted storage instruction, the information is stored into a storage instruction queue; if the information is the updating information of the storage instruction, the information is updated to a corresponding unit in the storage instruction queue;

and judging whether the access is a non-aligned access according to the updated address and the access size information, wherein if the access size is 2 words, but the lower three bits of the address are not 0, or the access size is 1 word, but the lower two bits of the address are not 0, or the access size is 2bytes, but the lower one bit of the address is not 0, the three conditions are in accordance with the conditions of the non-aligned access. And if the access is the non-aligned access, the non-aligned access verification process is carried out, and if the access is the aligned access, the aligned access verification process is carried out. Under the condition of non-aligned access, the instruction can be split into two accesses, addresses are respectively ma1_ addr and ma2_ addr, and the addresses are recorded in a storage instruction queue;

when the storage instruction is in non-aligned access, the controller judges whether the storage instruction is a cacheable attribute according to the address attribute, if the storage instruction is the cacheable attribute, the last data is indicated to be written into the cache, and if the storage instruction is a non-cacheable attribute, the last data is indicated to be written into the peripheral;

when the address attribute is cacheable, the controller monitors the write request of a first-level cache in the DUT, and when the address attribute is non-cacheable, the controller monitors the write request of peripheral equipment in the DUT, and the following operations are performed:

a) the controller finds out a corresponding instruction from the storage instruction queue according to the address and the access size of the write request, if the instruction address is not aligned and the cache is not written, the controller writes a part of data into the memory model according to the ma1_ addr, and compares the DUT write data and the verification system write data to be consistent during writing;

b) the controller continuously monitors write requests of the first-level cache and the peripheral equipment, if data are written once by corresponding instructions in the storage instruction queue, the current write request is written for the second time, the controller writes the other part of data into the memory model according to the ma2_ addr, and the data written by the DUT and the data written by the verification system are compared to be consistent during writing;

when the storage instruction is submitted, the controller finds out the corresponding instruction from the storage instruction queue according to the instruction identification and deletes the instruction.

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