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CN115000002A - Manufacturing method of semiconductor device, three-dimensional memory and storage system - Google Patents

Manufacturing method of semiconductor device, three-dimensional memory and storage system Download PDF

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CN115000002A
CN115000002A CN202210569785.9A CN202210569785A CN115000002A CN 115000002 A CN115000002 A CN 115000002A CN 202210569785 A CN202210569785 A CN 202210569785A CN 115000002 A CN115000002 A CN 115000002A
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layer
opening
contact hole
forming
mask
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曾臻
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H10W20/069—
    • H10W70/611—
    • H10W70/65—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明提供了一种半导体器件的制作方法、三维存储器及存储系统，半导体器件的制作方法，包括：形成半导体结构，半导体结构包括衬底、位于衬底上的堆叠结构和第一介质层，堆叠结构包括台阶结构、停止层、第二介质层，台阶结构包括层叠设置的栅极层和绝缘层；在台阶区形成第一台阶接触孔，第一台阶接触孔贯穿第一介质层和第二介质层并延伸到停止层；在第一介质层上形成掩膜层；形成包括第一台阶接触孔的第二台阶接触孔，第二台阶接触孔贯穿停止层并延伸到各相对应的栅极层；于第一介质层中形成第一开口；其中，第二台阶接触孔和第一开口在同一刻蚀步骤中形成。通过使第二台阶接触孔和第一开口在同一刻蚀步骤中形成，减少工艺步骤和降低成本。

Figure 202210569785

The invention provides a manufacturing method of a semiconductor device, a three-dimensional memory and a storage system, and the manufacturing method of a semiconductor device, comprising: forming a semiconductor structure, the semiconductor structure includes a substrate, a stack structure on the substrate and a first dielectric layer, and the stacking The structure includes a stepped structure, a stop layer, and a second dielectric layer, and the stepped structure includes a gate layer and an insulating layer arranged in layers; a first stepped contact hole is formed in the stepped area, and the first stepped contact hole penetrates the first dielectric layer and the second dielectric layer. forming a mask layer on the first dielectric layer; forming a second step contact hole including a first step contact hole, and the second step contact hole penetrates the stop layer and extends to each corresponding gate layer ; forming a first opening in the first dielectric layer; wherein, the second step contact hole and the first opening are formed in the same etching step. By forming the second step contact hole and the first opening in the same etching step, process steps and costs are reduced.

Figure 202210569785

Description

Manufacturing method of semiconductor device, three-dimensional memory and storage system
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device, a three-dimensional memory and a storage system.
Background
In recent years, development of Flash memories (Flash memories) has been particularly rapid. The main characteristic of flash memory is that it can keep the stored information for a long time without power-up, and it has the advantages of high integration level, fast access speed, easy erasing and rewriting, so it is widely used in microcomputer, automation control and other fields. In this context, three-dimensional memories (e.g., 3D NAND Flash) have been developed in response to the difficulties encountered with flat Flash memories and the pursuit of lower production costs per unit cell. The three-dimensional memory is formed with a plurality of layers of data storage units which are alternately stacked, and a planar structure is converted into a three-dimensional structure, so that the storage density and the integration level of the three-dimensional memory are improved. The three-dimensional memory can support accommodating higher storage capacity in a smaller space, thereby bringing about great cost saving, energy consumption reduction and great performance improvement to comprehensively meet the requirements of numerous consumer mobile devices and the enterprise deployment with the most severe requirements.
As the number of stacked layers of the three-dimensional memory increases, the difficulty of the process for forming the three-dimensional memory becomes greater and greater, which results in a decrease in yield and reliability of the three-dimensional memory. Meanwhile, the process steps and the process costs for forming the three-dimensional memory are increased. Therefore, there is a need to continually optimize the process of forming three-dimensional memory to continually reduce the number of process steps and cost.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, a three-dimensional memory and a storage system, so as to reduce the process steps and the cost.
In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device, including: forming a semiconductor structure, wherein the semiconductor structure comprises a substrate, a stacked structure and a first dielectric layer, the stacked structure and the first dielectric layer are positioned on the substrate, the stacked structure comprises a step area and a storage area which are distributed in the transverse direction parallel to the substrate, the stacked structure comprises a step structure, a stop layer and a second dielectric layer, the step structure comprises a gate layer and an insulating layer which are arranged in a step mode in a stacked mode, the stop layer completely covers the step structure, and the second dielectric layer covers the stop layer; forming a first step contact hole in the step area, wherein the first step contact hole penetrates through the first dielectric layer and the second dielectric layer and extends to the stop layer; forming a mask layer on the first medium layer, wherein the mask layer is provided with a first mask layer opening and a second mask layer opening, and the first mask layer opening corresponds to the first step contact hole; forming a second step contact hole including the first step contact hole according to the opening of the first mask layer, wherein the second step contact hole penetrates through the stop layer and extends to each corresponding gate layer; forming a first opening in the first dielectric layer according to the second mask layer opening; wherein the second step contact hole and the first opening are formed in the same etching step.
The step of forming the semiconductor structure further includes forming a channel structure which penetrates through the stacked structure and extends toward the substrate, and the method for manufacturing the semiconductor device further includes:
a channel contact block is formed in the first opening, the channel contact block being in communication with the channel structure.
Wherein, after the step area forms the first step contact hole, still include:
and cleaning the first step contact hole.
Wherein, after forming the first opening in the first dielectric layer according to the second mask layer opening, the method further comprises:
and filling the second step contact hole and the first opening respectively.
Wherein, form the mask layer on the first dielectric layer, before the mask layer has first mask layer opening and second mask layer opening corresponding to first step contact hole, still include:
and providing a mask plate, wherein the mask plate is provided with a first mask plate opening and a second mask plate opening, the first mask plate opening corresponds to the first mask layer opening, and the second mask plate opening corresponds to the second mask layer opening.
Wherein the material of the stop layer comprises carbon-doped nitride.
Wherein the carbon content of the stop layer is greater than 5%.
Wherein the thickness of the stop layer in a longitudinal direction perpendicular to the substrate is greater than 100 nm.
In order to solve the above problem, an embodiment of the present application further provides a three-dimensional memory, which includes an array memory structure and a peripheral circuit, wherein the array memory structure includes a semiconductor device formed by the method for manufacturing a semiconductor device according to any one of the above embodiments.
In order to solve the above problem, an embodiment of the present application further provides a memory system, where the memory system includes a controller and a three-dimensional memory, the controller is coupled to the three-dimensional memory and is configured to control the three-dimensional memory to store data, and the three-dimensional memory includes a semiconductor device formed by the method for manufacturing a semiconductor device according to any one of the above embodiments.
The invention has the beneficial effects that: the invention provides a manufacturing method of a semiconductor device, a three-dimensional memory and a storage system, which is different from the prior art, wherein the manufacturing method of the semiconductor device comprises the following steps: forming a semiconductor structure, wherein the semiconductor structure comprises a substrate, a stacked structure and a first dielectric layer, the stacked structure and the first dielectric layer are positioned on the substrate, the stacked structure comprises a step area and a storage area which are distributed in the transverse direction parallel to the substrate, the stacked structure comprises a step structure, a stop layer and a second dielectric layer, the step structure comprises a gate layer and an insulating layer which are arranged in a step mode in a stacked mode, the stop layer completely covers the step structure, and the second dielectric layer covers the stop layer; forming a first step contact hole in the step area, wherein the first step contact hole penetrates through the first dielectric layer and the second dielectric layer and extends to the stop layer; forming a mask layer on the first medium layer, wherein the mask layer is provided with a first mask layer opening and a second mask layer opening, and the first mask layer opening corresponds to the first step contact hole; forming a second step contact hole including the first step contact hole according to the opening of the first mask layer, wherein the second step contact hole penetrates through the stop layer and extends to each corresponding gate layer; forming a first opening in the first dielectric layer according to the second mask layer opening; wherein the second step contact hole and the first opening are formed in the same etching step. The method of the invention enables the second step contact hole and the first opening to be formed in the same etching step, thereby achieving the purposes of reducing the process steps and reducing the cost.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 2a to fig. 2e are schematic structural diagrams of steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a schematic block diagram of a storage system in an embodiment of the invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.
It will be understood that when an element is referred to as being "on," "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. Other words used to describe the relationship between components should be interpreted in a similar manner.
As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer may extend over the entire underlying or overlying structure, or may have an extent less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers above, and/or below it. The layer may comprise a plurality of layers. For example, the interconnect layers may include one or more conductive layers and contact layers (in which contacts, interconnect lines, and one or more dielectric layers are formed).
As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate such that the array structure extends in a vertical direction relative to the substrate; "vertical" refers to a direction perpendicular to the substrate.
It should be noted that the drawings provided in the embodiments of the present invention are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in the actual implementation, the type, quantity and proportion of the components in the actual implementation can be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, in which a specific flow chart is compared with the structure charts in fig. 2a to fig. 2e, the method may include the following steps:
s101, a step: a semiconductor structure is formed, the semiconductor structure comprises a substrate 110, a stack structure 120 and a first dielectric layer 130, the stack structure 120 comprises a step region and a storage region (a1 region and a2 region respectively) distributed in a transverse direction (X direction) parallel to the substrate 110, the stack structure 121 comprises a step structure 121, a stop layer 140 and a second dielectric layer 150, the step structure 121 comprises a gate layer 1211 and an insulating layer 1212 which are stacked in a step form, the stop layer 140 completely covers the step structure 121, and the second dielectric layer 150 covers the stop layer 140.
In addition, it should be noted that fig. 2a to 2e only show the structures related to the content of the embodiments of the present invention, and the semiconductor device of the present invention may further include other components and/or structures for realizing the complete functions of the device.
Fig. 2a shows the structure formed in step S101, which includes: a substrate 110, a stacked structure 120 on the substrate 110, and a first dielectric layer 130. The stacked structure 120 includes a step region and a storage region (a1 region and a2 region, respectively) distributed in a lateral direction (X direction) parallel to the substrate 110, a stop layer 140 completely covering the step structure 121, and a second dielectric layer 150 covering the stop layer 140. The step structure 121 includes a gate layer 1211 and an insulating layer 1212 stacked in a step.
Specifically, the substrate 110 may be a semiconductor substrate, and for example, may be a Silicon (Si), Germanium (Ge), SiGe substrate, Silicon On Insulator (SOI), Germanium On Insulator (GOI), or the like. In other embodiments, the semiconductor substrate may also be a substrate 110 including other element semiconductors or compound semiconductors, and may also be a stacked structure, such as Si/SiGe or the like. In addition, one or more layers may be formed below the substrate 110, for example, as shown in fig. 2a, a nitride layer 111 is formed below the substrate 110. The nitride film 111 may be formed in one or more layers in a specific area below the substrate 110 or in the entire substrate 110 to improve the wafer warpage of the device, or based on other functional requirements. In addition, one or more other film layers may be formed below the substrate 110 based on other process requirements, and are not particularly limited.
Specifically, a specific formation process of the semiconductor structure may be that, after the substrate 110 is provided, first, a stacked layer (not shown in the drawings) including a sacrificial layer (not shown in the drawings) and an insulating layer 1212 that are alternately stacked may be formed on the substrate 110 through a deposition process. Then, the stacked layer having the stepped structure 121, i.e., the sacrificial layer and the insulating layer 1212 alternately stacked in a stepped manner are formed at an outer side of the stacked layer, may be formed by a photo process (photo), a trim process (trim), an etch process (etch), and the like. Then, a stop layer 140 completely covering the steps of the stepped structure 121, a second dielectric layer 150 covering the stepped structure 121 and the stop layer 140, and a first dielectric layer 130 covering the stack layer may be formed on the stepped structure 121 through a deposition process. Finally, the original sacrificial layer may be removed, and a gate layer 1211 may be formed at the location of the original sacrificial layer, thereby forming the semiconductor structure shown in fig. 2 a. At this time, the stack structure 120 including the gate electrode layers 1211 and the insulating layers 1212 alternately stacked is formed. In addition, it should be noted that, in the process of forming the semiconductor structure shown in fig. 2a, other structures, such as a Gate Line Slit (Gate Line Slit), etc., are also formed, and are not specifically described since they are not the main point of the present invention.
S102, a step: a first step contact hole 171 is formed at the step region, and the first step contact hole 171 penetrates the first dielectric layer 130 and the second dielectric layer 150 and extends to the stop layer 140.
Wherein the material of the stop layer 140 comprises carbon-doped nitride.
Fig. 2b shows the structure formed in step S102, which includes: a substrate 110, a stacked structure 120 on the substrate 110, and a first dielectric layer 130. The stacked structure 120 includes a step structure 121, a stop layer 140 completely covering the step structure 121, a second dielectric layer 150 covering the stop layer 140, and a first step contact hole 171 in the second dielectric layer 150. The first step contact hole 171 penetrates through the second dielectric layer 150 and extends to the stop layer 140.
Specifically, the first step contact hole 171 may be formed at the step region (a1 region) by an etching process, such as dry etch (dry etch), and the first step contact hole 171 penetrates the first and second dielectric layers 130 and 150 and extends to the stop layer 140. Typically, the material of the first dielectric layer 130 and the second dielectric layer 150 is an oxide, such as silicon oxide (SiO) 2 ). The material of the stop layer 140 may include carbon-doped nitride, and since the materials of the first dielectric layer 130, the second dielectric layer 150 and the stop layer 140 are different, a first step contact is formed by removing the first dielectric layer 130 and the second dielectric layer 150 by dry etchingFor the holes 171, the etching gas can be selected by selecting the etching gas, such as the etching gas with smaller carbon fluorine ratio (ratio of carbon element to fluorine element, C/F), for example, carbon tetrafluoride (CF) 4 ) Or fluoromethane (CH) 3 F) As an etching gas, the selection ratio of the first dielectric layer 130 and the second dielectric layer 150 relative to the stop layer 140 is relatively high (for example, the selection ratio is greater than 1), that is, during etching, the etching speed of the first dielectric layer 130 and the second dielectric layer 150 is relatively high, while the etching speed of the stop layer 140 is relatively low, even the stop layer 140 is not etched substantially, at this time, the stop layer 140 may serve as a layer (stop layer) for stopping etching, so that the first step contact hole 171 is formed in the step region, and the first step contact hole 171 penetrates through the first dielectric layer 130 and the second dielectric layer 150 and extends to the stop layer 140.
Wherein the carbon content of the stop layer 140 is greater than 5%.
Specifically, the stacked layer includes sacrificial layers and insulating layers 1212 alternately stacked, the insulating layers 1212 serve to separate the sacrificial layers, and the material of the insulating layers 1212 may be made of an oxide such as silicon oxide (SiO) 2 ) And the material of the sacrificial layer may be composed of a nitride, such as silicon nitride (SiN). Because the sacrificial layer is mostly made of nitride, and the insulating layer is mostly made of oxide, after the nitride layer is formed, the nitride layer with a certain thickness can be oxidized to form the oxide layer with a certain thickness, and the steps are sequentially repeated, so that a certain number of stacked layers including the sacrificial layer and the insulating layer 1212 which are alternately stacked are formed. As can be seen from the above, the original sacrificial layer may be removed, and the gate layer 1211 may be formed at the position of the original sacrificial layer, thereby forming the semiconductor structure shown in fig. 2 a. In general, the sacrificial layer in the stacked structure 120 may be removed by using hot phosphoric acid, i.e., the hot phosphoric acid may react with the material nitride of the sacrificial layer, thereby removing the sacrificial layer. The material of the stop layer 140 includes carbon-doped nitride, and since the stop layer 140 contains carbon, phosphoric acid cannot react with carbon in the stop layer 140, so that the stop layer 140 is not substantially damaged when the sacrificial layer is removed. Preferably, the stop layer 140 has a carbon content greater than 5% in order to ensure that the stop layer 140 is not damaged when the sacrificial layer is removed。
Wherein the thickness of the stop layer 140 in the longitudinal direction (Z direction) perpendicular to the substrate 110 is more than 100 nm.
Specifically, since the first step contact hole 171 is formed in the step region, and the first step contact hole 171 penetrates through the first dielectric layer 130 and the second dielectric layer 150 and extends to the stop layer 140, a certain damage may be caused to the stop layer 140 during the etching process, in order to ensure that the stop layer 140 is not etched through when the first step contact hole 171 is formed, and then stops on the gate layer 1211 below the stop layer 140, and thus the device is electrically failed, it is preferable that the thickness L1 of the stop layer 140 in the longitudinal direction (Z direction) is greater than 100 nm.
Wherein, in step S102: after the step region forms the first step contact hole 171, the method further includes:
the first step contact hole 171 is subjected to a cleaning process.
Specifically, after the first step contact hole 171 is formed at the step region by an etching process, there may be residues of an etching reaction, such as a polymer (polymer), at sidewalls and a bottom wall of the first step contact hole 171. By cleaning the first step contact hole 171, the residues on the sidewall and the bottom wall of the first step contact hole 171 are removed, which is beneficial to the subsequent etching process or other processes. Meanwhile, the formation of defects (defects) caused by residues is avoided, and the electrical performance of the device is prevented from being influenced.
S103, a step: a mask layer 180 is formed on the first dielectric layer 130, the mask layer 180 having a first mask layer opening 1811 and a second mask layer opening 1812, the first mask layer opening 1811 corresponding to the first step contact hole 171.
Fig. 2c shows the structure formed in step S103, which includes: the semiconductor device includes a substrate 110, a stack structure 120 on the substrate 110, a first dielectric layer 130, and a mask layer 180. The stacked structure 120 includes a step structure 121, a stop layer 140 completely covering the step structure 121, a second dielectric layer 150 covering the stop layer 140, and a first step contact hole 171 in the second dielectric layer 150. The first step contact hole 171 penetrates through the second dielectric layer 150 and extends to the stop layer 140. The mask layer 180 includes a photoresist layer 181 and a hard mask layer 182, and the mask layer 180 has a first mask layer opening 1811 and a second mask layer opening 1812.
Specifically, a mask layer 180 may be formed on the first dielectric layer 130, and then a first mask layer opening 1811 and a second mask layer opening 1812 may be formed on the mask layer 180. The first mask layer opening 1811 corresponds to the first stepped contact hole 171, and the first mask layer opening 1811 is used for subsequent etching of the formed first stepped contact hole 171. The Mask layer 180 may only include the photoresist layer 181, or include the photoresist layer 181 and the Hard Mask layer 182(Hard Mask), and in general, when deep hole etching is performed, the photoresist layer 181 and the Hard Mask layer 182 may be selected as the Mask layer 180 in order to protect a film layer that does not need to be etched from being damaged. The hard mask is an inorganic thin film material formed by Chemical Vapor Deposition (CVD), and its main components are usually titanium nitride (TiN), silicon nitride (SiN), and silicon oxide (SiO) 2 ) And the like, which are mainly applied to the photolithography process, the pattern on the mask is transferred to the photoresist layer 181 through the photolithography process, that is, the patterned photoresist layer 181 is formed, then, the pattern of the photoresist is transferred to the hard mask layer 182 through the etching process, and then, the pattern is etched and transferred to the film layer to be etched through the hard mask layer 182.
In addition, due to the optical reflection effect on the surface of the substrate 110, the reflected light and the incident light interfere with each other, and a standing wave effect and multiple exposure are formed inside the photoresist, so that the critical dimension of the pattern cannot be controlled, and the etching precision is reduced. Preferably, a Bottom Anti-Reflective Coating (BARC) layer may be added between the photoresist layer 181 and the hard mask layer 182, and the main components thereof are a crosslinkable resin, a thermal acid generator, a surfactant, and a solvent, so as to reduce reflection and effectively improve standing wave effect and multiple exposure.
Wherein, in step S103: before forming the mask layer 180 on the first dielectric layer 130, the mask layer 180 having the first mask layer opening 1811 and the second mask layer opening 1812 corresponding to the first step contact hole 171, further includes:
a reticle (not shown in the figures) is provided having first reticle openings (not shown in the figures) corresponding to the first mask layer openings 1811 and second reticle openings (not shown in the figures) corresponding to the second mask layer openings 1812.
Specifically, a pattern on a mask (also referred to as a reticle) may be transferred onto the mask layer 180 through a photolithography process to form a first mask layer opening 1811 and a second mask layer opening 1812 on the mask layer 180. A mask having a first mask opening 1811 corresponding to the first mask layer opening 1811 and a second mask opening 1812 corresponding to the second mask layer opening 1812 may be provided, and a pattern on the mask may be transferred onto the mask layer 180 through a photolithography process, so as to simultaneously form the first mask layer opening 1811 and the second mask layer opening 1812 on the mask layer 180. The structure of the mask used for forming the second mask layer opening 1812 can be improved, so that the improved mask can be used for simultaneously forming the first mask layer opening 1811 and the second mask layer opening 1812 without adding a new mask, and the purposes of reducing the process steps and reducing the cost are achieved.
And S104: the second stepped contact holes 170 including the first stepped contact hole 171 are formed according to the first mask layer openings 1811, and the second stepped contact holes 170 penetrate the stop layer 140 and extend to the respective corresponding gate electrode 1211.
Fig. 2d shows the structure formed in step S104, which includes: the semiconductor device includes a substrate 110, a stack structure 120 on the substrate 110, a first dielectric layer 130, and a mask layer 180. The stacked structure 120 includes a step structure 121, a stop layer 140 completely covering the step structure 121, a second dielectric layer 150 covering the stop layer 140, and a second step contact hole 170 in the second dielectric layer 150. The second step contact holes 170 penetrate through the second dielectric layer 150 and the stop layer 140 and extend to the corresponding gate electrode 1211, including the first step contact holes 171 and the etching holes 172 formed in step S104.
Specifically, the second stepped contact holes 170 including the first stepped contact holes 171 may be formed through an etching process according to the first mask layer openings 1811, and the second stepped contact holes 170 penetrate the stop layer 140 and extend to the respective corresponding gate electrode layers 1211. In general, the material of the gate layer 1211 is a metal conductive material, such as tungsten (W), the material of the stop layer 140 may be a material including carbon-doped nitride, and accordingly, the etching selectivity of the stop layer 140 with respect to the gate layer 1211 can be increased by selecting a suitable etching gas based on the materials of the stop layer 140 and the gate layer 1211, that is, when etching is performed, the etching speed of the stop layer 140 is increased, the etching speed of the gate layer 1211 is decreased, or even the gate layer 1211 is not substantially etched, so that the stop layer 140 is partially removed and extends to each corresponding gate layer 1211, thereby forming the second step contact hole 170 including the first step contact hole 171.
And S105: forming a first opening 190 in the first dielectric layer 130 according to the second mask layer opening 1812; wherein the second stepped contact hole 170 and the first opening 190 are formed in the same etching step.
Fig. 2d shows the structure formed in step S105, which includes: the semiconductor device includes a substrate 110, a stack structure 120 on the substrate 110, a first dielectric layer 130, a first opening 190 in the first dielectric layer 130, and a mask layer 180. The stacked structure 120 includes a step structure 121, a stop layer 140 completely covering the step structure 121, a second dielectric layer 150 covering the stop layer 140, and a second step contact hole 170 in the second dielectric layer 150. The second step contact holes 170 penetrate through the second dielectric layer 150 and the stop layer 140 and extend to the corresponding gate electrode 1211, including the first step contact holes 171 and the etching holes 172 formed in step S104.
Specifically, the first opening 190 may be formed in the first dielectric layer 130 by an etching process according to the second mask layer opening 1812. In order to form the first opening 190 and the second step contact hole 170 in the same etching step, after the structure of the mask used for forming the second mask layer opening 1812 is improved, some parameters in the etching process for forming the first opening 190 need to be adjusted. The depth of the second step contact hole 170 including the first step contact hole 171 is L1 of the thickness of the stop layer 140 in the longitudinal direction (Z direction), and the depth of the first opening 190 is related to the actually required depth of the first opening 190, generally, the thickness of the etch stop layer 140 is required to be different from the depth of the first opening 190, and therefore, some parameters in the etching process for forming the first opening 190 need to be adjusted, so that the first opening 190 and the second step contact hole 170 are formed in the same etching step. By forming the second step contact hole 170 and the first opening 190 in the same etching step, both the process steps and the cost are reduced.
Specifically, the first opening 190 may be a structure having an opening formed after the second step contact hole 170 is formed and before the second step contact hole 170 is filled, that is, the structure of the mask and the etching process for forming the first opening 190 in the subsequent process may be improved by the mask and the etching process, and some parameters in the etching process for forming the first opening 190 may be adjusted, so that the second step contact hole 170 and the first opening 190 are formed in the same etching step, thereby achieving the purposes of reducing the process steps and reducing the cost.
Specifically, in some embodiments, in order to save the cost of the mask, the contact holes for the step region and the storage region can be formed by one mask in the same etching step, however, the biggest challenge in this way is to ensure that the contact holes formed in the step region are just above each corresponding gate layer 1211, rather than etching through the gate layer 1211, and thus, the leakage between the gate layer 1211 and the adjacent gate layer 1211 is caused. In response to the requirement, in the embodiment of the invention, a stop layer 140 (which may be an NDC thin film, a material of the NDC thin film includes carbon-doped nitride) is formed on the step structure 121 to completely cover the step of the step structure, so that a first step contact hole 171 penetrating through the second dielectric layer 150 and extending to the stop layer is formed first, and then, a second step contact hole 170 including the first step contact hole 171 is formed by etching downward from the bottom of the first step contact hole 171, thereby ensuring communication between the second step contact hole 170 and each corresponding gate layer 1211, and further improving yield and reliability of the device.
Wherein, in step S105: after forming the first opening 190 in the first dielectric layer 130 according to the second mask layer opening 1812, the method further includes:
s106, a step: the second step contact hole 170 and the first opening 190 are filled, respectively.
Fig. 2e shows the structure formed in step S106, which includes: the semiconductor device includes a substrate 110, a stack structure 120 on the substrate 110, a first dielectric layer 130, a first opening filling block 191 in the first dielectric layer 130, and a mask layer 180. The stacked structure 120 includes a step structure 121, a stop layer 140 completely covering the step structure 121, a second dielectric layer 150 covering the stop layer 140, and a second step contact 173 located in the second dielectric layer 150. The second step contact 173 extends through the second dielectric layer 150 and the stop layer 140 and extends to each corresponding gate layer 1211. The second stepped contact hole 170 and the first opening 190 may be filled by a deposition process to form a second stepped contact block 173 and a first opening filling block 191, respectively. Typically, the fill material filling the second stepped contact hole 170 and the first opening 190 is a conductive material, such as tungsten (W).
The step of forming the semiconductor structure further includes forming a channel structure 160 that penetrates through the stacked structure 120 and extends toward the substrate 110, and the method for manufacturing a semiconductor device further includes:
a channel contact block (i.e., a first opening fill block 191) is formed in the first opening 190 and is in communication with the channel structure 160.
Specifically, as can be seen from the above, the first opening 190 may be a structure having an opening formed after the second stepped contact hole 170 is formed and before the second stepped contact hole 170 is filled, and the first opening 190 may be a channel contact hole located above the channel structure 160. When the first opening 190 serves as a channel contact hole, the step of forming the semiconductor structure should further include forming a channel structure 160 extending through the stacked structure 120 and toward the substrate 110 as shown in fig. 2 d. After forming the first opening 190, a channel contact block may also be formed in the first opening 190, the channel contact block being in communication with the channel structure 160. In which a channel structure is used as a data storage unit of a semiconductor device for realizingAnd (4) a data storage function. Typically, the channel structure 160 includes a blocking layer, a charge trapping layer, and a tunneling layer. Typically, a channel contact hole (channel contact) is located above the channel structure 160, and a conductive plug 161 is further formed between the channel contact hole and the channel structure 160, and a material of the conductive plug 161 may have polysilicon doped with N-type material or P-type material. The structure of the mask for forming the first opening 190 is modified so that the mask is used to form a first mask layer opening 1811 and a second mask layer opening 1812 corresponding to the formation of the second step contact hole 170 and the first opening 190 in the same etching step. After the structure of the mask is improved, parameters in the etching process for forming the channel contact hole are adjusted. For example, when forming the trench contact hole by dry etching, it is possible to select a suitable etching gas, for example, a gas having a large carbon-fluorine ratio (ratio of carbon element to fluorine element, C/F) such as perfluoropropane (C/F) 3 F 8 ) As an etching gas, the etching selectivity of the first dielectric layer 130 to the conductive plug 161 is greater than 1, the etching selectivity of the stop layer 140 to the gate layer 1211 is greater than 1, i.e., the stop layer 140 is etched faster and the gate layer 1211 is etched slower, or even the gate layer 1211 is not etched substantially, so that the stop layer 140 is removed and extends to the corresponding second-step contact hole 170 of the gate layer 1211. Meanwhile, since the etching selection ratio of the first dielectric layer 130 to the conductive plug 161 is greater than 1, that is, the etching speed of the first dielectric layer 130 is higher, the etching speed of the conductive plug 161 is lower, and even the conductive plug 161 is not etched basically, the first dielectric layer 130 is removed, and a channel contact hole is formed above the channel structure 160. Besides selecting proper etching gas, according to actual process requirements, other parameters for forming the first opening 190 and the second step contact hole 170 can be adjusted in some adaptability, so that the second step contact hole 170 and the first opening 190 are formed in the same etching step, and the purposes of reducing process steps and reducing cost are achieved.
In addition, when the first opening 190 is not used as a channel contact hole, but is used as an opening in other process flows, the second step contact hole 170 and the first opening 190 can be formed in the same etching step by adjusting etching process parameters, such as etching gas and reaction time, in the process of forming the first opening 190, so that the purposes of reducing the process steps and reducing the cost are achieved. For example, when the first opening 190 is an opening with a certain depth, the etching selectivity of the stop layer 140 with respect to the gate layer 1211 is greater than 1 by selecting a suitable etching gas, and the etching gas can etch the first dielectric layer 130, so that when the stop layer 140 is removed by etching and extends to the gate layer 1211, the etching gas does not substantially react with the material of the gate layer 1211, so that the second step contact hole 170 is formed to penetrate through the stop layer 140 and extend to the corresponding gate layer 1211. Meanwhile, the reaction time is controlled, so that the formed first opening 190 can reach a certain depth, the second step contact hole 170 and the first opening 190 are formed in the same etching step, and the purposes of reducing the process steps and reducing the cost are achieved. It is understood that the depth of the first opening 190 should not differ greatly from the thickness of the stop layer 140 to ensure that the gate layer 1211 is not etched through when forming the first opening 190 or that the depth of the first opening is within a specified range when forming the second step contact hole 170.
The embodiment of the application also provides a three-dimensional memory, which comprises an array memory structure and peripheral circuits, wherein the array memory structure comprises a semiconductor device formed by the manufacturing method of the semiconductor device in any one of the above.
Specifically, the three-dimensional memory (3D NAND Flash) includes an Array memory structure (Array) and a peripheral Circuit (peripheral Circuit), and the semiconductor device formed by the method for manufacturing the semiconductor device is located in the peripheral Circuit, where the Array memory structure is used for storing information, and the peripheral Circuit may be located above or below the Array memory structure or located around the Array memory structure, and the peripheral Circuit is used for controlling the corresponding Array memory structure. In addition, the semiconductor device can also be applied to other microelectronic devices, such as a non-volatile Flash (Nor Flash), and the like, without limitation.
The embodiment of the application also provides a storage system, which comprises a controller and a three-dimensional memory, wherein the controller is coupled to the three-dimensional memory and is used for controlling the three-dimensional memory to store data, and the three-dimensional memory comprises a semiconductor device formed by the manufacturing method of the semiconductor device.
Specifically, as shown in FIG. 3, the memory system 200 includes a controller 210 and one or more three-dimensional memories 220, wherein the three-dimensional memories 220 include one or more array memory structures 221 and peripheral circuitry 222. The storage system 200 may communicate with the host 300 through the controller 210, wherein the controller 210 may be connected to the one or more three-dimensional memories 220 via channels in the one or more three-dimensional memories 220. Each three-dimensional memory 220 may be managed by the controller 210 via channels in the three-dimensional memory 220.
According to the foregoing, an embodiment of the present invention discloses a method for manufacturing a semiconductor device, a three-dimensional memory and a storage system, wherein the method for manufacturing the semiconductor device includes: forming a semiconductor structure, wherein the semiconductor structure comprises a substrate, a stacked structure and a first dielectric layer, the stacked structure and the first dielectric layer are positioned on the substrate, the stacked structure comprises a step area and a storage area which are distributed in the transverse direction parallel to the substrate, the stacked structure comprises a step structure, a stop layer and a second dielectric layer, the step structure comprises a gate layer and an insulating layer which are arranged in a step mode in a stacked mode, the stop layer completely covers the step structure, and the second dielectric layer covers the stop layer; forming a first step contact hole in the step area, wherein the first step contact hole penetrates through the first dielectric layer and the second dielectric layer and extends to the stop layer; forming a mask layer on the first medium layer, wherein the mask layer is provided with a first mask layer opening and a second mask layer opening, and the first mask layer opening corresponds to the first step contact hole; forming a second step contact hole including the first step contact hole according to the opening of the first mask layer, wherein the second step contact hole penetrates through the stop layer and extends to each corresponding gate layer; forming a first opening in the first dielectric layer according to the second mask layer opening; wherein the second step contact hole and the first opening are formed in the same etching step. The method of the invention enables the second step contact hole and the first opening to be formed in the same etching step, thereby achieving the purposes of reducing the process steps and reducing the cost.
The above description of the embodiments is only for helping understanding the technical solution of the present invention and its core idea; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. A method for manufacturing a semiconductor device, the method comprising:
forming a semiconductor structure, wherein the semiconductor structure comprises a substrate, a stacked structure and a first dielectric layer, the stacked structure is positioned on the substrate and comprises a step area and a storage area which are distributed in the transverse direction parallel to the substrate, the stacked structure comprises a step structure, a stop layer and a second dielectric layer, the step structure is positioned in the step area and comprises a gate layer and an insulating layer which are arranged in a step-by-step mode in a stacking mode, the stop layer completely covers the step structure, and the second dielectric layer covers the stop layer;
forming a first step contact hole in the step area, wherein the first step contact hole penetrates through the first dielectric layer and the second dielectric layer and extends to the stop layer;
forming a mask layer on the first dielectric layer, wherein the mask layer is provided with a first mask layer opening and a second mask layer opening, and the first mask layer opening corresponds to the first step contact hole;
forming a second step contact hole including the first step contact hole according to the first mask layer opening, wherein the second step contact hole penetrates through the stop layer and extends to each corresponding gate layer;
forming a first opening in the first dielectric layer according to the second mask layer opening;
wherein the second step contact hole and the first opening are formed in the same etching step.
2. The method of fabricating a semiconductor device according to claim 1, wherein the step of forming a semiconductor structure further comprises forming a channel structure extending through the stacked structure and toward the substrate, the method of fabricating a semiconductor device further comprising:
forming a channel contact block in the first opening, the channel contact block in communication with the channel structure.
3. The method of manufacturing a semiconductor device according to claim 1, further comprising, after forming the first stepped contact hole in the stepped region:
and cleaning the first step contact hole.
4. The method of fabricating a semiconductor device according to claim 1, wherein after forming a first opening in the first dielectric layer according to the second mask layer opening, further comprising:
and filling the second step contact hole and the first opening respectively.
5. The method of manufacturing a semiconductor device according to claim 1, wherein forming a mask layer on the first dielectric layer, the mask layer having a first mask layer opening and a second mask layer opening corresponding to the first step contact hole, further comprises:
providing a mask plate, wherein the mask plate is provided with a first mask plate opening and a second mask plate opening, the first mask plate opening corresponds to the first mask layer opening, and the second mask plate opening corresponds to the second mask layer opening.
6. The method of claim 1, wherein the stop layer comprises a carbon-doped nitride.
7. The method for manufacturing a semiconductor device according to claim 6, wherein a content of carbon in the stop layer is greater than 5%.
8. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the stop layer in a longitudinal direction perpendicular to the substrate is larger than 100 nm.
9. A three-dimensional memory comprising an array memory structure and peripheral circuitry, wherein the array memory structure comprises a semiconductor device formed by the method of fabricating a semiconductor device according to any one of claims 1 to 8.
10. A memory system comprising a controller and a three-dimensional memory, the controller being coupled to the three-dimensional memory and being configured to control the three-dimensional memory to store data, the three-dimensional memory comprising a semiconductor device formed by the method of manufacturing a semiconductor device according to any one of claims 1 to 8.
CN202210569785.9A 2022-05-24 2022-05-24 Manufacturing method of semiconductor device, three-dimensional memory and storage system Pending CN115000002A (en)

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CN202210569785.9A CN115000002A (en) 2022-05-24 2022-05-24 Manufacturing method of semiconductor device, three-dimensional memory and storage system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210569785.9A CN115000002A (en) 2022-05-24 2022-05-24 Manufacturing method of semiconductor device, three-dimensional memory and storage system

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CN115000002A true CN115000002A (en) 2022-09-02

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