CN115004300B

CN115004300B - Memory device and control method thereof

Info

Publication number: CN115004300B
Application number: CN202180003084.2A
Authority: CN
Inventors: 董祖奇; 李建平
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2021-08-19
Filing date: 2021-08-19
Publication date: 2025-05-16
Anticipated expiration: 2041-08-19
Also published as: CN115004300A; WO2023019495A1

Abstract

A memory device includes a memory cell array, the memory cell array including one or more memory cells connected between word lines and bit lines. The one or more memory cells include a selected memory cell connected between a selected bit line and a corresponding word line and an unselected memory cell connected between an unselected bit line and a corresponding word line. The memory device also includes a charge control circuit, the charge control circuit being configured to control precharging the selected bit line or the unselected bit line to a first voltage, allowing the unselected bit line to share charge with the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to a second voltage.

Description

Memory device and control method thereof

Technical Field

The present disclosure relates to memory devices and methods of operating the same.

Background

During a read operation of a memory cell, several steps may be required before a read voltage is applied into the memory cell. Switching between these steps can be burdensome and redundant, and create undesirable glitches during operation.

Disclosure of Invention

In one aspect, a memory device includes a memory cell array including one or more memory cells connected between word lines and bit lines. The one or more memory cells include selected memory cells connected between the selected bit line and the corresponding word line, and unselected memory cells connected between the unselected bit line and the corresponding word line. The memory device also includes a charge control circuit coupled to the memory cell array and configured to control pre-charging (precharge) the selected bit line or the unselected bit line to a first voltage, charge-sharing (CHARGE SHARING) the unselected bit line with the selected bit line so that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to a second voltage.

In another aspect, a system includes a memory device including an array of memory cells. The memory cell array includes one or more memory cells connected between word lines and bit lines. The one or more memory cells include a selected memory cell connected between a selected bit line and a corresponding word line and an unselected memory cell connected between an unselected bit line and a corresponding word line. The memory device also includes a charge control circuit coupled to the memory cell array and configured to control pre-charging the selected bit line or the unselected bit line to a first voltage, charge-sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach a same voltage level, and discharging the selected bit line to a second voltage.

In yet another aspect, a method for operating a memory device includes a selected memory cell connected between a selected bit line and a corresponding word line, an unselected memory cell connected between an unselected bit line and a corresponding word line, a first local control gate coupled to the selected bit line or the unselected bit line, a second local control gate coupled between the unselected bit line and the selected bit line, and a third local control gate coupled to the selected bit line. The method includes setting a selected bit line and an unselected bit line to an initial state, setting a first local control gate to an "on" state to precharge the selected bit line or the unselected bit line to a first voltage, setting the first local control gate to an "off" state and simultaneously setting a second local control gate to an "on" state so that the selected bit line and the unselected bit line reach the same voltage level, setting the second local control gate to an "off" state and simultaneously setting a third local control gate to an "on" state to discharge the selected bit line to a second voltage, applying a read voltage via the corresponding word line and obtaining a read result, and resetting the selected bit line and the unselected bit line to the initial state.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

Fig. 1 illustrates a block diagram of an exemplary system having a memory device in accordance with aspects of the present disclosure.

Fig. 2 illustrates a schematic diagram of an exemplary memory device including peripheral circuitry, in accordance with some aspects of the present disclosure.

Fig. 3 illustrates a schematic diagram of an exemplary memory device including a phase-change memory (PCM) cell, in accordance with some aspects of the present disclosure.

Fig. 4 illustrates a block diagram of an exemplary memory device including a memory cell array and peripheral circuitry, in accordance with aspects of the present disclosure.

Fig. 5 illustrates a block diagram of an exemplary memory device including a charge control circuit, in accordance with some aspects of the present disclosure.

Fig. 6 illustrates a block diagram of an exemplary memory device including a charge control circuit, in accordance with some aspects of the present disclosure.

7A-7B illustrate a time sequence of read operations of an exemplary memory device according to some aspects of the present disclosure.

Fig. 8 shows simulation results of a time sequence of control signals under a read operation.

Fig. 9A shows simulation results of a time series of control signals under a read operation.

Fig. 9B illustrates simulation results of a time series of control signals under a read operation using an exemplary method of operating a memory device in accordance with some aspects of the present disclosure.

Fig. 10 illustrates a flow chart of an exemplary method of operating a memory device in accordance with aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

Detailed Description

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the present disclosure may also be used in a variety of other applications. The functional and structural features as described in the present disclosure may be combined, adjusted, and modified from each other in a manner not specifically shown in the drawings so that such combinations, adjustments, and modifications are within the scope of the present disclosure.

Generally, the terms may be understood, at least in part, from the usage in the context. For example, the term "one or more" as used herein, depending at least in part on the context, may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a feature, structure, or combination of features in a plural sense. Similarly, terms such as "a," "an," or "the" may also be construed to express singular usage or plural usage, depending at least in part on the context. In addition, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but rather may allow for the presence of other factors not necessarily explicitly described, again depending at least in part on the context. In addition, the terms "coupled," "coupled to," or "coupled between" may be understood as not necessarily intended to be "physically joined or attached," i.e., directly attached, but may also be interpreted by indirect connection of intermediate components.

Phase Change Memory (PCM) cells are non-volatile memory devices that use phase change materials to store data. PCM may utilize the difference between the resistivity of amorphous and crystalline phases in phase change materials (e.g., chalcogenide alloys) based on electrothermal heating and quenching of the phase change material. The phase change material in a PCM cell may be located between two electrodes and may be applied with a current to repeatedly switch the material (or at least a portion thereof blocking the current path) between the two phases to store data. The "set" state is a low resistance state of the PCM cell, which can be obtained by creating crystalline regions in the chalcogenide material. Crystallization occurs when the chalcogenide material is heated at the crystallization temperature for a sufficient duration. In contrast, the "reset" state is a high resistance state of the PCM cell, which can be obtained by creating an amorphous region in the chalcogenide material. Amorphous states can be created when a chalcogenide material is heated above its melting temperature and then rapidly quenched to form an amorphous state. The "set" state may be referred to as an "on" state, and the "reset" state may be referred to as an "off" state.

Conventional read operations of memory cells may require multiple steps or operations to precharge share (PRECHARGE SHARING), charge share, or discharge the respective bit lines before a read voltage is applied via the word lines to read out the result. Due to the resistive-capacitive delay (CAPACITIVE DELAY, RC delay), a time interval should be given between every two steps of the multiple steps to avoid glitches caused by control signal overlap, thereby increasing the read delay.

Specifically, in order to obtain a result of determining whether the memory cell is in the "set" state or the "reset" state, a charge sharing process is required to bring the selected bit line and the unselected bit line to the same voltage level as a reference voltage before a read voltage is applied to the memory cell via the word line. The charge sharing process may include several precharge sharing, charge sharing and discharging steps, which are controlled by applying several control signals to turn on and off several control gates and applying a specific charge or discharge bias to the bit lines. However, due to the resistive-capacitive delay (RC delay), a time interval should be given between each of the plurality of steps to avoid glitches caused by overlapping of control signals, thereby increasing the read delay. Furthermore, in memory devices having Phase Change Memory (PCM) cells (e.g., each PCM cell may include a PCM element in series with a selector), read latency is a necessary factor for overall system performance. A solution that avoids glitches between control signal overlaps during precharge sharing, charge sharing, or discharge processes while reducing the overall read time is highly desirable. In addition, since there are multiple precharge sharing, charge sharing, or discharging processes, which are redundant and burdensome, it may be necessary to apply several control signals to turn on and off the control gates to precharge sharing, charge sharing, or discharging the corresponding bit lines. There is also a need for a simplified method and corresponding circuit design to control multiple on and off steps.

In order to solve one or more of the above problems, the present disclosure provides a solution in which an integrated charge control circuit is introduced to prepare a phase by pre-applying a control signal before switching to the next step of a charge or discharge process, thereby reducing glitches between switches and a time interval given to avoid glitches. In addition, processing is simplified to reduce read latency. Specifically, the selected bit line and the unselected bit line are set to initial states before a read voltage is applied to the word line to read out the result of the memory cell. In some embodiments, the initial state may be a grounded state or at 0V.

Then, during a precharge sharing process, the first local control gate is set to an "on" state to precharge the unselected bit lines to a first voltage, e.g., a first negative voltage. In some implementations, it may also precharge selected bit lines instead of unselected bit lines. The precharge share process is used to pull one of the bit lines to a voltage (e.g., a negative voltage) such that after a subsequent charge share process, both bit lines will be brought to the same voltage level (e.g., half the previous negative voltage). Note that "precharge" or "precharge share" hereinafter refers to charging a bit line before a charge sharing process.

Then, during the charge sharing process, the first local control gate is set to an "off" state to stop precharging the unselected bit lines (or selected bit lines), and at the same time, the second local control gate is set to an "on" state so that the selected bit lines and the unselected bit lines reach the same voltage level, which is the reference voltage. Note that "charge sharing" hereinafter refers to electrically connecting two bit lines to achieve the same voltage level.

The second local control gate is then set to an "off" state to interrupt charge sharing of the selected bit line and the unselected bit lines, and at the same time the third local control gate is set to an "on" state to discharge the selected bit line to a second voltage, e.g., a second negative voltage, followed by setting the third local control gate to an "off" state to interrupt discharge of the selected bit line. Note that "discharging" hereinafter refers to charging the bit line to a negative voltage level, particularly to a voltage level lower than the reference voltage.

Then, after discharging the selected bit line to the second negative voltage and maintaining the unselected bit lines at the reference voltage, a read voltage is applied via the corresponding word line, and a read result is obtained. If the selected memory cell on the selected bit line is in a "set" state, the voltage on the selected bit line will be pulled up above the reference voltage because the read voltage is above the set threshold voltage of the selected memory cell, while the unselected bit lines will remain at the reference voltage. The read data (e.g., read voltage or read current) of the memory cell in the "set" state may be obtained later. If the selected memory cell on the selected bit line is in a "reset" state, the voltage on the selected bit line will not be pulled up above the reference voltage because the read voltage is below the reset threshold voltage of the selected memory cell. The read data (e.g., read voltage or read current) of the memory cell in the "reset" state may be obtained later.

After the read result is read out, the selected bit line and the unselected bit line are reset to the initial state during the recovery process, and the read operation is completed.

As described above, by turning the first local control gate "on" and turning the second local control gate "off, and by simultaneously turning the second local control gate" off and the third local control gate "on", the time interval can be minimized. In order to turn on one local control gate while preventing a glitch and to turn off the other local control gate at the same time, an integrated charge control circuit may be provided. Specifically, one exemplary integrated charge control circuit provides a first control signal to a first local control gate, a second control signal AND an inverted first control signal (e.g., the first control signal is inverted by a first inverter) to a first AND logic gate, AND a third control signal AND an inverted second control signal (e.g., the second control signal is inverted by a second inverter) to a second AND logic gate. Thus, the inverted first control signal is maintained at 0V before the first control signal is turned to 0V, so that the second local control gate is not turned to "on" regardless of whether the second control signal is turned to "on". Thus, the second control signal may be applied to the first AND logic gate in advance AND wait until the first control signal transitions to 0V. And when the first control signal goes to 0V (i.e., the first local control gate goes "off"), the second local control gate immediately goes "on". Since the second control signal is already turned on when the first control signal is turned off, no or little glitch will occur. Similarly, the inverted second control signal is maintained at 0V before the second control signal turns to 0V, so that the third local control gate cannot turn to "on" regardless of whether the third control signal turns to "on". Thus, the third control signal may be applied to the second AND logic gate in advance AND wait until the second control signal transitions to 0V. And when the second control signal goes to 0V (i.e., the second local control gate goes "off"), the third local control gate immediately goes "on". Since the third control signal is already turned on when the second control signal is turned off, no or little glitch will occur. It should be noted that integrated charge control circuits according to some embodiments of the present disclosure are merely examples of achieving a desired function or mechanism, and any other combination of control gates that achieve the same or similar functionality is possible according to the teachings above.

Fig. 1 illustrates a block diagram of an exemplary system 100 having a memory device in accordance with aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a pointing device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a storage device therein. As shown in FIG. 1, system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 may be a processor of an electronic device, such as a central processing unit (central processing unit, CPU), or a system-on-chip (SoC), such as an application processor (application processor, AP). In some implementations, host 108 may be configured to send data to memory device 104 or receive data from memory device 104. In some implementations, the host may be a user logic unit or user interface so that a user can give instructions to the host and transfer the instructions to a memory device or memory array.

Memory device 104 may be any of the memory devices disclosed in this disclosure. As disclosed in detail below, according to some embodiments, the memory device 104 (e.g., phase-change random access memory (PCRAM), dynamic Random Access Memory (DRAM), or NAND flash memory device) may include a clock input, a command bus, a data bus, control logic units, address registers, row decoder/word line drivers, a memory cell array with memory cells, voltage generators, page buffers/sense amplifiers, column decoder/bit line drivers, data input/output (I/O).

According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 may manage data stored in memory device 104 and communicate with host 108. In some implementations, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, compact Flash (CF) card, universal serial bus (universal serial bus, USB) Flash drive, or other medium used in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some implementations, the memory controller 106 is designed to operate in a high duty cycle environment Solid State Drive (SSD) or embedded multimedia card (eMMC) that is used as a data storage device and enterprise storage array for mobile devices such as smartphones, tablets, laptops, etc. The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and write operations. The memory controller 106 may also be configured to manage various functions with respect to data stored or to be stored in the memory device 104 including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some implementations, the memory controller 106 is further configured to process error correction codes (error correction code, ECC) for data read from or written to the memory device 104. Any other suitable function may also be performed by the memory controller 106, such as formatting the memory device 104. Memory controller 106 may communicate with external devices (e.g., host 108) according to a particular communication protocol. For example, the memory controller 106 may communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PERIPHERAL COMPONENT INTERCONNECTION, PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (advanced technology attachment, ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer interface (SCSI) SMALL INTERFACE protocol, a small computer interface (SCSI) protocol, Enhanced small disk interface (ENHANCED SMALL DISK INTERFACE, ESDI) protocol, integrated Drive Electronics (IDE) protocol, firewire protocol, etc. In addition, the memory controller 106 may also be configured to control the operation of the memory device 104 to perform methods according to some embodiments of the present disclosure. For example, in some implementations, the memory controller 106 can determine whether the read voltage is above or below the threshold voltage of the selected memory cell. In some implementations, the memory controller 106 can determine that the state of the selected memory cell is a "set" state in response to the read voltage being above the threshold voltage of the selected memory cell, or a "reset" state in response to the read voltage being below the threshold voltage of the selected memory cell. Note that one or more of these operations of memory device 104 may also be performed in part or in whole by the control logic unit, according to some embodiments of the present disclosure.

Fig. 2 shows a schematic circuit diagram of an exemplary memory device 200 including peripheral circuitry in accordance with some aspects of the present disclosure. Memory device 200 may be an example of memory device 104 in fig. 1. The memory device 200 may include a memory cell array 201 and peripheral circuitry 202 coupled to the memory cell array 201. The memory cell array 201 may include word lines (e.g., selected word line 214), bit lines (e.g., selected bit line 216 and unselected bit line 218), and memory cells (e.g., selected memory cell 208 and unselected memory cell 210) formed between the word lines and the bit lines. In some implementations, each memory cell (e.g., selected memory cell 208 and unselected memory cell 210) may include a PCM element (not shown) in series with a selector (not shown). In some implementations, the memory cell (e.g., 208 or 210) may also be a DRAM cell including a pair of transistors and a capacitor. To read a selected memory cell (e.g., selected memory cell 208), a selected word line voltage (e.g., selected word line voltage Vwl 1) may be applied to a selected word line (e.g., selected word line 214), and a selected bit line voltage (e.g., selected bit line voltage Vbl 1) may be applied to a selected bit line (e.g., selected bit line 216). The other unselected word lines will remain at the unselected word line voltage (e.g., vwl 0), and the other unselected bit lines will remain at the unselected bit line voltage (e.g., vbl 0). In some implementations, before a selected word line voltage (e.g., selected word line voltage Vwl 1) is applied to a selected word line (e.g., selected word line 214), the unselected bit line voltage (e.g., vbl 0) of the unselected bit line (e.g., unselected bit line 218) is configured to be set to a reference voltage through a series of voltages during precharge sharing, charge sharing, and discharging processes. In some implementations, before a selected word line voltage (e.g., selected word line voltage Vwl 1) is applied to a selected word line (e.g., selected word line 214), a selected bit line voltage (e.g., vbl 1) of a selected bit line (e.g., selected bit line 216) is configured to be set to a series of voltages during precharge sharing, charge sharing, and discharge processes. These precharge sharing, charge sharing and discharging processes will be discussed later.

Fig. 3 shows a side view of a cross section of a memory device 300 having PCM elements in series with a selector. The memory device 300 includes one or more parallel bit lines 304 (i.e., corresponding to bit lines 216 in fig. 2) over a substrate 302 and one or more parallel word lines 316 (i.e., corresponding to word lines 214 in fig. 2) over the bit lines 304. The memory device 300 also includes one or more PCM cells 301 (i.e., corresponding to the memory cell 208 in fig. 2), each of the PCM cells 301 being disposed at an intersection of a respective pair of bit lines 304 and word lines 316. Adjacent PCM cells 301 are separated by insulating structures 322. Each PCM cell 301 includes a selector 308 and a PCM element 312 above the selector 308. Each PCM cell 301 also includes three electrodes 306, 310 and 314, respectively, vertically between a respective bit line 304, a selector 308, a PCM element 312 and a respective word line 316. As described above, a read operation of a memory cell may reduce the lifetime of the memory cell. This phenomenon is observed especially in PCM cells (e.g., 301) having a PCM element (e.g., 312) in series with a selector (e.g., 308), because PCM cells are more sensitive to read voltages and can have a higher probability of getting stuck in a "reset" state when the read voltage is too high.

Note that PCM element 312 may take advantage of the difference between the resistivity of the amorphous and crystalline phases in the phase change material based on electrothermal heating and quenching of the phase change material (e.g., chalcogenide alloy). The phase change element may be located between two electrodes and a current may be applied to repeatedly switch material (or at least a portion thereof blocking the current path) between the two phases to store data.

The selector 308 may include an Ovonic Threshold Switch (OTS) selector having an ovonic threshold switch (ovonic threshold switch, OTS) material, such as zinc telluride (ZnTe), that exhibits field-dependent volatile resistance switching behavior (referred to as the "OTS phenomenon") when an external bias voltage (Va) higher than a threshold voltage (Vth) is applied. At lower voltages (|va| < Vth), the high resistance of the OTS selector in its off state keeps the off-state current (Ioff) low. At higher voltages (|Va| > Vth), the OTS selector experiences OTS phenomena and switches to an on-state with low resistance, and thus, the current (Ion) through the OTS selector in the on-state increases. The volatile on state is maintained as long as a high voltage is supplied.

Fig. 4 illustrates a block diagram of an exemplary memory device 400 (e.g., corresponding to 104 in fig. 1) including a memory cell array 401 (e.g., corresponding to 201 in fig. 2) and peripheral circuitry, in accordance with some aspects of the present disclosure. In some implementations, the memory cells of the memory cell array 401 include PCM cells 301 as in fig. 3.

As shown in fig. 4, a page buffer/sense amplifier 404 may be coupled to the memory cell array 401 and configured to read data from and program (write) data to the memory cell array 401 according to a control signal from the control logic unit 412. In one example, page buffer/sense amplifier 404 can store a page of programming data (write data) to be programmed into a page of memory cell array 201 (e.g., in FIG. 2). In another example, page buffer/sense amplifier 404 can perform a program verify operation to ensure that data has been properly programmed into memory cells 208 coupled to a selected word line 214. In yet another example, the page buffer/sense amplifier 404 may also sense a low power signal from the selected bit line 216 representing a data bit stored in the memory cell 208 and amplify the small voltage swing to an identifiable logic level in a read operation.

The column decoder/bit line driver may be coupled to the memory cell array 401 and the control logic unit 412 and configured to control and select one or more memory cells (e.g., the selected memory cell 208) and bit lines (e.g., the selected bit line 216) by the control logic unit 412. The column decoder/bit line driver 406 may be further configured to drive the selected bit line 216. The column decoder/bit line driver 406 may be further configured to drive the selected bit line 216 using the bit line voltage generated from the voltage generator 410.

The data I/O416 may be coupled to the page buffer/sense amplifier 404 and/or the column decoder/bit line driver 406 and is configured to direct (route) data inputs from the data bus 423 to the selected memory cells 208 of the memory cell array 201 and to direct (route) data outputs from the selected memory cells to the data bus 423.

The row decoder/wordline driver 408 may be coupled to the control logic unit 412 and the memory cell array 401 and configured to be controlled by the control logic unit 412 and to select one or more memory cells (e.g., the selected memory cell 208) and a selected wordline (e.g., the selected wordline 214) in the memory cell array 201. The row decoder/word line driver 408 may be further configured to drive the selected word line 214. The row decoder/wordline driver 408 may be further configured to drive the selected wordline 214 using the wordline voltage generated from the voltage generator 410.

The voltage generator 410 may be coupled to the control logic unit 412 and configured to be controlled by the control logic unit 412 according to control signals from the control logic unit 412 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verify voltage, etc.), a bit line voltage, and a source line voltage to be provided to the memory cell array 401.

Control logic unit 412 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The control logic unit 412 is configured to receive clock signals, command signals, address signals, and data signals from a host (e.g., 108 in fig. 1). The command signals are received via a command bus 421. The data signal is received via the data bus 423. In some embodiments, control logic 412 may be implemented by a microprocessor, microcontroller (also known as a microcontroller unit (microcontroller unit, MCU)), digital signal processor (DIGITAL SIGNAL processor, DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (programmable logic device, PLD), state machine, gating logic, discrete hardware circuits, and other suitable hardware, firmware, and/or software configured to perform the various functions described. In some implementations, the control logic unit 412 is coupled to the word line driver 408 and is configured to direct the read voltage into the selected memory cell via the word line driver 408.

The address register 414 may be coupled to the control logic unit 412 or included in the control logic unit 412. The address register 414 may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit.

Fig. 5 illustrates a block diagram of a memory device (e.g., corresponding to 400 in fig. 4) including a charge control circuit 500, in accordance with some aspects of the present disclosure. As shown in fig. 4, once the control logic unit 412 determines that the command signal is a read command, it triggers a read operation. The read operation includes a series of processes of precharge sharing, charge sharing, and discharging before a read voltage is applied to a selected word line. According to some embodiments of the present disclosure, these precharge sharing, charge sharing, and discharging processes are performed by the charge control circuit 500. The charge control circuit 500 may include a voltage comparator 501 (e.g., corresponding to or included in the page buffer/sense amplifier 404) coupled to a memory cell array (e.g., corresponding to the memory cell array 201 or 401), an unselected bit line 511 (e.g., corresponding to the unselected bit line 218) connected to a first input terminal 503 of the voltage comparator 501, and a selected bit line 513 (e.g., corresponding to the selected bit line 216) connected to a second input terminal 505 of the voltage comparator 501. In some implementations, the voltage comparator 501 is configured to determine that a selected memory cell (e.g., selected memory cell 208) is in a "set" state if the selected bit line voltage Vbl ₁ of the selected bit line 513 (e.g., selected bit line 216) is above a reference voltage held by the unselected bit line 511 (e.g., corresponding to unselected bit line 218), and that the selected memory cell is in a "reset" state if the selected bit line voltage of the selected bit line is below the reference voltage.

The first local control gate 521 is coupled to the selected bit line 513 (e.g., corresponding to the selected bit line 216 in fig. 2) or the unselected bit line 511 (e.g., corresponding to the unselected bit line 218), and is configured to control whether the selected bit line 513 or the unselected bit line 511 is precharged to a first voltage (e.g., a first negative voltage Vn 1) during the precharge sharing process. In one example, as shown in fig. 5, the first local control gate 521 is configured to control whether the unselected bit line 511 is precharged to the first negative voltage Vn1. In some embodiments, the first negative voltage Vn1 may be-2V to-4V, such as-3.7V.

The second local control gate 523 is coupled between the selected bit line 513 and the unselected bit line 511, and is configured to control whether the selected bit line 513 and the unselected bit line 511 are brought to the same voltage level (e.g., one half of the first negative voltage Vn 1) during the charge sharing process. After the charge sharing process, the same voltage level described above (e.g., one-half of the first negative voltage Vn 1) may be a reference voltage that may be used to determine whether the selected memory cell is in a "set" state or a "reset" state by comparing the selected bit line voltage Vbl1 to a reference voltage maintained by the unselected bit lines 511. For example, if the selected memory cell is in a "set" state, the selected bit line voltage will be pulled up above the reference voltage after a read voltage is applied across the selected word line. Conversely, if the selected memory cell is in the "reset" state, the selected bit line voltage will remain below the reference voltage after the read voltage is applied across the selected word line.

The third local control gate 525 is coupled to the selected bit line 513 and is configured to control whether the selected bit line 513 is discharged to a second voltage (e.g., a second negative voltage Vn 2) during a discharging process. In some embodiments, the second negative voltage Vn2 may be-2V to-4V, for example-3.7V. Note that charge control circuit 500 according to some embodiments of the present disclosure is merely an example of implementing a desired function or mechanism, and any other combination of control logic gates implementing the same or similar functions is possible according to the teachings above.

Fig. 6 illustrates a block diagram of a memory device (e.g., corresponding to 400 in fig. 4) including a charge control circuit 600, in accordance with some aspects of the present disclosure. As described above, in order to switch between the first local control gate 521 and the second local control gate 523 and between the second local control gate 523 and the third local control gate 525 without causing a glitch and reduce the time interval, the exemplary charge control circuit 600 is introduced.

First, the first control signal 621 may be transmitted to turn the first local control gate 521 "on" and "off. That is, the first local control gate 521 is configured to be controlled by the first control signal 621.

Next, the second control signal 623 AND an inverted first control signal, which is an inverted control signal of the first control signal 621 generated by the first inverter 601, are supplied to the first AND logic gate 611. The output of the first AND logic gate 611 may be transferred to turn the second local control gate 523 "on" AND "off. That is, the second local control gate 523 is configured to be controlled by the output result of the first AND logic gate 611. The first inverter 601 is coupled to the first AND logic gate 611 AND is configured to invert the first control signal 621 into an inverted first control signal. The first AND logic gate 611 is configured to receive the second control signal 623 AND the inverted first control signal.

Third, the third control signal 625 AND an inverted second control signal, which is an inverted control signal of the second control signal 623 generated by the second inverter 603, are supplied to the second AND logic gate 613. The output of the second AND logic gate 613 may be transferred to turn the third local control gate 525 "on" AND "off. That is, the third local control gate 525 is configured to be controlled by the output result of the second AND logic gate 613. The second inverter 603 is coupled to the second AND logic gate 613 AND is configured to invert the second control signal 623 into an inverted second control signal. The second AND logic gate 613 is configured to receive the third control signal 625 AND the inverted second control signal.

As described above, by simultaneously turning "on" the first local control gate 521 and "off" the second local control gate 523, and by simultaneously turning "off" the second local control gate 523 and "on" the third local control gate 525, the time interval can be reduced to a minimum. Specifically, the first control signal 621 is provided to the first local control gate 521, the second control signal 623 AND the inverted first control signal (e.g., the first control signal 621 is inverted by the first inverter 601) are provided to the first AND logic gate 611, AND the third control signal 625 AND the inverted second control signal (e.g., the second control signal 623 is inverted by the second inverter 603) are provided to the second AND logic gate 613. Thus, the inverted first control signal remains at 0V until the first control signal 621 turns to 0V, so that the second local control gate 523 cannot turn to "on" regardless of whether the second control signal 623 turns to "on". Accordingly, the second control signal 623 may be turned on AND pre-applied to the first AND logic gate 611 AND wait until the first control signal 621 transitions to 0V. When the first control signal 621 goes to 0V (i.e., the first local control gate 521 goes to "off"), the second local control gate 523 immediately goes to "on". Since the second control signal 623 is already on and waiting when the first control signal 621 is off, no or little glitch will occur. Similarly, the inverted second control signal remains at 0V until the second control signal 623 transitions to 0V, such that the third local control gate 525 cannot transition to "on" regardless of whether the third control signal 625 transitions to "on". Accordingly, the third control signal 625 may be turned on AND pre-applied to the second AND logic gate 613 AND wait until the second control signal 623 transitions to 0V. When the second control signal 623 goes to 0V (i.e., the second local control gate 523 goes to "off"), the third local control gate 525 immediately goes to "on". Since the third control signal 625 is already turned on when the second control signal 623 is turned off, no or little glitch will occur. Note that charge control circuit 600 according to some embodiments of the present disclosure is merely an example of implementing a desired function or mechanism, and any other combination of control logic gates implementing the same or similar functions is possible according to the teachings above.

7A-7B illustrate a time sequence of read operations of an exemplary memory device according to some aspects of the present disclosure. Specifically, fig. 7A shows a "set" state readout sequence, and fig. 7B shows a "reset" state readout sequence. As shown in fig. 7A, step 1 is an initial state in which when the word line voltage (Vwl) has not been provided to a memory cell (e.g., selected memory cell 208), the current (Icell) on the memory cell is 0mA, and both the selected bit line voltage (Vbl 0) and the unselected bit line voltage (Vbl 0) are set to ground voltage or 0V.

Step 2 is a precharge sharing process in which a selected bit line (e.g., selected bit line 216) or an unselected bit line (e.g., unselected bit line 218) is precharged to a first negative voltage Vn1.

Step 3 is a charge sharing process in which the selected bit line and the unselected bit line are electrically connected such that the selected bit line and the unselected bit line reach the same voltage level, which is the reference voltage.

Step 4 is a discharge process in which the selected bit line is discharged to a second negative voltage Vn2.

Step 5 is a read process in which a read voltage (e.g., word line voltage (Vwl)) is provided to the memory cell. Since the memory cell is in the "set" state, the current across the memory cell increases and pulls up the selected bit line voltage above the reference voltage held by the unselected bit lines. The voltage comparator 501 (corresponding to the sense amplifier 404 or included in the sense amplifier 404) can thus determine that the memory cell is in a "set" state by the sense flag changing from 0 (Vbl 0> Vbl 1) to 1 (Vbl 0< Vbl 1).

Conversely, if the memory cell is in the "reset" state as in FIG. 7B, the current across the memory cell remains the same and the selected bit line voltage is not pulled up above the reference voltage. The voltage comparator 501 (corresponding to the sense amplifier 404 or included in the sense amplifier 404) can thus determine that the memory cell is in a "reset" state by the sense flag not changing from 0 to 1.

Step 6 is a restore process in which both the selected bit line and the unselected bit line are reset to an initial state, which is either ground voltage or 0V.

Fig. 8 shows simulation results of a time sequence of control signals under a read operation. As shown in fig. 8, step 2 may be divided into step 2a and step 2b, since the first local control gate (corresponding to 521 in fig. 5) is turned "on" during step 2a and turned "off" during step 2 b. Meanwhile, step 3 may be divided into step 3a and step 3b, because the second local control gate (corresponding to 523 in fig. 5) is turned "on" during step 3a and turned "off" during step 3 b. Also, step 4 may be divided into step 4a and step 4b, as the third local control gate (corresponding to 525 in fig. 5) is turned "on" during step 4a and turned "off" during step 4 b. By turning several local control gates "on" and "off" there are more than 9 steps for one read operation, which is burdensome and redundant for the entire system. Furthermore, since in some embodiments these local control gates may be controlled by a Basic Control Unit (BCU) that is a component of a memory controller (corresponding to 106 in fig. 1), several clock cycles may be required to perform these steps.

For example, fig. 9A, simulation results without charge control circuitry (e.g., 500 or 600) according to some embodiments of the present disclosure show that at least 2 clock cycles (4 ns) are required for each switching phase, and thus a total of 10ns are required for each read operation, which increases the total read latency (note that the entire read operation may take 120 ns).

Thus, after implementing a charge control circuit (e.g., 500 or 600) according to some embodiments of the present disclosure, fig. 9B shows that the total time interval is less than 0.5 nanoseconds (ns), e.g., 247 picoseconds (ps) +104 ps=351 ps, without any glitches.

Fig. 10 illustrates a flow chart of an exemplary method of operating a memory device in accordance with aspects of the present disclosure. The memory device may be any suitable memory device disclosed herein. The method 1000 may be implemented, in part or in whole, by the control logic unit 412 as in fig. 4 or the memory controller 106 as in fig. 1. It should be understood that the operations illustrated in method 1000 are not exhaustive and that other operations may be performed before, after, or between any of the illustrated operations. Further, some operations may be performed simultaneously or in a different order than shown in fig. 10.

Referring to fig. 10, the method 1000 begins at operation 1002, where a selected bit line (e.g., 216 in fig. 2) and an unselected bit line (e.g., 218 in fig. 2) are selected and set to an initial state. In some embodiments, the initial state may be a grounded state or at 0V.

The method 1000 proceeds to operation 1004, as shown in fig. 10, where during the precharge sharing process, a first local control gate (e.g., 521 in fig. 5) is set to an "on" state to precharge a selected bit line or an unselected bit line (e.g., precharge an unselected bit line as in fig. 7A) to a first voltage (e.g., a first negative voltage Vn 1). The precharge share process is used to pull one of the bit lines to a voltage (e.g., a negative voltage) such that after a subsequent charge share process, both bit lines will be brought to the same voltage level (e.g., half the previous negative voltage).

The method 1000 proceeds to operation 1006, as shown in fig. 10, where during the charge sharing process, the first local control gate is set to an "off" state to interrupt the precharging of the unselected bit lines, and at the same time the second local control gate (e.g., 523 in fig. 5) is set to an "on" state, such that the selected bit line and the unselected bit line reach the same voltage level, which is the reference voltage.

The method 1000 proceeds to operation 1008 as shown in fig. 10, where the second local control gate is set to an "off" state to interrupt charge sharing of the selected bit line and the unselected bit lines, and at the same time the third local control gate (e.g., 525 in fig. 5) is set to an "on" state to discharge the selected bit line to a second voltage (e.g., the second negative voltage Vn 2), and then the third local control gate is set to an "off" state to interrupt discharge of the selected bit line.

The method 1000 proceeds to operation 1010, as shown in fig. 10, where after the selected bit line is discharged to the second negative voltage and the unselected bit lines are held at the reference voltage, a read voltage is applied via the corresponding word line and a read result is obtained. If a selected memory cell (e.g., selected memory cell 208 in FIG. 2) on a selected bit line (e.g., selected bit line 216 in FIG. 2) is in a "set" state, the voltage on the selected bit line will be pulled up above the reference voltage because the read voltage is above the set threshold voltage of the selected memory cell, while the unselected bit lines will remain at the reference voltage. The read data (e.g., read voltage or read current) of the memory cell in the "set" state may be obtained. If the selected memory cell on the selected bit line is in a "reset" state, the voltage on the selected bit line will not be pulled up above the reference voltage because the read voltage is below the reset threshold voltage of the selected memory cell. The read data (e.g., read voltage or read current) of the memory cell in the "reset" state may be obtained. In some implementations, the memory cell may be a PCM cell 301 as in fig. 3.

The method 1000 proceeds to operation 1012, as shown in fig. 10, where after the read result is read out, the selected bit line and the unselected bit line are reset to an initial state during a recovery process, and the read operation is completed.

According to one aspect of the disclosure, a memory device includes a memory cell array including one or more memory cells connected between a word line and a bit line. The one or more memory cells include selected memory cells connected between the selected bit line and the corresponding word line and unselected memory cells connected between the unselected bit line and the corresponding word line. The memory device also includes a charge control circuit coupled to the array of memory cells and configured to control pre-charging the selected bit line or the unselected bit line to a first voltage, charge-sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to a second voltage.

In some embodiments, the total time interval between each of the following processes is less than 0.5 nanoseconds (ns) by precharging the selected bit line or the unselected bit line to a first voltage, sharing the unselected bit line with the selected bit line charge such that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to a second voltage.

In some implementations, the charge control circuit further includes a voltage comparator coupled to the memory cell array and configured to compare an unselected bit line voltage of the unselected bit line with a selected bit line voltage of the selected bit line and to generate a comparison output signal.

In some embodiments, the charge control circuit further includes a first local control gate coupled to the selected bit line or the unselected bit line and configured to control pre-charging of the selected bit line or the unselected bit line to the first voltage, a second local control gate coupled between the selected bit line and the unselected bit line and configured to control charge sharing of the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level, and a third local control gate coupled to the selected bit line and configured to control discharging of the selected bit line to the second voltage.

In some embodiments, the charge control circuit further includes a first inverter configured to receive the first control signal AND generate an inverted first control signal, a second inverter configured to receive the second control signal AND generate an inverted second control signal, a first AND logic gate coupled to the first inverter AND configured to receive the second control signal AND the inverted first control signal, AND a second AND logic gate coupled to the second inverter AND configured to receive the third control signal AND the inverted second control signal. The first local control gate is configured to be controlled by a first control signal, the second local control gate is configured to be controlled by a first output result of the first AND logic gate, AND the third local control gate is configured to be controlled by a second output result of the second AND logic gate.

In some implementations, each memory cell includes a Phase Change Memory (PCM) cell.

In some embodiments, a PCM cell includes a PCM element and a selector in series with the PCM element.

In some embodiments, the first voltage is a first negative voltage of-2V to-4V.

In some embodiments, the second voltage is a second negative voltage of-2V to-4V.

In some implementations, the same voltage level is a reference voltage and the voltage comparator is configured to compare the reference voltage held by the unselected bit lines to the selected bit line voltage of the selected bit line.

In some implementations, the voltage comparator is configured to determine that the selected memory cell is in a "set" state if the selected bit line voltage of the selected bit line is above a reference voltage and that the selected memory cell is in a "reset" state if the selected bit line voltage of the selected bit line is below the reference voltage.

In some implementations, the memory device further includes a sense amplifier coupled to the memory cell array, and the charge control circuit is included in the sense amplifier.

In some implementations, the memory device further includes a word line driver coupled to the array of memory cells and configured to drive read voltages into the selected memory cells via respective word lines.

In some implementations, the memory device also includes a control logic unit coupled to the word line driver and configured to direct the read voltage into the selected memory cell via the word line driver.

In some embodiments, the memory device further includes a data register coupled to the charge control circuit and configured to store read data and a comparison output signal.

According to another aspect of the disclosure, a system includes a memory device including an array of memory cells. The memory cell array includes one or more memory cells connected between word lines and bit lines. The one or more memory cells include a selected memory cell connected between a selected bit line and a corresponding word line and an unselected memory cell connected between an unselected bit line and a corresponding word line. The memory device also includes a charge control circuit coupled to the memory cell array and configured to control pre-charging the selected bit line or the unselected bit line to a first voltage, charge-sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach a same voltage level, and discharging the selected bit line to a second voltage.

In some embodiments, the total time interval between each of the following processes is less than 0.5 nanoseconds (ns) by precharging the selected bit line or the unselected bit line to a first voltage, charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to a second voltage.

In some implementations, the charge control circuit of the system further includes a voltage comparator coupled to the memory cell array and configured to compare an unselected bit line voltage of the unselected bit line with a selected bit line voltage of the selected bit line and generate a comparison output signal.

In some embodiments, the charge control circuit of the system further includes a first local control gate coupled to the selected bit line or the unselected bit line and configured to control the precharging of the selected bit line or the unselected bit line to the first voltage, a second local control gate coupled between the selected bit line and the unselected bit line and configured to control the charge sharing of the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level, and a third local control gate coupled to the selected bit line and configured to control the discharging of the selected bit line to the second voltage.

In some embodiments, the charge control circuit of the system further includes a first inverter configured to receive a first control signal AND generate an inverted first control signal, a second inverter configured to receive a second control signal AND generate an inverted second control signal, a first AND logic gate coupled to the first inverter AND configured to receive the second control signal AND the inverted first control signal, AND a second AND logic gate coupled to the second inverter AND configured to receive a third control signal AND the inverted second control signal. The first local control gate is configured to be controlled by a first control signal, the second local control gate is configured to be controlled by a first output result of the first AND logic gate, AND the third local control gate is configured to be controlled by a second output result of the second AND logic gate.

In some embodiments, the first voltage is a first negative voltage of-2V to-4V.

In some implementations, the voltage comparator is configured to determine that the selected memory cell is in a "set" state if the selected bit line voltage of the selected bit line is above a reference voltage, and that the selected memory cell is in a "reset" state if the selected bit line voltage of the selected bit line is below the reference voltage.

In some implementations, the memory device of the system further includes a sense amplifier coupled to the memory cell array, and the charge control circuit is included in the sense amplifier.

In some implementations, the memory device of the system also includes a word line driver coupled to the array of memory cells and configured to drive a read voltage into the selected memory cell via a respective word line.

In some implementations, the memory device of the system also includes a control logic unit coupled to the word line driver and configured to direct the read voltage into the selected memory cell via the word line driver.

In some implementations, the memory device of the system further includes a data register coupled to the charge control circuit and configured to store read data and the comparison output signal.

According to yet another aspect of the disclosure, a method for operating a memory device includes a selected memory cell connected between a selected bit line and a corresponding word line, an unselected memory cell connected between an unselected bit line and a corresponding word line, a first local control gate coupled to the selected bit line or the unselected bit line, a second local control gate coupled between the unselected bit line and the selected bit line, and a third local control gate coupled to the selected bit line. The method includes setting a selected bit line and an unselected bit line to an initial state, setting a first local control gate to an "on" state to precharge the selected bit line or the unselected bit line to a first voltage, setting the first local control gate to an "off" state and simultaneously setting a second local control gate to an "on" state so that the selected bit line and the unselected bit line reach the same voltage level, setting the second local control gate to an "off" state and simultaneously setting a third local control gate to an "on" state to discharge the selected bit line to a second voltage, applying a read voltage via the corresponding word line and obtaining a read result, and resetting the selected bit line and the unselected bit line to the initial state.

In some embodiments, the initial state is a ground state or 0V.

In some implementations, the same voltage level is a reference voltage and obtaining the read result includes determining that the selected memory cell is in a "set" state if the selected bit line voltage is above the reference voltage and that the selected memory cell is in a "reset" state if the selected bit line voltage is below the reference voltage.

The foregoing description of specific embodiments may be readily modified and/or adapted for use in various applications. Accordingly, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A memory device, comprising:

a memory cell array comprising one or more memory cells connected between word lines and bit lines, wherein the one or more memory cells comprise:

a selected memory cell connected between the selected bit line and the corresponding word line, and

And a charge control circuit coupled to the memory cell array and configured to control the precharging of the selected bit line or the unselected bit line to a first voltage, charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to a second voltage, wherein the charge control circuit further comprises:

a first local control gate coupled to the selected bit line or the unselected bit line and configured to control pre-charging of the selected bit line or the unselected bit line to the first voltage;

A second local control gate coupled between the selected bit line and the unselected bit line and configured to control charge sharing of the unselected bit line and the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level, and

A third local control gate coupled to the selected bit line and configured to control discharging the selected bit line to the second voltage,

Wherein "turning off" the first local control gate is performed simultaneously with "turning on" the second local control gate, and "turning off" the second local control gate is performed simultaneously with "turning on" the third local control gate.

2. The memory device of claim 1, wherein a total time interval between each of precharging the selected bit line or the unselected bit line to the first voltage, charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to the second voltage is less than 0.5 nanoseconds (ns).

3. The memory device of claim 1 or 2, wherein the charge control circuit further comprises:

A voltage comparator is coupled to the memory cell array and configured to compare an unselected bit line voltage of the unselected bit line with a selected bit line voltage of the selected bit line and generate a comparison output signal.

4. The memory device of claim 1, wherein the charge control circuit further comprises:

a first inverter configured to receive a first control signal and generate an inverted first control signal;

A second inverter configured to receive a second control signal and generate an inverted second control signal;

A first AND logic gate coupled to the first inverter AND configured to receive the second control signal AND the inverted first control signal, AND

A second AND logic gate coupled to the second inverter AND configured to receive a third control signal AND the inverted second control signal, wherein the first local control gate is configured to be controlled by the first control signal, the second local control gate is configured to be controlled by a first output result of the first AND logic gate, AND the third local control gate is configured to be controlled by a second output result of the second AND logic gate.

5. The memory device of claim 1 or 2, wherein each memory cell comprises a Phase Change Memory (PCM) cell.

6. The memory device of claim 5, wherein the phase change memory cell comprises a phase change memory element and a selector in series with the phase change memory element.

7. The memory device of claim 1 or 2, wherein the first voltage is a first negative voltage of-2V to-4V.

8. The memory device of claim 1 or 2, wherein the second voltage is a second negative voltage of-2V to-4V.

9. The memory device of claim 3, wherein the same voltage level is a reference voltage and the voltage comparator is configured to compare the reference voltage held by the unselected bit line to the selected bit line voltage of the selected bit line.

10. The memory device of claim 9, wherein the voltage comparator is configured to determine that the selected memory cell is in a "set" state if a selected bit line voltage of the selected bit line is above the reference voltage and that the selected memory cell is in a "reset" state if the selected bit line voltage of the selected bit line is below the reference voltage.

11. The memory device of claim 1 or 2, further comprising:

a sense amplifier coupled to the memory cell array, wherein the charge control circuit is included in the sense amplifier.

12. The memory device of claim 1 or 2, further comprising:

A word line driver coupled to the array of memory cells and configured to drive a read voltage into the selected memory cell via the respective word line.

13. The memory device of claim 12, further comprising:

A control logic unit coupled to the word line driver and configured to direct the read voltage into the selected memory cell via the word line driver.

14. The memory device of claim 3, further comprising:

A data register coupled to the charge control circuit and configured to store read data and the comparison output signal.

15. A system, comprising:

a memory device, comprising:

An unselected memory cell connected between the unselected bit line and the corresponding word line, and

A charge control circuit coupled to the memory cell array and configured to control pre-charging the selected bit line or the unselected bit line to a first voltage, charge-sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach a same voltage level, and discharging the selected bit line to a second voltage, wherein the charge control circuit further comprises:

Wherein the turning off of the first local control gate is performed simultaneously with the turning on of the second local control gate, and the turning off of the second local control gate is performed simultaneously with the turning on of the third local control gate, and

A memory controller coupled to the memory device and configured to control the memory device.

16. The system of claim 15, wherein a total time interval between each of precharging the selected bit line or the unselected bit line to the first voltage, charge sharing the unselected bit line with the selected bit line such that the unselected bit line and the selected bit line reach the same voltage level, and discharging the selected bit line to the second voltage is less than 0.5 nanoseconds (ns).

17. The system of claim 15 or 16, wherein the charge control circuit further comprises:

18. The system of claim 15, wherein the charge control circuit further comprises:

19. The system of claim 15 or 16, wherein each memory cell comprises a Phase Change Memory (PCM) cell.

20. The system of claim 19, wherein the phase change memory cell comprises a phase change memory element and a selector in series with the phase change memory element.

21. The system of claim 15 or 16, wherein the first voltage is a first negative voltage of-2V to-4V.

22. The system of claim 15 or 16, wherein the second voltage is a second negative voltage of-2V to-4V.

23. The system of claim 17, wherein the same voltage level is a reference voltage and the voltage comparator is configured to compare the reference voltage held by the unselected bit line to the selected bit line voltage of the selected bit line.

24. The system of claim 23, wherein the voltage comparator is configured to determine that the selected memory cell is in a "set" state if the selected bit line voltage of the selected bit line is above the reference voltage and that the selected memory cell is in a "reset" state if the selected bit line voltage of the selected bit line is below the reference voltage.

25. The system of claim 15 or 16, further comprising:

a sense amplifier coupled to the memory cell array, and the charge control circuit is included in the sense amplifier.

26. The system of claim 15 or 16, further comprising:

27. The system of claim 26, further comprising:

28. The system of claim 17, further comprising:

29. A method for operating a memory device including a selected memory cell connected between a selected bit line and a corresponding word line, an unselected memory cell connected between an unselected bit line and the corresponding word line, a first local control gate coupled to the selected bit line or the unselected bit line, a second local control gate coupled between the unselected bit line and the selected bit line, and a third local control gate coupled to the selected bit line, and comprising:

Setting the selected bit line and the unselected bit line to an initial state;

setting a first local control gate to an "on" state to precharge the selected bit line or the unselected bit line to a first voltage;

setting the first local control gate to an "off" state and simultaneously setting a second local control gate to an "on" state so that the selected bit line and the unselected bit line reach the same voltage level;

setting the second local control gate to an "off" state and simultaneously setting a third local control gate to an "on" state to discharge the selected bit line to a second voltage;

applying a read voltage via the corresponding word line and obtaining a read result, and

The selected bit line and the unselected bit line are reset to the initial state.

30. The method of claim 29, wherein the initial state is a ground state or 0V.

31. The method of claim 29 or 30, wherein the same voltage level is a reference voltage and obtaining the read result includes determining that the selected memory cell is in a "set" state if the selected bit line voltage is above the reference voltage and in a "reset" state if the selected bit line voltage is below the reference voltage.