CN114976864A - High-efficiency vertical cavity surface EML chip with embossment - Google Patents

Abstract

A high-efficiency vertical cavity surface EML chip with a relief relates to the technical field of semiconductor photoelectron and comprises a VCSEL unit, an oxidation isolation layer, an EOM unit and the relief, wherein the oxidation isolation layer is arranged between the VCSEL unit and the EOM unit and used for preventing the electric potential at the contact part of the two units from influencing the working current in each unit; the relief is arranged above the EOM unit and used for suppressing a high-order transverse mode so as to realize mode control. The invention breakthroughs an oxidation isolation layer with an electrical insulation effect arranged between the VCSEL unit and the EOM unit to isolate the high-frequency modulation signal applied to the EOM unit, so that the VCSEL unit and the EOM unit are relatively independent, the high-frequency modulation signal is prevented from influencing the current in the VCSEL unit, and the stable output of the VCSEL unit is ensured. The embossment of the invention enables the specular reflectivity of the high-order transverse mode to be relatively reduced, thereby achieving the purpose of inhibiting the high-order transverse mode, ensuring the realization of stable output of the basic transverse mode, optimizing the quality of light beams, reducing the threshold current and the insertion loss, and meeting the single-mode application requirements of the VCSEL chip.

Description

A high-efficiency vertical cavity surface EML chip with relief

technical field

The invention relates to the technical field of semiconductor optoelectronics, in particular to a high-efficiency vertical cavity surface EML chip with relief.

Background technique

With the rapid development of the data communication era, Vertical Cavity Surface Emitting Laser (VCSEL) due to its excellent characteristics, such as small chip size, output circular light spot, low operating threshold, high coupling efficiency, and easy integration, etc. , is widely used in the field of optical communication, such as optical interconnection, optical sensing, optical storage, application scenarios such as data center short-distance communication, 5G base station, HDMI ultra-high-definition video transmission and so on. VCSEL chips have good economy, practicability and reliability, which brings great convenience to information exchange in all walks of life.

As the amount of data increases day by day, higher requirements are placed on the rate and quality of data transmission. At present, VCSEL chips mostly use direct modulation for signal transmission, that is, direct modulation by high-speed radio frequency electrical signals. With the improvement of the modulation rate, the direct modulation of the VCSEL chip is prone to the chirp phenomenon during its operation. This phenomenon will limit the transmission rate of the laser chip. When the transmission distance increases, crosstalk will also be generated. , Optical power attenuation, reducing the transmission quality of the signal. To achieve a higher modulation rate, if the modulation method is not changed, the current density needs to be doubled, which will bring about the problems of increased chip power consumption and shortened life.

Similar to an edge-emitting EML chip, an edge-emitting laser chip is monolithically integrated by a light-emitting unit DFB and a modulation unit. The existing vertical cavity surface EML is monolithically integrated by a light-emitting unit (VCSEL unit) and a modulation unit (EOM unit). A vertical emission laser chip, which is usually in the structure of "NDBR-active region-oxide confinement layer-PDBR-absorbing region-NDBR", the VCSEL unit and the EOM unit respectively realize the optical resonance of the VCSEL unit and enhance the EOM unit by sharing the PDBR. of light absorption. However, since there is no electrical isolation between the VCSEL unit and the EOM unit, when a high-frequency modulation signal is applied to the EOM unit, the current in the VCSEL unit will be affected, thereby affecting the stable output of the VCSEL unit.

In addition, traditional VCSEL chips are usually single longitudinal mode, multi-transverse mode beams, and the number of transverse mode modes is usually 3-6. In the multi-transverse mode working state, the superposition of multiple modes of mixed oscillation is likely to cause mode competition, resulting in optical Power and spectral instability. However, since the stable fundamental transverse mode output can meet the requirements of high-density optical storage reading, free optical interconnection, and data transmission in single-mode fibers, it is hoped that VCSEL chips have stable fundamental transverse mode output in many application scenarios. characteristic.

Based on this, we provide a high-efficiency vertical cavity surface EML chip with relief.

SUMMARY OF THE INVENTION

The present invention provides a high-efficiency vertical cavity surface EML chip with relief, the main purpose of which is to solve the problems existing in the prior art.

The present invention adopts following technical scheme:

A high-efficiency vertical cavity surface EML chip with relief, comprising a VCSEL unit, an oxide isolation layer, an EOM unit and a relief, wherein: the VCSEL unit from bottom to top includes a substrate, a buffer layer, a first DBR, a resonant cavity and a second DBR; the EOM unit includes a third DBR, an absorption region and a fourth DBR from bottom to top; the oxide isolation layer is disposed between the VCSEL unit and the EOM unit, and is used to prevent the potential at the contact of the two units from affecting the respective units The working current inside; the relief is arranged above the EOM unit to suppress the high-order transverse mode to realize mode control.

The invention makes a breakthrough by setting an oxide isolation layer with electrical insulating effect between the VCSEL unit and the EOM unit to isolate the high-frequency modulation signal applied to the EOM unit, so that the VCSEL unit and the EOM unit are relatively independent, and prevent the high-frequency modulation signal from affecting the VCSEL unit. The current in the cell has an effect, thus ensuring a stable output of the VCSEL cell. Compared with the direct contact between the VCSEL unit and the EOM unit in the prior art, the electrical isolation can reduce the RC delay in the high-frequency signal transmission process, which helps to improve the transmission performance and achieve a better modulation effect.

For the design of the VCSEL unit plus the EOM unit in the present invention, the fourth DBR on the top absorbs light, especially for long wavelengths (1310 and 1550 nm), which will cause problems of high threshold current and large insertion loss. . By arranging the relief above the EOM unit, the present invention relatively reduces the specular reflectivity of the high-order transverse mode, thereby achieving the purpose of suppressing the high-order transverse mode, ensuring the stable output of the fundamental transverse mode, optimizing the beam quality, reducing the threshold current and inserting loss, to meet the single-mode application requirements of VCSEL chips.

The relief is a ring-shaped structure with a hollow center. In specific applications, the ring-shaped structure can be designed as a circular ring or a square ring. During fabrication, the surface of the fourth DBR can be embossed by dry etching or wet etching. The relief is made of polymer material, dielectric material or semiconductor material, wherein the polymer material can be selected from PI or BCB, etc.; the dielectric material can be selected from silicon nitride, silicon oxide or aluminum oxide, etc.; the semiconductor material can be selected from GaAs or AlGaAs. In the application, the design can be selected according to the actual needs, which is not limited here.

The material of the substrate is GaAs, and the thickness of the oxide isolation layer is 5-5000 nm, which can be designed with reference to the thickness of the oxide confinement layer of the traditional VCSEL structure for specific applications. The GaAs material system has higher reliability. When the resonant cavity of the VCSEL unit and the absorption region of the EOM unit are both made of GaAs material system, the material properties of the two units are similar, which can greatly improve the stability of chip epitaxial deposition and reduce the difficulty of mass production. .

Based on a GaAs material system, the material of the oxide isolation layer is Al ₂ O ₃ , which is formed by oxidizing a prefabricated layer with a material of AlxGa1 _{- xAs} through a wet oxidation process, wherein x≥0.97. Al ₂ O ₃ has good electrical insulating effect and is an ideal material for oxide isolation layer. The material of the oxide isolation prefabricated layer is AlGaAs material, which matches the lattice of the GaAs substrate system, which can realize continuous epitaxial growth, reduce the difficulty of epitaxial production, and facilitate mass production. At the same time, the epitaxial crystal quality of the VCSEL unit and the EOM unit is ensured, and the reliability of the device is improved.

The first DBR, the second DBR, the third DBR and the fourth DBR are periodic structures composed of Al _i Ga _1-i As/Al _j Ga _1-j As materials, and both i and j are not greater than 0.92. Since the oxidation isolation prefabricated layer adopts Al _x Ga _1-x As material with high aluminum content, on the one hand, in order to prevent the first DBR, the second DBR, the third DBR and the fourth DBR from being excessively oxidized, on the other hand, due to the aluminum content The higher the amount, the higher the device resistance. Therefore, it should be ensured that the materials composing the first DBR, the second DBR, the third DBR and the fourth DBR contain no more than 92% of aluminum. In addition, attention should be paid to avoid the use of aluminum arsenide materials in the application.

The resonant cavity is a sandwich structure of a lower waveguide, an active region and an upper waveguide, and a buried tunnel junction is used for optical and electrical confinement, and the cavity length of the resonant cavity is an integer multiple of the half-lasing wavelength. The gain structure of the quantum well of the resonator can be single quantum well, multiple quantum well, tunnel junction cascade quantum well or quantum dot, and the quantum well can be selected from InGaAs/GaAs, InGaAs/AlGaAs, InGaAs/GaAsP, GaAs/AlGaAs, AlInGaAs. One of /AlGaAs, InGaAsP/AlGaAs and AlGaInP/GaAs.

With the quantum well of the resonant cavity, the quantum well material of the absorption region can also select one of InGaAs/GaAs, InGaAs/AlGaAs, InGaAs/GaAsP, GaAs/AlGaAs, AlInGaAs/AlGaAs, InGaAsP/AlGaAs and AlGaInP/GaAs, But in order to achieve modulation, the quantum well wavelength of the absorption region should be controlled to be 5-99 nm shorter than the quantum well wavelength of the resonant cavity.

The absorption region is a single quantum well or a multiple quantum well structure. When the absorption region is a single quantum well structure, a third waveguide layer is arranged between the absorption region and the third DBR, and a fourth waveguide layer is arranged between the absorption region and the fourth DBR. This is because the single quantum well structure needs to form the same FP resonator as the VCSEL unit, but the FP resonator in the absorption region is a passive F-P to enhance absorption, rather than the active F-P in the VCSEL unit.

When the absorption region adopts a pair of quantum well structures, the EOM unit realizes the modulation of the light intensity of the VCSEL unit based on the quantum confinement Stark effect (QCSE). By modulating the bias voltage of the EOM unit, the movement of the absorption sideband of the absorption region can be directly realized, and then the high-speed modulation of the output light intensity of the VCSEL can be indirectly realized. Compared with the traditional direct modulation method, the high-efficiency modulation using the EOM modulation unit can reduce the constraints on the design of the VCSEL unit, thereby helping to improve the photoelectric conversion efficiency and optimize the structural design of the VCSEL unit.

When the absorption region adopts multiple pairs of quantum well structures, the EOM unit realizes the modulation of the light intensity of the VCSEL unit based on the reflectivity deviation of the top mirror and the bottom mirror. By modulating the bias voltage of the EOM unit, the absorption state of the absorption region is directly affected, thereby controlling the overall reflectivity of the top mirror, thereby indirectly realizing high-speed modulation of the output light intensity of the VCSEL.

Regarding the specific structure of the resonant cavity, the present invention provides the following two specific embodiments for selection:

As a first embodiment: the resonant cavity includes a first confinement layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second confinement layer, a P-type confinement layer and a buried tunnel junction from bottom to top; The first DBR is a first N-type doped DBR; the second DBR is a second N-type doped DBR; the third DBR is a third N-type doped DBR; the fourth DBR is a P-type doped DBR Hybrid DBR.

The reasons for setting the buried tunnel junction are: First, because PDBR has high free carrier absorption and resistance, it increases the light absorption loss and heat loss, and reduces the electrical conversion efficiency of the VCSEL unit. The VCSEL unit of the present invention adopts the buried tunnel junction to reverse the polarity of the PDBR, thereby avoiding the light absorption loss and heat loss caused by the higher free carrier absorption and resistance caused by the PDBR, which is beneficial to improve the VCSEL unit. Second, in terms of process technology, point defects and dislocations will occur at the interface between the oxide layer and the semiconductor during the oxidation process of the oxidation confinement layer, and the thermal expansion coefficients of the oxide layer and the semiconductor are different, which leads to the oxidation process usually It is very difficult to control, the process window is extremely narrow, and the oxide layer-semiconductor interface is easily cracked or peeled off after the oxidation process. The invention replaces the oxidation confinement layer of the VCSEL unit in the prior art with a buried tunnel junction to achieve electrical and optical confinement, and can avoid the problem of yield loss that traditional oxidation confinement type VCSELs often face in the key process of wet oxidation. , the production difficulty can be reduced, the production process can be simplified, and the buried tunnel junction prepared by the photolithography process has good uniformity, which greatly improves the yield.

Specifically, the buried tunnel junction includes a P-type heavily doped layer and an N-type heavily doped layer from bottom to top, and the pore diameter of the buried tunnel junction is 2-100 μm. Specifically, the material of the P-type heavily doped layer is GaInP, GaAs or AlGaAs, the material of the N-type heavily doped layer is GaInP, GaAs or AlGaAs; the thickness of the P-type heavily doped layer is in the range of 8-50 nm, the thickness of the N-type heavily doped layer ranges from 10 to 50 nm; the P-type heavily doped layer dopant atom may be C, Mg, Zn or Be, and the N-type heavily doped layer dopant atom may be Te or Se; the doping concentration of the P-type heavily doped layer and the N-type heavily doped layer is in the order of 10 ¹⁹ -10 ²⁰ cm ^-3 .

The epitaxial structure of the present invention adopts the NP-TJ-N-O-NP structure, but in practical applications, the epitaxial structure can also be adjusted to NP-TJ-N-O-PN, PN-TJ-P-O-NP, PN according to needs -TJ-P-O-PN, structure, where N refers to N-type confinement layer or N-type doped DBR, P refers to P-type confinement layer or P-type doped DBR, TJ refers to buried tunnel junction, O refers to is the oxide isolation layer.

As a second embodiment: the resonant cavity includes a first confinement layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second confinement layer and an oxide confinement layer from bottom to top; the first DBR is the first confinement layer. an N-type doped DBR; the second DBR is a first P-type doped DBR; the third DBR is a second N-type doped DBR; the fourth DBR is a second P-type doped DBR. It can be seen that the epitaxial structure provided by the present invention is an NP-O-NP structure, but in practical applications, the epitaxial structure can also be adjusted to an NP-O-PN, PN-O-NP or PN-O-PN structure as required , where N refers to the N-type doped DBR, P refers to the P-type doped DBR, and O refers to the oxide isolation layer.

When the material of the substrate is GaAs system, the thickness of the oxidation limiting layer is 5-5000 nm. The oxidation confinement layer is formed by an oxidation confinement prefabricated layer through a wet oxidation process, the oxidized region forms Al ₂ O ₃ with optical and electrical confinement functions, and the pore diameter of the unoxidized region is in the range of 2-100 μm; the oxidation confinement prefabricated layer is doped or undoped _{AlyGa1 -} yAs, where 0.92<y<x. Since the oxidation processes of the oxidation confinement prefabricated layer and the oxidation isolation prefabricated layer are carried out simultaneously, and the oxidation confinement prefabricated layer needs to be partially oxidized to form a photoelectric confinement aperture, the _{AlyGa1 -} yAs used in the oxidation confinement prefabricated layer is The aluminum content of the material should be between the DBR and the oxide isolation prefab, so it is set as 0.92<y<x. It can be seen that the prefabricated layer materials of the oxidation confinement layer and the oxidation isolation layer are all AlGaAs materials, which match the lattice of the GaAs substrate system, which ensures the epitaxial crystal quality of the VCSEL unit and the EOM unit, and improves the reliability of the device. In addition, the present invention innovatively creates a differential oxidation method. By precisely designing the aluminum content deviation of the oxidation isolation prefabricated layer and the oxidation limiting prefabricated layer, the oxidation isolation layer and the oxidation limiting layer can be formed in the same oxidation process, which greatly simplifies The chip process is improved and the production cost is reduced.

The high-efficiency vertical cavity surface EML chip further includes a first electrode, a second ring electrode, a third ring electrode and a fourth ring electrode, wherein: the first electrode is a first plane electrode disposed on the lower surface of the substrate Or the first ring electrode is arranged on the upper surface of the first DBR; the second ring electrode is arranged on the upper surface of the second DBR; the third ring electrode is arranged on the upper surface of the third DBR; Four ring electrodes are arranged on the upper surface of the fourth DBR.

Since an oxide isolation layer with electrical isolation effect is set between the VCSEL unit and the EOM unit, the electrodes cannot be shared, and a four-electrode structure is required. In practical applications, the first electrode can be set as a first plane electrode or a first ring electrode according to requirements, so as to meet different application scenarios, such as the application of TOP-TOP contact type and TOP-BOTTOM contact type.

Compared with the prior art, the beneficial effects produced by the present invention are:

1. The present invention makes a breakthrough by setting an oxide isolation layer with an electrical insulating effect between the VCSEL unit and the EOM unit to isolate the high-frequency modulation signal applied to the EOM unit, so that the VCSEL unit and the EOM unit are relatively independent, preventing high-frequency modulation signals. Affects the current in the VCSEL cell to ensure stable output of the VCSEL cell. Compared with the direct contact between the VCSEL unit and the EOM unit in the prior art, the electrical isolation can reduce the RC delay in the high-frequency signal transmission process, which helps to improve the transmission performance and achieve a better modulation effect.

2. Based on the structure of VCSEL unit + oxide isolation layer + EOM unit, the present invention reduces the specular reflectivity of the high-order transverse mode relatively by arranging relief above the EOM unit, so as to achieve the purpose of suppressing the high-order transverse mode and ensure the realization of basic The transverse mode stabilizes the output, optimizes the beam quality, reduces the threshold current and insertion loss, and meets the single-mode application requirements of VCSEL chips.

Description of drawings

FIG. 1 is a schematic diagram of a cross-sectional structure of a chip provided in Embodiment 1 of the present invention.

FIG. 2 is a schematic diagram of the resonant cavity structure of the VCSEL unit provided in the first embodiment of the present invention.

FIG. 3 is a schematic diagram of a modulation principle provided by Embodiment 1 of the present invention.

FIG. 4 is a schematic structural diagram of the relief provided by Embodiment 1 of the present invention.

FIG. 5 is a top view of the relief provided by the first embodiment of the present invention.

FIG. 6 is a schematic diagram of the control principle of the transverse mode of the relief provided by the first embodiment of the present invention.

FIG. 7 is an effect diagram of the horizontal mode control of the relief provided by the first embodiment of the present invention.

FIG. 8 is a schematic diagram of a resonant cavity structure of the VCSEL unit provided in the second embodiment of the present invention.

FIG. 9 is a schematic diagram of a modulation principle provided by Embodiment 2 of the present invention.

In the picture:

10. Substrate 11. Buffer layer

12. The first N-type doped DBR 13. Resonant cavity

14. Second N-type doped DBR 15. Oxidation isolation layer

16. The third N-type doped DBR 17. The third waveguide layer

18. Absorption region 19. Fourth waveguide layer

110, P-type doped DBR 111, first plane electrode

111', the first ring electrode 112, the second ring electrode

113, the third ring electrode 114, the fourth ring electrode

116. Relief

21. The first confinement layer 22. The first waveguide layer

23. Quantum well layer 24. Second waveguide layer

25. Second confinement layer 26. Buried tunnel junction

27. P-type confinement layer 28. Oxidation confinement layer

20. Top reflector 30. Bottom reflector.

Detailed ways

Specific embodiments of the present invention will be described below with reference to the accompanying drawings. Numerous details are described below in order to provide a thorough understanding of the present invention, but for those skilled in the art, the present invention may be practiced without these details.

Example 1:

As shown in FIG. 1 and FIG. 4 , this embodiment provides a high-efficiency vertical cavity surface EML chip with relief, which includes a VCSEL unit, an oxide isolation layer 15 , an EOM unit and a relief 116 , and the oxide isolation layer 15 is disposed on the VCSEL unit and the EOM. Between the units, it is used to prevent the potential at the contact of the two units from affecting the working current in the respective units. The relief 116 is disposed above the EOM unit for suppressing high-order transverse modes for mode control.

As shown in FIG. 1 , the VCSEL unit includes a substrate 10 , a buffer layer 11 , a first DBR 12 , a resonant cavity 13 and a second DBR 14 from bottom to top. The EOM unit includes a third DBR 16 , a third waveguide layer 17 , an absorption region 18 , a fourth waveguide layer 19 and a fourth DBR 110 from bottom to top.

As shown in FIG. 1 , the chip further includes a first electrode, a second ring electrode 112 , a third ring electrode 113 and a fourth ring electrode 114 . Specifically, in this embodiment, the first electrode is the first planar electrode 111 disposed on the lower surface of the substrate 10, and in other embodiments, the first electrode may also be the first electrode 111 disposed on the upper surface of the first DBR A ring electrode 111 ′; the second ring electrode 112 is arranged on the upper surface of the second DBR 14 ; the third ring electrode 113 is arranged on the upper surface of the third DBR 16 ; the fourth ring electrode 114 is arranged on the upper surface of the fourth DBR 110 .

Preferably, the substrate 10 is a Si-doped GaAs substrate with a doping concentration of 1.5e ¹⁸ cm ⁻³ .

Preferably, the buffer layer 11 is a Si-doped GaAs layer with a doping concentration of 2e ¹⁸ cm ⁻³ and a thickness of 200 nm.

Preferably, the first DBR 12 is a first N-type doped DBR, the second DBR 14 is a second N-type doped DBR, the third DBR 16 is a third N-type doped DBR, and the first, second, and third N-type doped DBRs DBR is high refractive index/low refractive index/high refractive index/low refractive index.../high refractive index structure, the high refractive index material is Si-doped Al _0.12 Ga _0.88 As layer, and the low refractive index material is Si-doped Al _0.9 Ga _0.1 As layer. The thickness of the Si-doped Al _0.12 Ga _0.88 As layer is 60 nm and the doping concentration is 2e ¹⁸ cm ^-3 , and the thickness of the Si-doped Al _0.9 Ga _0.1 As layer is 69.4 nm and the doping concentration is 2e ¹⁸ cm ^-3 .

As shown in FIG. 2, the optical thickness of the resonant cavity 13 is one wavelength, and the resonant cavity 13 includes a first confinement layer 21, a first waveguide layer 22, a quantum well layer 23, a second waveguide layer 24, a second confinement layer from bottom to top layer 25 , P-type confinement layer 27 and buried tunnel junction 26 .

Preferably, the first confinement layer 21 is Si-doped Al _0.6 Ga _0.4 As with a thickness of 22 nm and a doping concentration of 2e ¹⁷ cm ⁻³ .

Preferably, the first waveguide layer 22 is Al _0.45 Ga _0.55 As with a thickness of 18 nm.

Preferably, the quantum well layer 23 is a well/barrier/well/barrier/well structure composed of a barrier layer Al _0.35 Ga _0.65 As with a thickness of 10 nm and a well layer with a thickness of 8 nm GaAs, and the lasing wavelength is 850 nm.

Preferably, the second waveguide layer 24 is Al _0.45 Ga _0.55 As with a thickness of 30 nm.

Preferably, the second confinement layer 25 is Si-doped Al _0.6 Ga _0.4 As with a thickness of 62.5 nm and a doping concentration of 2e ¹⁸ cm ⁻³ .

Preferably, the P-type confinement layer 27 is C-doped AlGaAs or 1-2 pairs of P-type doped DBR, and the doping concentration is 2e ¹⁸ cm ^-3 .

Preferably, the buried tunnel junction 26 includes an Al _0.2 Ga _0.8 As heavily doped C layer and an Al _0.2 Ga _0.8 As heavily doped Te layer from bottom to top. The thickness of the Al _0.2 Ga _0.8 As heavily doped C layer is 15 nm and the doping concentration is 1.5e ²⁰ cm ^-3 ; the thickness of the Al _0.2 Ga _0.8 As heavily doped Te layer is 15 nm and the doping concentration is 2e ¹⁹ cm ^-3 , the pore size of the buried tunnel junction is 8 μm.

Preferably, the oxide isolation layer 15 is an Al ₂ O ₃ isolation layer with an electrical insulating effect formed from an undoped Al _0.98 Ga _0.02 As oxide isolation prefabricated layer with a thickness of 30 nm through a wet oxidation process, which can effectively prevent The potential at the contact of the VCSEL cell and the EOM cell affects the current in the VCSEL cell, further improving the performance of the VCSEL.

Preferably, the third waveguide layer 17 is Si-doped Al _0.45 Ga _0.55 As with a thickness of 77 nm and a doping concentration of 2e ¹⁷ cm ⁻³ .

Preferably, the absorption region 18 is a pair of quantum wells with Al _0.35 Ga _0.65 As as the barrier and GaAs as the well, the thickness of the Al _0.35 Ga _0.65 As barrier layer is 5 nm, the thickness of the GaAs well layer is 6 nm, the thickness of the absorption region 18 is 450 nm, The quantum well wavelength of region 18 is 830 nm.

Preferably, the fourth waveguide layer 19 is C-doped Al _0.45 Ga _0.55 As with a thickness of 77 nm and a doping concentration of 2e ¹⁷ cm ⁻³ . The third waveguide layer 17 and the fourth waveguide layer 19 are respectively N-type and P-type doped to form a PN junction, and the absorption region 18 is formed between the PN junctions.

Preferably, the fourth DBR 110 is a P-type doped DBR, and the P-type doped DBR is a periodically superimposed high refractive index/low refractive index/high refractive index/low refractive index.../high refractive index structure, high refractive index material is a C-doped Al _0.12 Ga _0.88 As layer, and the low refractive index material is a C-doped Al _0.9 Ga _0.1 As layer. The thickness of the C-doped Al _0.12 Ga _0.88 As layer is 60 nm and the doping concentration is 2e ¹⁸ cm ^-3 ; the thickness of the C-doped Al _0.9 Ga _0.1 As layer is 69.4 nm and the doping concentration is 2e ¹⁸ cm ^-3 .

The working principle of the buried tunnel junction 26 is as follows: buried in a degenerate heavily doped semiconductor, the Fermi level of the n-type semiconductor enters the conduction band, and the Fermi level of the p-type semiconductor enters the valence band. Due to the tunneling effect of quantum mechanics, the electrons in the conduction band of the n region may pass through the forbidden band to the p-type valence band, and the electrons in the valence band of the p region may also pass through the conduction band of the forbidden region to the n region, so that a tunnel current may be generated. Here, on the one hand, the oxide confinement layer is replaced by a buried tunnel junction 26 to achieve electrical and optical confinement. On the other hand, the buried tunnel junction 26 reverses the polarity of the PDBR, thereby avoiding the light absorption loss and heat loss caused by the higher free carrier absorption and resistance caused by the PDBR, which is beneficial to improve the light output of the VCSEL unit Efficiency; on the other hand, in terms of process technology, point defects and dislocations will occur at the interface between the oxide layer and the semiconductor during the oxidation process of the oxidation limiting layer, and the thermal expansion coefficients of the oxide layer and the semiconductor are different, which leads to the oxidation process usually It is very difficult to control, the process window is extremely narrow, and the oxide layer-semiconductor interface is easily cracked or peeled off after the oxidation process. Replacing the oxide confinement layer of the prior art VCSEL cell with a buried tunnel junction can help improve manufacturing yields. Therefore, replacing the oxide confinement layer with a buried tunnel junction to achieve optical and electrical confinement is beneficial to improve the light extraction efficiency and manufacturing yield of the VCSEL.

As shown in FIG. 3 , the modulation principle of this embodiment is: when no bias voltage or a relatively low bias voltage is applied between the third ring electrode 113 and the fourth ring electrode 114 , the absorption curve of the EOM unit and the emission wave of the VCSEL unit Compared with the long-term, it is in the blue-shift direction. At this time, the lasing beam of the VCSEL unit will not suffer absorption loss after passing through the EOM unit. When a higher bias voltage is applied to the EOM unit, due to the quantum confinement Stark effect (QCSE), its absorption spectral sidebands will rapidly shift to long wavelengths, covering the emission wavelength of the VCSEL unit, so the high-speed electrical modulation applied to the EOM unit The signal directly affects the movement of its absorption sideband, and realizes high-speed modulation of the light intensity of the VCSEL light. In this embodiment, the EOM unit and the VCSEL unit are separated by the oxide isolation layer 15, and the two are relatively independent, which helps to achieve a better modulation effect.

As shown in FIG. 4 to FIG. 7 , the material on the upper surface of the P-type DBR is selectively etched to form a relief 116. The middle of the relief 116 has an annular area of a certain size, which can be designed to have a certain width and depth according to the actual light field. The ring-shaped or square-shaped ring-shaped etched area corresponds to the high-order transverse mode exit area. Keeping the central area of the light-exit hole unchanged, the center of the light-exit hole presents an unetched area in the shape of a boss. The etched region is the exit region of the fundamental transverse mode. There is a thickness difference between the reflectivity of the etched area and the unetched area, which causes the reflectivity of the two areas to change to the beam, so the reflectivity of the etched area will be lower than that of the unetched area, and the high-order transverse mode corresponding to the etched area will be suppressed. It can be seen that by optimizing the design of the width, depth and height of the relief, the specular loss of the high-order mode here can be increased, and the specular reflectivity of the high-order mode can be relatively reduced, so as to achieve the purpose of suppressing the high-order mode lasing and effectively realize the fundamental Transverse mode stable output. Preferably, in this embodiment, the shape of the relief 116 is an annular structure, and the material of the relief 116 is GaAs.

The preparation method of the present embodiment comprises the following steps:

1. The MOCVD method is used to deposit the buffer layer 11, the first N-type doped DBR and the resonant cavity 13 in sequence on the substrate 10. The resonant cavity 13 includes a first confinement layer 21, a first waveguide layer 22, a quantum well layer 23, The second waveguide layer 24, the second confinement layer 25, the P-type confinement layer 27 and the tunnel junction layer.

2. The tunnel junction etching mask SiNx is formed on the surface of the tunnel junction layer by the enhanced plasma chemical vapor deposition method, photolithography and reactive ion etching process, and then the tunnel junction layer is etched by inductively coupled plasma to form a buried hole with a diameter of 8 μm Tunnel junction 26, and finally remove the tunnel junction etching mask SiNx by BOE.

3. Continue to grow the second N-type doped DBR, the oxide isolation prefabricated layer (Al _0.98 Ga _0.02 As), the third N-type doped DBR, the third waveguide layer 17 and the absorption region on the surface of the buried tunnel junction by MOCVD method. 18. The fourth waveguide layer 19 and the P-type doped DBR.

4. The substrate 10 is etched by ICP to expose the buffer layer 11 , and a first planar electrode 111 is prepared on the surface of the buffer layer 11 away from the first N-type doped DBR.

5. First, a contact layer selection mask SiNx is formed on the top of the second N-type doped DBR by enhanced plasma chemical vapor deposition (PECVD), photolithography and reactive ion etching (RIE) processes, and then selective by ICP etching Edge etching, so that the epitaxial structure above the top of the second N-type doped DBR is etched to the upper surface of the second N-type doped DBR, and then the contact layer selection mask SiNx is removed by BOE; The beam evaporation metal layer process and the lift-off process are used to form the second ring electrode 112 on the upper surface of the second N-type doped DBR.

6. The oxidation isolation prefabricated layer with the composition Al _0.98 Ga _0.02 As is oxidized by the wet oxidation process to form the oxide isolation layer 15 with the composition Al ₂ O ₃ .

7. Referring to the method of step 5, the third ring electrode 113 is formed on the upper surface of the third N-type doped DBR, but it should be noted that when performing ICP etching, the epitaxial structure must be more than 200 nm away from the bottom of the third N-type doped DBR. Selective edge etching is performed to prevent the oxide isolation layer 15 from being etched through, causing the oxide isolation layer 15 to fail. Then, a fourth ring electrode 114 is fabricated on the upper surface of the P-type doped DBR by using the prior art.

8. On the upper surface of the P-type doped DBR, dry etching or wet etching is used to form a surface relief 116 .

It should be noted that, in step 6, the reasons for choosing the oxidation process of oxidizing the isolation prefabricated layer after the first plane electrode 111 and the second ring electrode 112 are prepared are: first, the metal layer can be fully utilized in the oxidation process (That is, the advantage of the more accurate alignment of the first planar electrode 111 and the second ring electrode 112 ensures that the oxidation process is precise and controllable; secondly, the etching process of the first planar electrode 111 and the second ring electrode 112 will reduce the oxidation process. The oxidation area can greatly save the oxidation time and help to improve the uniformity of oxidation; thirdly, the oxidation isolation prefabricated layer will generate stress after oxidation, which will have a certain impact on the etching step of the metal electrode part, so it is necessary to first The metal electrode portion is fabricated.

The reason why the third ring electrode 113 and the fourth ring electrode 114 are prepared after the oxidation process is that it is necessary to observe whether the oxidation isolation prefabricated layer is sufficiently oxidized to form the oxidation isolation layer 15 under an infrared microscope during the oxidation process. If the layer is oxidized again, it is unfavorable to observe the morphology of the oxide isolation layer 15 .

Embodiment 2:

As shown in FIGS. 1 and 4 , the structural design of this embodiment is basically the same as that of the first embodiment, but there are differences in the structure of the resonant cavity 13 , the modulation principle of the EOM unit and the fabrication method of the VCSEL chip. First, the structure of the resonant cavity 13 in this embodiment will be described:

As shown in FIG. 8 , the resonant cavity 13 includes a first confinement layer 21 , a first waveguide layer 22 , a quantum well layer 23 , a second waveguide layer 24 , a second confinement layer 25 , and an oxide confinement layer 28 from bottom to top.

Preferably, the oxidation confinement layer 28 is formed of an undoped Al _0.93 Ga _0.07 As oxidation confinement prefabricated layer with a thickness of 30 nm through a wet oxidation process. Al ₂ O ₃ .

As shown in FIG. 1, based on the difference of the resonant cavity 13, the first to fourth DBRs in this embodiment are also different from those in the first embodiment:

The first DBR 12 is a first N-type doped DBR, the third DBR 16 is a second N-type doped DBR, and the first N-type doped DBR and the second N-type doped DBR are high refractive index/low refractive index/high Refractive index/low refractive index.../high refractive index structure, the high refractive index material is a Si-doped Al _0.12 Ga _0.88 As layer, and the low refractive index material is a Si-doped Al _0.9 Ga _0.1 As layer. The thickness of the Si-doped Al _0.12 Ga _0.88 As layer is 60 nm and the doping concentration is 2e ¹⁸ cm ^-3 , and the thickness of the Si-doped Al _0.9 Ga _0.1 As layer is 69.4 nm and the doping concentration is 2e ¹⁸ cm ^-3 .

The second DBR 14 is a first P-type doped DBR, the fourth DBR 110 is a second P-type doped DBR, and the first P-type doped DBR and the second P-type doped DBR are periodically superimposed high refractive index/low refractive index rate/high refractive index/low refractive index.../high refractive index structure, the high refractive index material is a C-doped Al _0.12 Ga _0.88 As layer, and the low refractive index material is a C-doped Al _0.9 Ga _0.1 As layer. The thickness of the C-doped Al _0.12 Ga _0.88 As layer is 60 nm and the doping concentration is 2e ¹⁸ cm ^-3 ; the thickness of the C-doped Al _0.9 Ga _0.1 As layer is 69.4 nm and the doping concentration is 2e ¹⁸ cm ^-3 .

The modulation mode in this embodiment is described in detail below:

In this embodiment, the third waveguide layer 17 and the fourth waveguide layer 19 are not provided, and the absorption region 18 is a plurality of pairs of quantum wells with Al _0.35 Ga _0.65 As as the barrier and GaAs as the well, and the thickness of the Al _0.35 Ga _0.65 As barrier layer is 5 nm. The thickness of the GaAs well layer is 6 nm, and the thickness of the absorption region is 450 nm. Increasing the period number of the quantum well of the absorption region 18 can reduce the period number of the top P-type doped DBR 110 .

As shown in FIG. 1 , the bottom mirror 30 is the part below the resonator 13 , and the top mirror 20 is the part above the resonator 13 . For the lasing wavelength of the cavity 13 of 850 nm, the overall reflectivity of the bottom reflector 30 can be designed to be 99.995%, and the overall reflectivity of the top reflector 20 can be designed to be 99.89%. The absorbing region 18 of the EOM cell is placed where the light intensity of the top mirror 20 is maximum.

As shown in FIG. 9 , the modulation principle of this embodiment is: when no bias voltage or a relatively low bias voltage is applied between the third ring electrode 113 and the fourth ring electrode 114 , the absorption region 18 in the EOM unit is in a non-absorbing state At this time, the reflectivity of the bottom mirror 30 is 99.995%, and the reflectivity of the top mirror 20 is 99.89%. The photons emitted by the quantum well 23 can form a continuous and stable back-and-forth oscillation in the resonant cavity 13. After the gain reaches a certain value The light output can be formed through the top reflector 20; when a higher bias voltage is applied between the third ring electrode 113 and the fourth ring electrode 114, the absorption effect of the absorption region 18 in the EOM unit is strengthened, and the reflectivity of the top reflector 20 It drops to 99.68%. At this time, the photons emitted by the quantum well 23 cannot oscillate continuously and stably in the resonant cavity 13, or the gain is insufficient, the light intensity cannot penetrate the top reflector 20 to stabilize the light output, or the output laser power is reduced. Therefore, by modulating the bias level of the EOM unit and changing the working state of the absorption region 18, the reflectivity of the top DBR can be affected, thereby realizing high-speed modulation of the light intensity of the VCSEL unit.

The preparation method of the VCSEL chip of the present embodiment is described in detail below: it includes the following steps:

1. On the substrate 10, the buffer layer 11, the first N-type doped DBR, the resonator 13, the first P-type doped DBR, the oxide isolation prefabricated layer, the second N-type doped DBR, the first N-type doped DBR, the first N-type doped DBR, the first Three waveguide layers 17, an absorption region 18, a fourth waveguide layer 19, and a second P-doped DBR; the resonant cavity 13 includes a first confinement layer 21, a first waveguide layer 22, a quantum well layer 23, a second waveguide layer 24, a Two confinement layers 25, an oxidation confinement prefabricated layer.

2. The substrate 10 is etched by ICP to expose the buffer layer 11 , and a first planar electrode is prepared on the surface of the buffer layer 11 away from the first N-type doped DBR.

3. First, a contact layer selection mask SiNx is formed on the upper surface of the first P-type doped DBR through enhanced plasma chemical vapor deposition (PECVD), photolithography and reactive ion etching (RIE) processes, and then ICP etching is performed. Selective edge etching, so that the epitaxial structure above the top of the first P-type doped DBR is etched to the upper surface of the first P-type doped DBR, and then the contact layer selection mask SiNx is removed by BOE; finally, the photolithography process is used. , an electron beam evaporation metal layer process and a lift-off process to form a second ring electrode 112 on the upper surface of the first P-type doped DBR.

4. The oxidation isolation prefabricated layer with the composition Al _0.98 Ga _0.02 As and the oxidation limiting prefabricated layer with the composition Al _0.93 Ga _0.07 As are oxidized by the wet oxidation process to form the oxidation isolation layer 15 of Al ₂ O ₃ and the oxidation limit Layer 28.

5. Referring to the method of step 4, the third ring electrode 113 is fabricated on the upper surface of the second N-type doped DBR, but it should be noted that when performing ICP etching, the epitaxial structure must be more than 200 nm away from the bottom of the second N-type doped DBR. Selective edge etching is performed to prevent the oxide isolation layer 15 from being etched through, causing the oxide isolation layer 15 to fail. Then, a fourth ring electrode 114 is formed on the upper surface of the second P-type doped DBR by using the prior art.

6. On the upper surface of the second P-type doped DBR, dry etching or wet etching is used to form relief 116 .

The above are only specific embodiments of the present invention, but the design concept of the present invention is not limited to this, and any non-substantial modification of the present invention by using this concept should be regarded as an act of infringing the protection scope of the present invention.

Claims (10)

1. The utility model provides a take high-efficient vertical cavity surface EML chip of relief (sculpture), its characterized in that: the device comprises a VCSEL unit, an oxidation isolation layer, an EOM unit and a relief, wherein:

the VCSEL unit comprises a substrate, a buffer layer, a first DBR, a resonant cavity and a second DBR from bottom to top;

the EOM unit comprises a third DBR, an absorption region and a fourth DBR from bottom to top;

the oxidation isolation layer is arranged between the VCSEL unit and the EOM unit and used for preventing the electric potential of the contact position of the two units from influencing the working current in the respective units;

the relief is arranged above the EOM unit and used for restraining a high-order transverse mode so as to realize mode control.

2. The high-efficiency vertical-cavity surface EML chip with relief of claim 1, wherein: the material of the oxidation isolation layer is Al ₂ O ₃ Which is made of Al _x Ga _1-x The As prefabricated layer is formed by oxidation through a wet oxidation process, wherein x is more than or equal to 0.97; the first DBR, the second DBR, the third DBR and the fourth DBR are made of Al _i Ga _1-i As/Al _j Ga _1-j The As material has a periodic structure, and i and j are not more than 0.92.

3. The high-efficiency vertical-cavity surface EML chip with relief of claim 2, wherein: the resonant cavity comprises a first limiting layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second limiting layer, a P-type limiting layer and a buried tunnel junction from bottom to top; the first DBR is a first N-type doped DBR; the second DBR is a second N-type doped DBR; the third DBR is a third N-type doped DBR; the fourth DBR is a P-type doped DBR.

4. The high-efficiency vertical-cavity surface EML chip with relief of claim 2, wherein: the resonant cavity comprises a first limiting layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a second limiting layer and an oxidation limiting layer from bottom to top; the first DBR is a first N-type doped DBR; the second DBR is a first P-type doped DBR; the third DBR is a second N-type doped DBR; the fourth DBR is a second P-type doped DBR.

5. The high-efficiency vertical-cavity surface EML chip with relief of claim 4, wherein: the oxidation limiting layer is formed by an oxidation limiting prefabricated layer through a wet oxidation process, and the aperture range of an unoxidized area is 2-100 mu m; the oxidation limiting prefabricated layer is doped or undoped Al _y Ga _1-y As, wherein 0.92 < y < x.

6. The high-efficiency vertical-cavity surface EML chip with relief of claim 1, wherein: the wavelength of the quantum well of the absorption region is 5-99nm shorter than that of the quantum well of the resonant cavity.

7. The high-efficiency vertical-cavity surface EML chip with relief of claim 1, wherein: still include first electrode, second annular electrode, third annular electrode and fourth annular electrode, wherein: the first electrode is a first planar electrode arranged on the lower surface of the substrate or a first annular electrode arranged on the upper surface of the first DBR; the second annular electrode is arranged on the upper surface of the second DBR; the third ring electrode is arranged on the upper surface of the third DBR; the fourth ring-shaped electrode is disposed on an upper surface of the fourth DBR.

8. The high-efficiency vertical-cavity surface EML chip with relief of claim 1, wherein: the embossment is of an annular structure with a hollow middle part.

9. The high-efficiency vertical-cavity surface EML chip with relief of claim 8, wherein: the relief is in a circular ring structure or a square ring structure.

10. The embossed high-efficiency vertical-cavity surface EML chip of claim 9, wherein: the relief is made of a polymer material, a dielectric material or a semiconductor material, wherein the polymer material is PI or BCB; the dielectric material is silicon nitride, silicon oxide or aluminum oxide; the semiconductor material is GaAs or AlGaAs.

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