CN114937704A - Distributed groove electrode power device and manufacturing method thereof - Google Patents
Distributed groove electrode power device and manufacturing method thereof Download PDFInfo
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Abstract
本发明公开了一种分布式凹槽电极功率器件及其制作方法，主要解决现有肖特基二极管开启电压高和输出电流小的问题，其包括：衬底(1)、过渡层(2)、势垒层(3)、钝化层(4)，钝化层(4)的左侧设置有阴极(6)，势垒层(3)和钝化层(4)的右侧设置有凹槽阳极(12)，凹槽阳极(12)的底部位于过渡层(2)中，凹槽阳极(12)的表面和钝化层(4)右侧的表面设有互连金属(13)，互连金属(13)中部的下方设有M个右阵列块(11)，互连金属(13)左部的下方设有N个左阵列块(10)，右阵列块(11)和左阵列块(10)的下部位于过渡层(2)中。本发明开启电压小，导通电流大，可作为电力电子系统的基本器件。
The invention discloses a distributed groove electrode power device and a manufacturing method thereof, which mainly solve the problems of high turn-on voltage and small output current of the existing Schottky diode, comprising: a substrate (1) and a transition layer (2) , a barrier layer (3), a passivation layer (4), the left side of the passivation layer (4) is provided with a cathode (6), and the right side of the barrier layer (3) and the passivation layer (4) is provided with a concave The groove anode (12), the bottom of the groove anode (12) is located in the transition layer (2), and the surface of the groove anode (12) and the surface on the right side of the passivation layer (4) are provided with interconnection metal (13), M right array blocks (11) are arranged under the middle of the interconnection metal (13), and N left array blocks (10) are arranged under the left part of the interconnection metal (13). The right array block (11) and the left array The lower part of the block (10) is located in the transition layer (2). The present invention has small turn-on voltage and large on-current, and can be used as a basic device of a power electronic system.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and relates to a power device adopting a distributed groove structure, which can be used for a power electronic system.
Technical Field
Since only majority carriers participate in the conduction of the schottky barrier diode, the schottky barrier diode does not have the problems of minority carrier lifetime and reverse recovery, and plays a crucial role in power converters and inverters. As the operating frequency of the circuit increases, the performance of the schottky barrier diode must also increase to maintain high power conversion efficiency. Due to the excellent material properties of GaN, such as high breakdown field strength, good thermal properties, and high electron mobility, GaN-based schottky barrier diodes have received much attention from researchers in high power and high frequency applications. In recent years, a great deal of constructive research work has been carried out at home and abroad for high-performance GaN schottky barrier diodes, and especially, the transverse AlGaN/GaN schottky barrier diodes are widely researched due to the advantage that the transverse AlGaN/GaN schottky barrier diodes are compatible with the plane process of the AlGaN/GaN high electron mobility transistor. The lateral AlGaN/GaN Schottky barrier diode is beneficial to realizing the monolithic integration of the Schottky barrier diode device and the high electron mobility transistor device, thereby reducing parasitic elements and increasing the flexibility of design.
A conventional lateral AlGaN/GaN schottky barrier diode structure, as shown in fig. 1, includes: the structure comprises a substrate 1, a transition layer 2, a barrier layer 3, a passivation layer 4, a cathode 5 and an anode 6; a passivation layer 4 is deposited on the barrier layer 3, a cathode 5 is deposited on the left side of the upper surface of the barrier layer 3, and an anode 6 is deposited on the right side of the upper surface of the barrier layer 3. The conventional AlGaN/GaN Schottky barrier diode has high turn-on voltage and small output current, and the efficiency and the output power of a power electronic circuit and a system are seriously limited. In order to improve the above-mentioned problems of the conventional lateral AlGaN/GaN schottky barrier diode, researchers have proposed a lateral AlGaN/GaN schottky barrier diode having a recessed anode structure, however, the recessed anode structure has a very limited capability of lowering the turn-on voltage, and the increased recessed structure reduces the current conduction path, thereby resulting in a reduction in the output current and thus a reduction in the system operation efficiency.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a distributed groove electrode power device and a manufacturing method thereof, so as to reduce the starting voltage and increase the output current of the device.
In order to achieve the purpose, the technical scheme of the invention is as follows:
1. a distributed groove electrode power device comprises from bottom to top: substrate 1, transition layer 2, barrier layer 3, passivation layer 4, above the barrier layer 3, the left side of passivation layer 4 is provided with cathode slot 5, is provided with negative pole 6 above cathode slot 5, and the right side of barrier layer 3 and passivation layer 4 is provided with recess anode 12, and the bottom of recess anode 12 is arranged in transition layer 2, its characterized in that:
the surface of the groove anode 12 is provided with interconnection metal 13;
m right array blocks 11 and N left array blocks 10 are sequentially distributed below the interconnection metal 13 and on the left side of the groove anode 12, and the lower parts of the right array blocks 11 and the left array blocks 10 are located in the transition layer 2.
Further, the substrate 1 is made of sapphire, silicon carbide, silicon or graphene.
Further, the thickness a of the barrier layer 3 is 3nm to 100 nm; the thickness b of the passivation layer 4 is 5 nm-1000 nm; the heights c of the M right array blocks 11, the N left array blocks 10 and the groove anode 12 are the same, and c is larger than a + b.
Further, the N left array blocks 10 and the M right array blocks 11 are distributed in a staggered manner.
Further, the minimum spacing d between the left array block 10 and the right array block 11 is greater than 0; the distance e between the right array block 11 and the groove anode 12 is greater than 0.
Further, the left array block 10 is composed of N metal cuboid blocks with equal intervals, the interval f is larger than 0, and N is larger than or equal to 1; the right array block 11 is composed of M metal cuboid blocks with equal intervals, the interval g of the metal cuboid blocks is larger than 0, and M is larger than or equal to 2.
2. The invention discloses a method for manufacturing a distributed groove electrode power device, which comprises the following steps:
A) extending GaN semiconductor material on a substrate 1 to form a transition layer 2;
B) extending GaN-based wide bandgap semiconductor material on the transition layer 2 to form a barrier layer 3;
C) depositing an insulator on the barrier layer 3 to form a passivation layer 4;
D) manufacturing a mask on the passivation layer 4 for the first time, etching the left side of the passivation layer 4 by using the mask until the upper surface of the barrier layer 3 is etched to form a cathode slot 5;
E) making masks on the passivation layer 4 and the cathode slot 5 for the second time, depositing metal on the cathode slot 5 and the passivation layer 4 by using the masks, and performing rapid thermal annealing to form a cathode 6;
F) making masks on the passivation layer 4 and the cathode 6 for the third time, etching the right side of the passivation layer 4 by using the masks until the etching is performed below the lower surface of the barrier layer 3, and forming N left array block grooves 7, M right array block grooves 8 and anode grooves 9;
G) and manufacturing masks on the passivation layer 4, the cathode 6, the left array block groove 7, the right array block groove 8 and the anode slot 9 for the fourth time, and depositing metal on the left array block groove 7, the right array block groove 8 and the anode slot 9 by using the masks to form N left array blocks 10, M right array blocks 11, groove anodes 12 and interconnection metal 13 so as to finish the manufacture of the whole device.
Compared with a groove anode transverse AlGaN/GaN Schottky barrier diode device, the device has the following advantages:
1. because the device adopts the structures of the right array block 11 and the left array block 10, when the groove anode 12 of the device applies positive voltage, current carriers can flow in from the edges of the array block and the groove anode 12, so that the addition of the structures of the right array block 11 and the left array block 10 is equivalent to the increase of the contact area between the anode of the Schottky barrier diode and the current, the efficiency of the current carriers for tunneling the Schottky barrier is improved, the starting voltage is reduced, and the conduction current is increased.
2. The device adopts a distributed array structure, and the anode end metal blocks are connected in parallel, so that the voltage drop of the anode end during conduction is reduced, and the starting voltage is reduced.
Drawings
FIG. 1 is a block diagram of a conventional AlGaN/GaN SBD;
FIG. 2 is a top view of a distributed notch electrode power device of the present invention;
FIG. 3 is a cross-sectional view of the device of the present invention taken along line AA' in a top view;
FIG. 4 is a cross-sectional view of the device of the present invention taken along line BB' in a top view;
FIG. 5 is a cross-sectional view of the device of the present invention taken along line CC' in a top view;
FIG. 6 is a schematic diagram of a flow chart for manufacturing a distributed groove electrode power device according to the present invention;
fig. 7 is a graph of the forward on output characteristics of a device of the present invention and a conventional device.
Detailed Description
Embodiments and effects of the present invention are described in further detail below with reference to the accompanying drawings.
Referring to fig. 2, 3, 4, and 5, the distributed groove electrode power device of the present example includes: the structure comprises a substrate 1, a transition layer 2, a barrier layer 3, a passivation layer 4, a cathode slot 5, a cathode 6, a left array block groove 7, a right array block groove 8, an anode slot 9, a left array block 10, a right array block 11, a groove anode 12 and interconnection metal 13. Wherein:
the substrate 1 is made of sapphire, silicon carbide, silicon or graphene materials;
the transition layer 2 is positioned on the upper part of the substrate 1, the thickness of the transition layer is 3-100 mu m, and the doping concentration is 1 multiplied by 10 15 ～1×10 18 cm -3 ；
The barrier layer 3 is positioned on the upper part of the transition layer 2 and is composed of a plurality of layers of same or different GaN-based wide bandgap semiconductor materials, and the thickness a is 3 nm-100 nm;
the passivation layer 4 is arranged on the barrier layer 3 and is made of SiO 2 、SiN、Al 2 O 3 、Sc 2 O 3 、HfO 2 、TiO 2 Any one of the above materials or other insulating dielectric materials, the thickness b is 5 nm-1000 nm;
the cathode slot 5 is positioned at the left side of the passivation layer 4, and the lower surface of the cathode slot is in contact with the barrier layer 3;
the cathode 6 is positioned at the upper part of the cathode slot 5, and the cathode 6 forms good ohmic contact with a semiconductor below;
the left array block groove 7, the right array block groove 8 and the anode groove 9 are sequentially distributed on the right sides of the passivation layer 4 and the barrier layer 3 from left to right, the lower parts of the left array block groove 7, the right array block groove 8 and the anode groove 9 are positioned in the transition layer 2, the heights c of the left array block groove 7, the right array block groove 8 and the anode groove 9 are the same, and c is greater than a + b;
the left array block 10 is positioned at the upper part of the left array block groove 7, the right array block 11 is positioned at the upper part of the right array block groove 8, the groove anode 12 is positioned at the upper part of the anode groove 9, the left array block 10, the right array block 11 and the groove anode 12 form Schottky contact with surrounding semiconductors, the minimum distance d between the left array block 10 and the right array block 11 is larger than 0, and the distance e between the right array block 11 and the groove anode 12 is larger than 0; the left array block 10 is composed of N metal cuboid blocks with equal intervals, the interval f is larger than 0, and N is larger than or equal to 1; the right array block 11 is composed of M metal cuboid blocks with equal intervals, the interval g of the metal cuboid blocks is greater than 0, and M is greater than or equal to 2;
the interconnect metal 13 is located on the upper surfaces of the left array block 10, the right array block 11 and the groove anode 12.
Referring to fig. 6, the method for manufacturing a distributed groove electrode power device of the present invention provides the following three examples.
The first embodiment is as follows: and manufacturing a distributed groove electrode power device with the thickness a of the barrier layer 3 being 3nm, the thickness b of the passivation layer 4 being 5nm, the height c of the array block and the groove anode 12 being 17nm and 1 left array block 10 and 2 right array blocks 11.
Using metal organic chemical vapor deposition technology, setting the temperature at 950 ℃, the pressure at 40Torr and using SiH 4 Is a doping source, the hydrogen flow is 4000sccm, the ammonia flow is 4000sccm, and the gallium source flow is 100 mu mol/minOn a sapphire substrate 1, the epitaxial thickness is 1 μm and the doping concentration is 1X 10 15 cm -3 N of (A) to (B) - And a type GaN transition layer 2.
Using molecular beam epitaxy technique, setting vacuum degree to be less than or equal to 1.0 × 10 -10 mbar, radio frequency power of 400W, and N as reactant 2 High purity Ga source, high purity Al source, epitaxial growth of Al with thickness a of 3nm on GaN transition layer 2 0.5 Ga 0.5 N material forming the barrier layer 3.
Setting N using plasma enhanced chemical vapor deposition technique 2 O flow rate of 850sccm, SiH 4 Depositing SiO on the barrier layer 3 under the process conditions of the flow of 200sccm, the temperature of 250 ℃, the RF power of 25W and the pressure of 1100mTorr 2 To produce a passivation layer 4 having a thickness of 5 nm.
And 4, manufacturing a cathode slot 5 as shown in fig. 6 d.
Making a mask on the upper part of the passivation layer 4 for the first time, setting Cl by using a reactive ion etching technology 2 Etching the left side of the passivation layer 4 by using the mask under the process conditions of 15sccm, 10mTorr of pressure and 100W of power until the upper surface of the barrier layer 3 to form the cathode slot 5.
And 5, manufacturing the cathode 6 as shown in fig. 6 e.
Making a mask on the passivation layer 4 and the upper part of the etched cathode slot 5 for the second time, and setting the vacuum degree to be 1.8 multiplied by 10 - 3 Pa, power 350W, evaporation rate
Depositing metal on the upper part of the etched table top by using an electron beam evaporation technology, wherein the deposited metal is a Ti/Au/Ni metal combination, namely Ti, Au and Ni are respectively deposited from bottom to top, and the thicknesses of the deposited metal are 0.02 mu m, 0.3 mu m and 0.05 mu m in sequence; then setting the temperature to 850 ℃ and the process condition of 35s for depositionThe metal of (2) is subjected to rapid thermal annealing to complete the manufacture of the cathode 6.
Making a mask on the upper parts of the cathode 6 and the passivation layer 4 for the third time, and setting Cl 2 The right side of the passivation layer 4 is etched by using the mask under the process conditions of 15sccm flow, 10mT pressure and 100W power, the etching depth is 17nm, and a left array block groove 7, two right array block grooves 8 and an anode groove 9 are formed by etching at the same time.
Step 7. make a left array block 10, two right array blocks 11, trench anodes 12 and interconnect metal 13, as in fig. 6 g.
Making masks on the upper parts of the cathode 6, the passivation layer 4, the left array block groove 7, the right array block groove 8 and the anode groove 9 for the fourth time, and setting the vacuum degree to be less than or equal to 1.6 multiplied by 10 -3 Pa, power set at 350W, evaporation rate at
According to the technical conditions of the method, metal is deposited on the right side of the upper portion of a passivation layer 4, the upper portions of a left array block groove 7, a right array block groove 8 and an anode groove 9 by using the mask and adopting an electron beam evaporation technology, wherein the deposited metal is Ni, the thickness of the deposited metal is 0.207 mu m, Schottky contact is manufactured, a left array block 10, a right array block 11, a groove anode 12 and interconnection metal 13 are formed, and the manufacture of the device is completed.
Example two: and manufacturing a distributed groove electrode power device with the thickness a of the barrier layer 3 being 50nm, the thickness b of the passivation layer 4 being 500nm, the height c of the array block and the groove anode 12 being 700nm and 2 left array blocks 10 and 3 right array blocks 11.
Step one, a transition layer 2 is manufactured, as shown in fig. 6 a.
And (3) performing epitaxial growth of a GaN material with the thickness of 4.9 mu m on the silicon carbide substrate 1 by using a metal organic chemical vapor deposition technology under the process conditions of the temperature of 1000 ℃, the pressure of 45Torr, the hydrogen flow of 4600sccm, the ammonia flow of 4600sccm and the gallium source flow of 120 mu mol/min to finish the manufacture of the transition layer 2.
Step two, epitaxial Al 0.1 Ga 0.9 N, the barrier layer 3 is produced, as shown in fig. 6 b.
Using molecular beam epitaxy technique under vacuum degree of 1.0 × 10 -11 mbar, radio frequency power of 420W, and N as reactant 2 Al with the thickness of 50nm is epitaxially grown on the GaN transition layer 2 under the process conditions of the high-purity Ga source and the high-purity Al source 0.1 Ga 0.9 N material forming the barrier layer 3.
Step three, depositing SiO 2 And a passivation layer 4 is fabricated, as shown in fig. 6 c.
Using plasma enhanced chemical vapor deposition techniques at N 2 O flow rate of 850sccm, SiH 4 SiO with the thickness of 500nm is deposited on the barrier layer 3 under the process conditions of the flow of 200sccm, the temperature of 250 ℃, the RF power of 25W and the pressure of 1100mTorr 2 And a passivation layer 4 is formed.
Step four, manufacturing the cathode slot 5 as shown in figure 6 d.
A first mask is made on the upper part of the passivation layer 4 by using a reactive ion etching technique in Cl 2 And etching the left side of the passivation layer 4 by using the mask until the upper surface of the barrier layer 3 is etched under the process conditions of the flow of 15sccm, the pressure of 10mTorr and the power of 110W to form the cathode slot 5.
Step five, manufacturing the cathode 6 as shown in fig. 6 e.
Making a mask on the passivation layer 4 and the etched cathode trench 5 for the second time, depositing metal on the etched cathode trench 5 by electron beam evaporation technology, and vacuum degree less than 1.8 × 10 -3 Pa, power 400W, evaporation rate
Under the process conditions of (1), depositing Ti/Al/Ni/Au metal combinations, namely Ti, Al, Ni and Au from bottom to top, wherein the thicknesses of the Ti/Al/Ni/Au metal combinations are 0.02 mu m, 0.14 mu m, 0.055 mu m and 0.045 mu m in sequence; then, rapid thermal annealing was performed at 860 ℃ for 30 seconds, thereby completing the fabrication of the cathode 6.
And sixthly, manufacturing a left array block groove 7, a right array block groove 8 and an anode groove 9, as shown in fig. 6 f.
A third mask is made on the upper parts of the cathode 6 and the passivation layer 4, and the reactive ion etching technology is used to etch Cl 2 Under the process conditions of 15sccm flow, 10mTorr pressure and 110W power, the right side of the passivation layer 4 is etched by the mask with the depth of 700nm to form two left array block grooves 7, three right array block grooves 8 and an anode groove 9.
Step seven, manufacturing a left array block 10, a right array block 11, a groove anode 12 and an interconnection metal 13, as shown in FIG. 6 g.
Making masks on the upper parts of the cathode 6, the passivation layer 4, the left array block groove 7, the right array block groove 8 and the anode groove 9 for the fourth time, adopting an electron beam evaporation technology, and keeping the vacuum degree at 1.6 multiplied by 10 -3 Pa, power 350W, evaporation rate
Under the process conditions of (1), metal Wu is deposited on the right side of the upper part of the passivation layer 4, the upper parts of the left array block groove 7, the right array block groove 8 and the anode groove 9 to make Schottky contact, and a left array block 10, a right array block 11, a groove anode 12 and interconnection metal 13 are formed.
Example three: the thickness a of the barrier layer 3 is 100nm, the thickness b of the passivation layer 4 is 1 mu m, the height c of the array block and the groove anode 12 is 1.5 mu m, and the distributed groove electrode power device is provided with three left array blocks 10 and four right array blocks 11.
Step a. make the transition layer 2, as in fig. 6 a.
The temperature is 950 ℃, the pressure is 40Torr, and SiH is adopted 4 Is a doping source with hydrogen flow of 4000sccm, ammonia flow of 4000sccm and gallium source flow of 100 mu mol/min, and is prepared by epitaxially growing on a silicon substrate 1 to a thickness of 3 mu m and a doping concentration of 1 × 10 18 cm -3 N of (a) - And a type GaN transition layer 2.
Step B, epitaxial Al 0.01 Ga 0.99 N, the barrier layer 3 is produced, as shown in fig. 6 b.
The vacuum degree is less than or equal to 1.0 multiplied by 10 -10 mbar, radio frequency power of 400W, and N as reactant 2 High-purity Ga source and high-purity Al sourceBy using molecular beam epitaxy technique, epitaxial growth of 100 nm-thick Al on GaN transition layer 2 0.01 Ga 0.99 N material forming the barrier layer 3.
Step C, depositing SiO 2 And a passivation layer 4 is fabricated, as shown in fig. 6 c.
The temperature was set at 250 deg.C, RF power at 25W, and pressure at 1100mTorr, N 2 O flow rate of 850sccm, SiH 4 Depositing SiO on the barrier layer 3 by using the plasma enhanced chemical vapor deposition technology under the process condition of the flow rate of 200sccm 2 To produce a passivation layer 4 having a thickness of 1 μm.
Step D, manufacturing the cathode slot 5 as shown in FIG. 6 d.
A first mask is made on the upper part of the passivation layer 4 by using Cl 2 Etching the left side of the passivation layer 4 by using a reactive ion etching technology under the process conditions of 15sccm, 10mTorr of pressure and 100W of power until the upper surface of the barrier layer 3 to form the cathode slot 5.
Step e. make cathode 6, as shown in fig. 6 e.
Making a mask on the passivation layer 4 and the upper part of the cathode slot 5 formed by etching for the second time, wherein the vacuum degree is less than 1.8 multiplied by 10 - 3 Pa, power 500W, evaporation rate
Depositing metal on the upper part of the etched cathode slot 5 by using an electron beam evaporation technology, wherein the deposited metal is a Ti/Al/Mo/Au metal combination, namely Ti, Al, Mo and Au are respectively from bottom to top, and the thicknesses of the deposited metal are 0.02 mu m, 0.1 mu m, 0.03 mu m and 0.03 mu m in sequence; and (3) carrying out rapid thermal annealing by adopting the process conditions of 860 ℃ and 30s to finish the manufacture of the cathode 6.
And F, manufacturing a left array block groove 7, a right array block groove 8 and an anode groove 9, as shown in FIG. 6 f.
Making a mask on the cathode 6 and the passivation layer 4 for the third time, using CF 4 The flow rate was 45sccm, O 2 The flow is 5sccm, the pressure is 15mTorr, the power is 300W, and the reactive ion etching technology is used for etching the right side of the passivation layer 4Etching the positions to form three left array block grooves 7, four right array block grooves 8 and an anode groove 9 with the depth of 1.5 mu m.
Step g. make left array block 10, right array block 11, trench anodes 12 and interconnect metal 13, as in fig. 6 g.
Making masks on the upper parts of the cathode 6, the passivation layer 4, the left array block groove 7, the right array block groove 8 and the anode groove 9 for the fourth time, and setting the vacuum degree to be 1.6 multiplied by 10 -3 Pa, power 350W, evaporation rate
According to the process conditions, an electron beam evaporation technology is adopted, metal is deposited on the right side of the upper portion of the passivation layer 4, the left array block groove 7, the right array block groove 8 and the upper portion of the anode groove 9 through the mask to form Schottky contact, the deposited metal is Mo, three left array blocks 10, four right array blocks 11, a groove anode 12 and interconnection metal 13 are formed, and the whole device is manufactured.
The effects of the present invention can be further illustrated by the following simulations.
Simulation: forward conduction output characteristic simulations were performed on the conventional lateral AlGaN/GaN schottky barrier diode and the device according to the second embodiment of the present invention, respectively, and the results are shown in fig. 7. As can be seen from fig. 7, the turn-on voltage of the device of the present invention is 0.36V, the turn-on voltage of the conventional device is 0.75V, and the output current of the device of the present invention is larger than that of the conventional device. Therefore, compared with the traditional device, the device has the advantages that the turn-on voltage is reduced, and the output current is remarkably increased.
The foregoing description is only three specific embodiments of the present invention and is not intended to limit the present invention, and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made in the method according to the present invention without departing from the principle and scope of the invention, but these modifications and variations are within the scope of the invention as defined in the appended claims.
Claims (10)
1. A distributed groove electrode power device comprises from bottom to top: substrate (1), transition layer (2), barrier layer (3), passivation layer (4), above barrier layer (3), the left side of passivation layer (4) is provided with negative pole groove (5), is provided with negative pole (6) above negative pole groove (5), and the right side of barrier layer (3) and passivation layer (4) is provided with recess anode (12), and the bottom of recess anode (12) is arranged in transition layer (2), its characterized in that:
the surfaces of the right sides of the groove anode (12) and the passivation layer (4) are provided with interconnection metal (13);
m right array blocks (11) are arranged below the middle part of the interconnection metal (13), N left array blocks (10) are arranged below the left part of the interconnection metal (13), and the lower parts of the right array blocks (11) and the left array blocks (10) are positioned in the transition layer (2).
2. Device according to claim 1, characterized in that the substrate (1) is of sapphire or silicon carbide or silicon or graphene material.
3. The device of claim 1, wherein:
the thickness a of the barrier layer (3) is 3 nm-100 nm;
the thickness b of the passivation layer (4) is 5 nm-1000 nm;
the heights c of the M right array blocks (11), the N left array blocks (10) and the groove anode (12) are the same, and c is larger than a + b.
4. Device according to claim 1, characterized in that the N left array blocks (10) and the M right array blocks (11) are distributed staggered.
5. The device of claim 1, wherein:
the minimum distance d between the left array block (10) and the right array block (11) is greater than 0;
the distance e between the right array block (11) and the groove anode (12) is larger than 0.
6. The device of claim 1, wherein:
the left array block (10) consists of N metal cuboid blocks at equal intervals, the interval f is larger than 0, and N is larger than or equal to 1;
the right array block (11) is composed of M metal cuboid blocks at equal intervals, the interval g of the metal cuboid blocks is greater than 0, and M is greater than or equal to 2.
7. A manufacturing method of a distributed groove electrode power device is characterized by comprising the following steps:
A) epitaxial growth of GaN semiconductor material on a substrate (1) to form a transition layer (2);
B) a GaN-based wide bandgap semiconductor material is extended on the transition layer (2) to form a barrier layer (3);
C) depositing an insulator on the barrier layer (3) to form a passivation layer (4);
D) manufacturing a mask on the passivation layer (4) for the first time, etching the left side of the passivation layer (4) by using the mask until the upper surface of the barrier layer (3) is etched to form a cathode groove (5);
E) manufacturing masks on the passivation layer (4) and the cathode slot (5) for the second time, depositing metal above the cathode slot (5) and the passivation layer (4) by using the masks, and performing rapid thermal annealing to form a cathode (6);
F) a mask is manufactured on the passivation layer (4) and the cathode (6) for the third time, etching is carried out on the right side of the passivation layer (4) by using the mask until the etching is below the lower surface of the barrier layer (3), and N left array block grooves (7), M right array block grooves (8) and anode grooves (9) are formed;
G) and manufacturing a mask for the fourth time on the passivation layer (4), the cathode (6), the left array block groove (7), the right array block groove (8) and the anode groove (9), and depositing metal above the left array block groove (7), the right array block groove (8) and the anode groove (9) by using the mask to form N left array blocks (10), M right array blocks (11), a groove anode (12) and interconnection metal (13) to finish the manufacturing of the whole device.
8. The method of claim 7, wherein: the epitaxial technique used in the steps A) and B) comprises the following steps: chemical vapor deposition methods, hydride vapor phase epitaxy methods, molecular beam epitaxy methods.
9. The method of claim 7, wherein: the metal deposition process used in the steps E) and G) comprises the following steps: electron beam evaporation process, sputtering process.
10. The method of claim 7, wherein: the process conditions of the rapid thermal annealing used in the step E) are as follows: the temperature is set to 800-1000 ℃, and the time is set to 25-40 s.
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