CN114913801A - Display panel driving method and display device - Google Patents

Abstract

Embodiments of the present invention provide a driving method and a display device for a display panel, which can improve the screen flicker phenomenon during power up and down. The display panel includes a pixel circuit, and the pixel circuit includes a driving transistor and a data writing transistor, wherein the gate of the data writing transistor is electrically connected to the first scan signal line, the first electrode of the data writing transistor is electrically connected to the data line, and the data writing transistor is electrically connected to the data line. The second pole of the writing transistor is electrically connected to the driving transistor, and the first scanning signal line is used to provide the gate of the data writing transistor with a first enabling voltage and a first non-enabling voltage; the driving process of the display panel includes the first stage and display stage, the first stage is located before and/or after the display stage; the driving method of the display panel includes: during at least part of the time period of the first stage, the display driving chip provides the data line with a voltage less than the first disable voltage Voltage.

Description

Display panel driving method and display device

【Technical field】

The present invention relates to the field of display technology, and in particular, to a driving method of a display panel and a display device.

【Background technique】

With the continuous development of display technology, users have higher and higher requirements on the performance of display devices in all aspects. However, at present, due to the unreasonable design of the power-on and power-off sequence, the display device has occasional power-on and off-screen flashing. Although the screen flashing phenomenon is short-lived, it can still be seen by the user, which greatly affects the user's experience. .

[Content of the invention]

In view of this, embodiments of the present invention provide a method for driving a display panel and a display device, so as to effectively improve the screen flicker phenomenon during power-on and power-off of the display device.

In one aspect, an embodiment of the present invention provides a method for driving a display panel. The display panel includes a pixel circuit, and the pixel circuit includes a driving transistor and a data writing transistor, wherein a gate of the data writing transistor is connected to a gate of the data writing transistor. The first scan signal line is electrically connected, the first pole of the data writing transistor is electrically connected to the data line, the second pole of the data writing transistor is electrically connected to the driving transistor, and the first scan signal line is used for providing a first enable voltage and a first disable voltage to the gate of the data writing transistor;

The driving process of the display panel includes a first stage and a display stage, and the first stage is located before and/or after the display stage;

The driving method includes: during at least part of the time period of the first stage, a display driving chip provides a voltage lower than the first disable voltage to the data line.

On the other hand, an embodiment of the present invention provides a display device, including:

A display panel includes a pixel circuit, the pixel circuit includes a driving transistor and a data writing transistor, wherein a gate of the data writing transistor is electrically connected to a first scan signal line, and a first electrode of the data writing transistor is electrically connected is electrically connected to a data line, the second electrode of the data writing transistor is electrically connected to the driving transistor, and the first scan signal line is used to provide a first enable voltage and a gate of the data writing transistor the first non-enable voltage;

A display driver chip, electrically connected to the data line, for providing a voltage lower than the first disable voltage to the data line in a first stage, and providing a data voltage to the data line in a display stage, the first stage before and/or after the display stage

A technical scheme in the above-mentioned technical scheme has the following beneficial effects:

During the research process, the inventor found that the leakage of electricity from the data line to the light-emitting element is one of the main factors that cause the screen to flash up and down. In the first stage, that is, in the power-on and power-off stage, the first scan signal line performs normal line-by-line refresh on the pixel circuits from the first row to the last row. When the pixel circuit is not refreshed by the first scan signal line, the pixel circuits in the pixel circuit The gate of the data writing transistor receives the first disabling voltage. In the embodiment of the present invention, by supplying a voltage lower than the first disabling voltage to the data line in at least part of the time period of the first stage, the gate of the data writing transistor can be The gate-source voltage Vgs1 (Vgs1=V _GH -V _Data ) is greater than 0, so that the gate-source voltage Vgs1 is much larger than the threshold voltage of the data writing transistor. At this time, the data writing transistor can be controlled to be in a completely off state, effectively The connection path between the data line and the light-emitting element is cut off to prevent the voltage on the data line from leaking to the light-emitting element. Since the time that the pixel circuit is not refreshed by the first scanning signal line is much longer than the time that the pixel circuit is refreshed by the first scanning signal line within one frame, the embodiment of the present invention can effectively prevent the light-emitting element from emitting abnormally during the power-on and power-off process, and further Effectively improve the screen splash phenomenon during power-on and power-off.

【Description of drawings】

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

FIG. 1 is a schematic structural diagram of a display device provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

3 is a timing diagram corresponding to a pixel circuit provided by an embodiment of the present invention;

4 is a timing diagram of a display panel provided in an embodiment of the present invention in a first stage and a display stage;

FIG. 5 is another timing diagram of the display panel in the first stage and the display stage provided by an embodiment of the present invention;

6 is another timing diagram of the display panel in the first stage and the display stage provided by an embodiment of the present invention;

FIG. 7 is another timing diagram of the display panel in the first stage and the display stage provided by an embodiment of the present invention;

FIG. 8 is another timing diagram of the display panel in the first stage and the display stage provided by an embodiment of the present invention;

FIG. 9 is another timing diagram of the display panel in the first stage and the display stage provided by an embodiment of the present invention;

10 is another timing diagram of the display panel in the first stage and the display stage provided by an embodiment of the present invention;

11 is a schematic diagram of a circuit structure of a first transmit shift circuit provided by an embodiment of the present invention;

FIG. 12 is another timing diagram of the display panel in the first stage and the display stage provided by an embodiment of the present invention;

FIG. 13 is another timing diagram of the display panel provided in the embodiment of the present invention in the first stage and the display stage;

FIG. 14 is another timing diagram of the display panel in the first stage and the display stage provided by the embodiment of the present invention;

FIG. 15 is another schematic structural diagram of a display device provided by an embodiment of the present invention;

FIG. 16 is another schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

FIG. 17 is another timing diagram corresponding to the pixel circuit provided by the embodiment of the present invention;

FIG. 18 is another timing diagram of the display panel provided in the embodiment of the present invention in the first stage and the display stage;

FIG. 19 is another schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

FIG. 20 is another timing diagram corresponding to the pixel circuit provided by the embodiment of the present invention.

【Detailed ways】

In order to better understand the technical solutions of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. As used in the embodiments of the present invention and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.

It should be understood that the term "and/or" used in this document is only an association relationship to describe the associated objects, indicating that there may be three kinds of relationships, for example, A and/or B, which may indicate that A exists alone, and A and B exist at the same time. B, there are three cases of B alone. In addition, the character "/" in this document generally indicates that the related objects are an "or" relationship.

An embodiment of the present invention provides a driving method for a display panel, and the driving method can be applied to the display device shown in FIG. 1 .

As shown in FIG. 1 , FIG. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention. The display device includes a display panel 100 and a display driver chip 200 , wherein the display panel 100 includes an electrically connected pixel circuit 1 and a light-emitting device. element 2.

As shown in FIG. 2 and FIG. 3 , FIG. 2 is a schematic structural diagram of a pixel circuit 1 provided by an embodiment of the present invention, and FIG. 3 is a timing diagram corresponding to the pixel circuit 1 provided by an embodiment of the present invention. 1 includes a driving transistor M0 and a data writing transistor M1, wherein the gate of the data writing transistor M1 is electrically connected to the first scan signal line Scan1, the first pole of the data writing transistor M1 is electrically connected to the data line Data, and the data writing transistor M1 is electrically connected to the data line Data. The second pole of the input transistor M1 is electrically connected to the driving transistor M0, and specifically may be electrically connected to the first pole of the driving transistor M0.

The first scan signal line Scan1 is used to provide the first enable voltage V _GL and the first disable voltage V _GH to the gate of the data writing transistor M1 . When the first scan signal line Scan1 provides the first enable voltage, the data writing transistor M1 is turned on, and the data voltage V _Data on the data line Data is written into the first pole of the driving transistor M0. When the first scan signal line Scan1 When the first disable voltage is provided, the data writing transistor M1 is turned off, and the data voltage V _Data cannot be written into the driving transistor M0.

As shown in FIG. 4, FIG. 4 is a timing diagram of the display panel 100 in the first stage T1 and the display stage T2 according to the embodiment of the present invention. The driving process of the display panel 100 includes the first stage T1 and the display stage T2. A stage T1 precedes and/or follows the display stage T2. The embodiments of the present invention illustrate that the driving process of the display panel 100 includes two first stages T1 as an example. One of the first stages T1 is located before the display stage T2, and the first stage T1 is the upper stage before the display panel 100 enters normal display. The power-on stage can be, for example, a power-on stage/wake-up stage, and another first stage T1 is located after the display stage T2, and the first stage T1 is a power-off stage after the display panel 100 finishes normal display, for example, can be a shutdown stage/sleep stage .

Based on this, with reference to FIGS. 1 to 3 , the driving method provided by the embodiment of the present invention includes: in at least part of the time period of the first stage T1 , the display driving chip 200 provides the data line Data with a voltage V less than the first disabling voltage V _GH voltage.

In the pixel circuit 1, the driving transistor M0 and the data writing transistor M1 are both P-type transistors, and the threshold voltage of the P-type transistor is less than 0, for example, the threshold voltage may be between -1V and -2V.

During the research process, the inventor found that the leakage of electricity from the data line Data to the light-emitting element 2 is one of the main factors causing the screen to flash up and down. In the first stage T1, the first scan signal line Scan1 performs normal line-by-line refresh for the pixel circuits 1 in the first row to the last row. When the pixel circuit 1 is not refreshed by the first scan signal line Scan1, the data in the pixel circuit 1 The gate of the write transistor M1 receives the first disable voltage V _GH . In the embodiment of the present invention, by providing a voltage lower than the first disable voltage V _GH to the data line Data during at least a part of the time period of the first stage T1, it can be The gate-source voltage Vgs1 of the data writing transistor M1 ( _Vgs1 =VGH -V _Data ) is greater than 0, so that the gate-source voltage Vgs1 is much larger than the threshold voltage of the data writing transistor M1, and the data writing can be controlled at this time The transistor M1 is in a completely off state, effectively cutting off the connection path between the data line Data and the light-emitting element 2 , and preventing the voltage on the data line Data from leaking to the light-emitting element 2 . Since the time when the pixel circuit 1 is not refreshed by the first scan signal line Scan1 is much longer than the time when the pixel circuit 1 is refreshed by the first scan signal line Scan1 within one frame, the embodiment of the present invention can effectively prevent the light-emitting element 2 from being powered on and off It emits light abnormally, thereby effectively improving the screen splash phenomenon during power-on and power-off.

In addition, it should be noted that, referring to FIG. 2 again, the pixel circuit 1 further includes a second light-emitting control transistor M2, which is also a P-type transistor. The gate of the second light-emitting control transistor M2 is electrically connected to the light-emitting control signal line Emit, the first electrode of the second light-emitting control transistor M2 is electrically connected to the driving transistor M0, and specifically to the second electrode of the driving transistor M0, and the second light-emitting control transistor M2 is electrically connected to the second electrode of the driving transistor M0. The second electrode of the control transistor M2 is electrically connected to the light-emitting element 2 . Referring to FIG. 3 , the light-emitting control signal line Emit is used to provide the light-emitting enable voltage V _GL ′ and the light-emitting non-enable voltage V _GH ′ to the gate of the second light-emitting control transistor M2 , wherein the light-emitting enable voltage V _GL ′ may be the same as the The first enable voltage V _GL is equal, and the light emission disable voltage V _GH ′ may be equal to the first disable voltage V _GH .

When the light-emitting control signal line Emit provides the light-emitting enable voltage V _GL ', the second light-emitting control transistor M2 is turned on, the driving current flows to the light-emitting element 2, and the light-emitting element 2 is controlled to emit light. When the light-emitting control signal line Emit provides the light-emitting non-enable When the voltage V _GH ′ is reached, the second light-emitting control transistor M2 is turned off, and the driving current cannot flow to the light-emitting element 2 , so that the light-emitting element 2 does not emit light.

In the first stage T1, when the light-emitting control signal line Emit provides the light-emitting disable voltage V _GH ′ to the pixel circuit 1 , if the potential of the first electrode of the second light-emitting control transistor M2 is too high, the second light-emitting control transistor M2 will cause the second light-emitting control The transistor M2 is in a poor off state, and at this time, the light-emitting element 2 may still emit light abnormally. In the embodiment of the present invention, a voltage lower than the first disable voltage _VGH is provided to the data line Data in the first stage T1. When the data writing transistor M1 is refreshed by the first scan signal line Scan1, the gate of the data writing transistor M1 is refreshed. When the data writing transistor M1 is turned on by receiving the first enable voltage V _GL , the voltage transmitted on the data line Data will be transmitted to the first pole of the second light-emitting control transistor M2, so that the second light-emitting control transistor M2 is turned on. One pole receives a voltage lower than the light-emitting disable voltage V _GH ' (the first disable voltage V _GH ), at this time, the gate-source voltage Vgs2 of the second light-emitting control transistor M2 (Vgs2=V _GH '-V _Data ) is greater than 0, which is far greater than the threshold voltage of the second light-emitting control transistor M2, thereby further improving the off-state reliability of the second light-emitting control transistor M2, preventing leakage current from flowing to the light-emitting element 2, and avoiding the light-emitting element 2 to a greater extent. Extraordinarily glowing.

In order to improve the screen splash phenomenon during power-on and power-off to a greater extent, in the embodiment of the present invention, in the entire first stage T1, the display driver chip 200 provides the data line Data with a voltage less than the first disable voltage V _GH . Voltage.

In a feasible implementation manner, referring to FIG. 1 and FIG. 2 again, the display device further includes a power driver chip 300 . The pixel circuit 1 further includes a first light-emitting control transistor M3, and the first light-emitting control transistor M3 is a P-type transistor. The gate of the first light-emitting control transistor M3 is electrically connected to the light-emitting control signal line Emit, the first electrode of the first light-emitting control transistor M3 is electrically connected to the power supply signal line PVDD, and the second electrode of the first light-emitting control transistor M3 is electrically connected to the driving transistor M0 Electrical connection, specifically, can be electrically connected to the first electrode of the driving transistor M0. The light-emitting control signal line Emit is used to provide the light-emitting enable voltage V _GL ' and the light-emitting non-enable voltage V _GH ' to the gate of the first light-emitting control transistor M3, wherein the light-emitting enable voltage V _GL ' may be the same as the first enable voltage V GL ' The voltages V _GL are equal, and the light-emitting disable voltage V _GH ′ may be equal to the first disable voltage V _GH .

When the light-emitting control signal line Emit provides the light-emitting enable voltage V _GL ′, the first light-emitting control transistor M3 is turned on, and the power signal provided by the power signal line PVDD is written into the first pole of the driving transistor M0. When the light-emitting control signal line Emit When the light-emitting non-enable voltage V _GH ′ is provided, the first light-emitting control transistor M3 is turned off, and the power signal cannot be written to the first electrode of the driving transistor M0 .

Based on this, referring to FIG. 4 again, the first stage T1 includes a non-power supply period t1 and a power supply period t2, and the power supply period t2 is located between the non-power supply period t1 and the display stage T2. The driving method further includes: in the non-power supply period t1, the power driving chip 300 does not provide the power supply voltage to the power supply signal line PVDD, and in the power supply period t2, the power supply driving chip 300 provides the power supply voltage V _{PVDD to the power supply signal line PVDD} .

Taking the first stage T1 as the power-on stage as an example, when the display panel 100 is powered on, the display panel 100 first enters the non-power supply period t1. The interval between stages T2 is a certain period of time, so the screen splash phenomenon is more easily detected by human eyes. For example, in order to reduce power consumption when the display panel is turned off, basically all signals belong to the floating state. Especially the data line. Therefore, some charges may be accumulated when the screen is closed, resulting in different potentials of each data line. If the power supply stage t2 is entered from the beginning, and the power supply signal line PVDD provides a corresponding potential, the panel has the basic conditions for emitting light. The charge accumulated on the data line will greatly increase the probability of screen splash. Entering the non-power supply stage t1 first can reduce the risk of screen splashing. Therefore, by causing the power driver chip 300 not to supply power to the power supply signal line PVDD during the non-power supply period t1, the pixel circuit 1 cannot receive the power supply voltage V _PVDD , thereby preventing the light-emitting element 2 from emitting abnormally during the non-power supply period t1 to a greater extent.

In addition, it should be noted that, in the embodiment of the present invention, the data writing transistor M1 can be controlled to be turned off when the data writing transistor M1 is not refreshed, and the second light emitting control transistor M1 can be controlled to be turned off when the data writing transistor M1 is refreshed, so as to The connection path between the data writing transistor M1 and the light emitting element 2 is cut off, so even if the power driver chip 300 normally supplies power to the power signal line PVDD during the power supply period t2, it can still prevent the light emitting element 2 from abnormally emitting light during the power supply period t2.

In a feasible implementation manner, as shown in FIG. 5 , FIG. 5 is another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 according to the embodiment of the present invention. In the first stage T1, the display The process of the driving chip 200 providing the voltage to the data line Data includes: in the power supply period t2, the display driving chip 200 provides the black state voltage V _GMP to the data line Data. It should be noted that the black state voltage V _GMP is smaller than the first disable voltage V _GH , and the black state voltage may specifically be a voltage of 0 gray scale.

In the embodiment of the present invention, by supplying the black state voltage V _GMP to the data line Data during the power supply period t2, even if the data writing transistor M1 is refreshed by the first scan signal line Scan1, the black state voltage V _GMP is written into the driving transistor M0, and the light emitting element 2 It will only appear in the black state under the action of the black state voltage V _GMP , and will not light up.

In a feasible implementation manner, referring to FIG. 5 again, in the first stage T1, the process of supplying voltage to the data line Data by the display driver chip 200 further includes: in the non-power supply period t1, the display driver chip 200 provides a voltage to the data line Data A constant voltage V ₁ , the constant voltage V ₁ is smaller than the first non-enable voltage V _GH , so that while effectively controlling the working state of the data writing transistor M1, it can also reduce the voltage jump on the data line Data, thereby reducing power consumption.

Further, the voltage difference between the constant voltage V1 and the _first non-enable voltage VGH is ΔV, in order to ensure that the gate-source voltage _Vgs1 of the data writing transistor M1 is greater than the threshold voltage of the data writing transistor M1 to a greater extent , can make △V≥1V.

In a feasible implementation manner, with reference to FIG. 5 , as shown in FIG. 6 , FIG. 6 is another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided by the embodiment of the present invention. In stage T1, the process of supplying the voltage to the data line Data by the display driving chip 200 further includes: in the non-power supply period t1, the display driving chip 200 provides the data line Data with a voltage less than or equal to the black state voltage V _GMP .

In the non-power supply period t1, a voltage less than or equal to the black state voltage V _GMP is provided to the data line Data, which can prevent the data voltage from being too high in this period and save power consumption to a certain extent. In particular, referring to FIG. 6 , when the constant voltage V ₁ is equal to the black state voltage V _GMP , that is, the display driving chip 200 provides the black state voltage V _GMP to the data line Data during both the power supply period t2 and the non-power supply period t1, and the data line Data There is no voltage jump in the whole first stage T1, and the power consumption is lower.

In a feasible implementation manner, as shown in FIG. 7 , FIG. 7 is another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 according to the embodiment of the present invention, and the non-power supply period t1 includes x sub-periods During the period t11, the voltage supplied to the data line Data in the sub-period t11_i is lower than the voltage supplied to the data line Data in the sub-period t11_i+1, x is a positive integer greater than or equal to 2, 1≤i≤x-1. For clear illustration, the i-th sub-period is denoted by reference numeral t11_i in FIG. 6 .

In this arrangement, in the non-power supply period t1 during x sub-periods t11, the voltage provided by the display driver chip 200 to the data line Data is gradually increased until it is increased to the same level as the black state voltage V in the xth sub-period t11_x _GMP is close to or equal to the black-state voltage V _GMP , which can prevent the screen from being impacted by excessive voltage jumps on the data line Data when the non-power supply period t1 enters the power supply period t2 .

其中，k为大于或等于1的正整数，f1为第一扫描信号线Scan1在显示阶段T2所输出的第一扫描信号的频率。其中，

为一帧时间。Further, the duration of the sub-period t11 is t0,

Wherein, k is a positive integer greater than or equal to 1, and f1 is the frequency of the first scan signal output by the first scan signal line Scan1 in the display stage T2. in,

for one frame time.

In this way, the duration of each sub-period t11 is an integer multiple of one frame time, so that in one frame time, the first scan signal line Scan1 performs one round of refreshes on the first row of sub-pixel circuits 1 to the last row of pixel circuits 1 , the data voltage V _Data written by the first row of sub-pixel circuits 1 to the last row of pixel circuits 1 only corresponds to a certain constant data voltage V _Data provided to the data line Data in one sub-period t11, that is, multiple rows of pixel circuits. The data voltage V _Data written in 1 is the same, so within a frame time, the data voltage V _Data has the same degree of regulation on the data writing transistor M1 in the multi-row pixel circuit 1, which improves the ability of different pixel circuits in the same frame time. 1 for regulatory uniformity.

Further, the voltage supplied to the data line Data in the first sub-period t11_1 is less than 2.5V, or the ground voltage is supplied to the data line Data in the first sub-period t11_1.

In the above setting method, by providing a voltage less than 2.5V to the data line Data in the first sub-period t11_1 or directly providing a ground voltage, the voltage provided to the data line Data in the first sub-period t11_1 can be made smaller, That is, there is a large voltage difference between the voltage supplied to the data line Data in the first sub-period t11_1 and the black state voltage V _GMP . If the non-power supply period t1 includes a larger number of sub-periods t11, when the data voltage V _Data is gradually increased in the subsequent other sub-periods t11, the voltage increase space is larger, so that the data voltage V corresponding to the other subsequent sub-periods t11 is improved. _Data is designed to be more flexible.

In a feasible implementation manner, the display panel 100 has at least two display modes, for example, the display panel 100 has a normal mode, an Always on Display (AOD) mode, and a High Brightness Mode (HBM) model. When the display panel 100 performs the always-on display mode in the display stage T2, the display panel 100 usually only displays part of the content, for example, only time information, etc., so the display panel 100 is usually displayed at a lower brightness in this display mode, and when the display panel 100 is displayed When the highlight mode is executed in the display stage T2 , in order to optimize the display performance, the display panel 100 is usually displayed with a higher brightness.

Since the brightness levels corresponding to different display modes are different, when the display panel 100 executes different display modes in the display stage T2, the black state voltage V _GMP , the power supply voltage V _PVDD and the first disable corresponding to the different display modes The voltage _VGH can also be different. For example, compared with the normal mode, the brightness level in the highlight mode is higher, so when the display panel 100 performs the highlight mode in the display stage T2, the corresponding black state voltage V _GMP is higher.

As shown in FIG. 8 , FIG. 8 is another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 according to the embodiment of the present invention. When the display panel 100 performs different display modes in the display stage T2, the first The first disabling voltages _{VGH corresponding to the stage T1 are equal, the power supply voltages V PVDD are} equal, and the black state voltages V _GMP are also equal.

Taking the first stage T1 as the power-on stage as an example, no matter what display mode the display panel 100 executes after power-on and enters the display stage T2, in the first stage T1, the data voltage V provided to the data line Data is set in the first stage T1. In the case of _Data , the data voltage V _Data is set based on the same first disable voltage V _GH . For example, the first disable voltage V _GH is when the display panel 100 executes the normal mode in the display stage T2 The corresponding first disable voltage V _GH1 . The voltages provided by the power driver chip 300 to the power signal line PVDD are also the same power supply voltage V _PVDD . For example, the power supply voltage V _PVDD is the power supply voltage V _PVDD1 corresponding to the display panel 100 performing the normal mode in the display stage T2 . The black state voltage V _GMP provided by the display driver chip 200 to the data line Data during the power supply period t2 is also the same voltage. For example, the black state voltage V _GMP is the black state corresponding to the normal mode of the display panel 100 in the display period T2 voltage V _GMP1 .

In this way, no matter what display mode the display panel 100 performs in the display stage T2, the same type of voltage in the first stage T1 follows the same voltage setting, and the setting of each voltage in the first stage T1 is simpler.

Alternatively, in another feasible implementation manner, when the display panel 100 performs different display modes in the display stage T2, different voltage settings may also be performed for the same type of voltage in the first stage T1.

The first stage T1 is located before the display stage T2, and the display mode executed by the display panel 100 after the first stage T1 ends is the first display mode, or, the first stage T1 is located after the display stage T2, and the display panel 100 enters the first display mode. The display mode performed before stage T1 is the first display mode.

It should be noted that, in the display stage T2, the display panel 100 can switch the display mode executed by the display panel 100 according to the user's usage requirements. The above-mentioned first display mode refers to the display mode that the display panel 100 needs to execute at the beginning when the display panel 100 first enters the display stage T2, or the display mode that the display panel 100 executes last when the display panel 100 is about to end the display stage T2. . For example, taking the first stage T1 as the power-on stage as an example, when the display panel 100 starts to perform normal screen display after power-on, the display panel 100 initially executes the normal mode in the display stage T2, and switches to the highlight mode after a period of time. At this time, the first display mode refers to the normal mode.

As shown in FIG. 9 , FIG. 9 is another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided by the embodiment of the present invention. When the first display mode is the normal mode, the first stage T1 corresponds to The first disable voltage is V _GH1 , the power supply voltage is V _PVDD1 , and the black state voltage is V _GMP1 . The first disabling voltage V _GH1 , the power supply voltage V _PVDD1 and the black state voltage V _GMP1 are respectively the first disabling voltage, the power supply voltage and the black state voltage corresponding to when the display panel 100 performs the normal mode in the display stage T2 .

When the first display mode is the highlight mode, the first disabling voltage corresponding to the first stage T1 is V _GH2 , the power supply voltage is V _PVDD2 , and the black state voltage is V _GMP2 . The first disabling voltage V _GH2 , the power supply voltage V _PVDD2 , and the black state voltage V _GMP2 are respectively the first disabling voltage, power supply voltage and black state voltage. Since the highlight mode prioritizes performance requirements, the first disabling voltage, the power supply voltage, and the black-state voltage can all be adjusted upward in the highlight mode compared to the normal mode. Referring to FIG. 9 , when the first display mode is the highlight mode, the first disabling voltage V _GH2 , the power supply voltage V _PVDD2 and the black state voltage V _GMP2 corresponding to the first stage T1 satisfy: V _GH2 >V _GH1 , V _PVDD2 >V _PVDD1 , V _GMP2 >V _GMP1 , V _GH2 -V _{GH1 ≥V GMP2} -V _{GMP1 ≥V PVDD2} -V _PVDD1 .

When the first display mode is the always-display mode, the first disabling voltage corresponding to the first stage T1 is V _GH3 , the power supply voltage is V _PVDD3 , and the black state voltage is V _GMP3 . The first disabling voltage V _GH3 , the power supply voltage V _PVDD3 , and the black state voltage V _GMP3 are respectively the first disabling voltage, the power supply voltage and the black state voltage corresponding to the display panel 100 when the display panel 100 performs the normal display mode in the display stage T2 . Since the brightness level corresponding to the normal display mode is not as high as the brightness level corresponding to the highlight mode, in order to save power consumption, the upward adjustment degree of each voltage in the normal display mode can be smaller than that in the highlight mode. 9. When the first display mode is the always-display mode, the first disabling voltage V _GH3 , the power supply voltage V _PVDD3 and the black state voltage V _GMP3 corresponding to the first stage T1 satisfy: V _GH1 <V _GH3 <V _GH2 , V _PVDD1 <V _PVDD3 <V _PVDD2 , V _GMP1 <V _GMP3 <V _GMP2 , and V _GH3 -V _{GH1 ≥V GMP3} -V _{GMP1 ≥V PVDD3} -V _PVDD1 .

Alternatively, in order to reduce power consumption to a greater degree, as shown in FIG. 10 , FIG. 10 is another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 according to the embodiment of the present invention, when the first display mode In the normally display mode, the first disabling voltage V _GH3 , the power supply voltage V _PVDD3 and the black state voltage V _GMP3 corresponding to the first stage T1 can also satisfy: V _GH3 <V _GH1 , V _PVDD3 <V _PVDD1 , V _GMP3 < V _GMP1 , and V _GH1 -V _{GH3 ≤V GMP1} -V _{GMP3 ≤V PVDD1} -V _PVDD3 .

供电时段t2的时长为t2，

其中，f1为第一扫描信号线Scan1在显示阶段T2所输出的第一扫描信号的频率。In a feasible implementation manner, the duration of the non-power supply period t1 is t1,

The duration of the power supply period t2 is t2,

Wherein, f1 is the frequency of the first scan signal output by the first scan signal line Scan1 in the display stage T2.

By setting the durations of the non-power supply period t1 and the power supply period t2 to be at least one frame, respectively, in the non-power supply period t1 and the power supply period t2, the first scan signal line Scan1 is capable of providing pixel circuits from the first row 1 to the last row. The pixel circuit 1 of the pixel circuit 1 performs at least one complete refresh, so that the voltage transmitted on the data line Data can effectively control all the pixel circuits 1, so as to ensure that the screen splash phenomenon in different areas of the display area can be effectively improved. By further setting the durations of the non-power supply period t1 and the power supply period t2 to at most three frames, it is possible to prevent the power-on and power-off process from being too long and affecting the user's use experience.

In a feasible implementation manner, the first scan signal output by the first scan signal line Scan1 in the display stage T2 has multiple frequencies, and f1 is the maximum value of the frequency of the first scan signal. It can be understood that, the higher the frequency of the first scan signal, the shorter the corresponding one frame time. When the display panel 100 performs frequency conversion driving in the display stage T2, by setting f1 to be the value of the first scan signal. The maximum value of the frequency can shorten the time of the power-on and power-off process and optimize the user experience.

供电时段t2的时长为t2，

m和n分别为大于或等于0的整数。其中，f1为第一扫描信号线Scan1在显示阶段T2所输出的第一扫描信号的频率，f2为发光控制信号线Emit在显示阶段T2所输出的发光控制信号的频率。In a feasible implementation manner, the duration of the non-power supply period t1 is t1,

The duration of the power supply period t2 is t2,

m and n are integers greater than or equal to 0, respectively. Wherein, f1 is the frequency of the first scan signal output by the first scan signal line Scan1 in the display stage T2, and f2 is the frequency of the light emission control signal output by the light emission control signal line Emit in the display stage T2.

为缩短上下电时间，非供电时段t1和供电时段t2在分别满足大于一帧的前提下，可以不将其设定为一帧的整数倍，只要满足

的整数倍也可以。When the display panel 100 is driven at a low frequency, in order to improve flickering, the refresh frequency of the lighting control signal may be greater than the refresh frequency of the first scanning signal. For example, referring to FIG. 3 , the frequency of the first scanning signal is 30 Hz, and the frequency of the lighting control signal may be is 60Hz, that is

In order to shorten the power-on and power-off time, the non-power supply period t1 and the power supply period t2 may not be set to an integer multiple of one frame, provided that they meet the requirements of more than one frame respectively, as long as the

Integer multiples are also possible.

In a feasible implementation manner, the durations of the non-power supply period t1 and the power supply period t2 may be set to be unequal.

Since the power supply period t2 needs to be powered on the power supply voltage, there is a long time delay. In order to ensure that the voltage is switched to be stable, the power supply period t2 can be made to have a longer duration, that is, the duration of the non-power supply period t1 is shorter than that of the power supply period t2. Exemplarily, the duration of the non-power supply period t1 is 2 frames, and the duration of the power supply period t2 is 3 frames.

In a feasible implementation manner, referring to FIG. 1 and FIG. 2 again, the pixel circuit 1 includes a second light-emitting control transistor M2, the gate of the second light-emitting control transistor M2 is electrically connected to the light-emitting control signal line Emit, and the second light-emitting control transistor M2 is electrically connected to the second light-emitting control transistor M2. The first pole of the transistor M2 is electrically connected to the driving transistor M0, the second pole of the second light-emitting control transistor M2 is electrically connected to the light-emitting element 2, and the light-emitting control signal line Emit is used to provide a light-emitting enable to the gate of the second light-emitting control transistor M2. The enable voltage V _GL ' and the light emission disable voltage V _GH '.

The display panel 100 further includes a plurality of emission shift circuits 3 arranged in cascade. The emission shift circuit 3 is electrically connected to the light emission control signal line Emit. The emission shift circuit 3 includes a first emission shift circuit 4. The circuit 4 is also electrically connected to the transmission frame start signal line STV_E.

As shown in FIG. 11 , FIG. 11 is a schematic diagram of a circuit structure of a first emission shift circuit 4 provided by an embodiment of the present invention. The first emission shift circuit 4 further includes a first control transistor M1 ′ and a first output transistor M2'. The first control transistor M1' is electrically connected between the emission frame start signal line STV_E and the gate of the first output transistor M2', the first pole of the first output transistor M2' is electrically connected to the first fixed potential signal line VGL, the first The second electrode of an output transistor M2' is electrically connected to the light-emitting control signal line Emit, wherein the first fixed-potential signal line VGL is used to provide the light-emitting enable voltage V _GL '.

As shown in FIG. 12, FIG. 12 is another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 according to the embodiment of the present invention. The driving method further includes: in the first stage T1, the display driving chip 200 sends the The emission frame start signal line _{STV_E} provides a disabling voltage of the first output transistor M2', which may be equal to the first disabling voltage VGH.

It should be noted that, in conjunction with FIG. 11 and FIG. 12 , the transmit shift register is also connected to the first transmit clock signal line CK1_E and the second transmit clock signal line CK2_E respectively. In the first stage T1, the first transmit clock signal line CK1_E and the first transmit clock signal line CK1_E 2. The transmitting clock signal line CK2_E can normally supply the pulse signal in the first stage T1.

In the circuit structure based on the current transmission shift register, when the non-enable voltage of the first output transistor M2' is supplied to the transmission frame start signal line STV_E, the non-enable voltage is transmitted through the turned-on first control transistor M1' To the first output transistor M2 ′, the first output transistor M2 ′ is controlled to be turned off, so that the first emission shift circuit 4 cannot output the light-emitting enable voltage V _GL ′ and cannot realize the sequential downward shift. In this way, it can be avoided that the emission shift circuit 3 transmits the emission enable voltage V _GL ′ to the emission control signal line, and the second emission control transistor M2 in the pixel circuit 1 is prevented from being turned on, thereby avoiding the leakage current of the data line Data. As for the light-emitting element 2, the problem of up and down the flashing screen is improved to a greater extent.

Further, referring to FIG. 11 again, the first emission shift circuit 4 includes a protection transistor M3', the gate of the protection transistor M3' is electrically connected to the control signal line RST, and the first pole of the protection transistor M3' is connected to the second fixed potential signal The line VGH is electrically connected, the second fixed potential signal line VGH is used to provide the disable voltage of the first output transistor M2', the second pole of the protection transistor M3' is electrically connected to the gate of the first output transistor M2', and the control signal The line RST is used to provide a second enable voltage V _GL1 and a second non-enable voltage V _GH1 to the gate of the protection transistor M3', the second enable voltage V _GL1 may be equal to the first enable voltage V _GL , the The second disable voltage V _GH1 may be equal to the first disable voltage V _GH .

Referring to FIG. 12 again, the driving method of the display panel 100 includes: in the first stage T1 , the display driving chip 200 provides the second disable voltage V _GH1 to the control signal line RST.

In the emission shift circuit 3, the protection transistor M3' is a transistor for preventing abnormal power-off. In the first stage T1, by supplying the second non-enable voltage V _GH1 to the control signal line RST, the protection transistor M3' is kept off, and the first stage T1 The high level provided by the two fixed potential signal lines VGH charges the parasitic capacitance in the protection transistor M3'. If an abnormal power failure occurs during the power supply process of the first stage T1, the protection transistor M3' can transmit the high level stored by itself to the gate of the first output transistor M2' to ensure that the first output transistor M2' is turned off and the first output transistor M2' is turned off. An emission shift circuit 4 cannot output the light-emitting enable voltage V _GL ′, thereby controlling the light-emitting element 2 to not emit light, and controlling the first emission shift circuit 4 to continue to shift downward.

In addition, it should be noted that the first emission shift circuit 4 may further include: the second control transistor M4' to the sixth control transistor M8', the second output transistor M9', the first capacitor C1, the second capacitor C2 and the first Three capacitors C3, the connection manner of the above structure is the same as that in the prior art, and will not be repeated here.

In another feasible implementation manner, as shown in FIG. 13 , FIG. 13 is another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided by the embodiment of the present invention. During the power supply period t2, the display panel 100 displays The driving chip 200 may also provide a clock signal to the emission frame start signal line STV_E, that is, control the light emission control signal line Emit to perform normal refresh of the pixel circuit 1 .

Since the embodiment of the present invention can cut off the connection path between the data line Data and the light-emitting element 2 in the first stage T1, even if the light-emitting control signal line Emit normally drives the pixel circuit 1 in the first stage T1, it is still effective. Improve the splash screen phenomenon.

In a feasible implementation manner, referring to FIG. 1 again, the display panel further includes a plurality of first scan shift circuits 5 arranged in cascade, and the first scan shift circuits 5 are respectively connected to the first scan clock signal lines CK1_S1, The first B scan clock signal line CK2_S1 is electrically connected to the first scan signal line Scan1. The first scan shift circuit 5 includes a first scan shift circuit 6 , and the first scan shift circuit 6 is also electrically connected to the first scan frame start signal line STV_S1 .

Based on this, as shown in FIG. 14 , FIG. 14 is another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided by the embodiment of the present invention, and the driving method further includes: in the first stage T1, display driving The chip 200 provides pulse signals to the first A scan clock signal line CK1_S1, the first B scan clock signal line CK2_S1 and the first scan frame start signal line STV_S1, respectively.

In the above setting method, the first scan shift circuit works normally in the first stage T1, so that the first scan signal line Scan1 normally refreshes the pixel circuit 1, but as mentioned above, based on the embodiment of the present invention, in the first The setting of the data voltage V _Data in the stage T1 can prevent the light-emitting element 2 from emitting abnormal light in the first stage T1 even if the first scanning signal line Scan1 refreshes the pixel circuit 1 normally.

In a possible setting manner, as shown in FIGS. 15 to 17 , FIG. 15 is another schematic structural diagram of a display device provided by an embodiment of the present invention, and FIG. 16 is a pixel circuit 1 provided by an embodiment of the present invention. 17 is another timing diagram corresponding to the pixel circuit 1 provided by the embodiment of the present invention. The pixel circuit 1 includes a control transistor M7, and the gate of the control transistor M7 is electrically connected to the second scan signal line Scan2. The first electrode of the control transistor M7 is electrically connected to the control signal line DVH, and the second electrode of the control transistor M7 is electrically connected to the driving transistor M0, specifically the first electrode of the driving transistor M0.

As shown in Fig. 15, the display panel 100 further includes a plurality of second scan shift circuits 7 arranged in cascade. The second scan shift circuits 7 are respectively connected with the second scan clock signal line CK1_S2 and the second scan clock signal line B. CK2_S2 is electrically connected to the second scan signal line Scan2. Wherein, the second scan shift circuit 7 includes a second A scan shift circuit 8, and the second A scan shift circuit 8 is also electrically connected to the second scan frame start signal line STV_S2.

As shown in FIG. 18 , FIG. 18 is another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided by the embodiment of the present invention. The driving method further includes: in the first stage T1, the display driving chip 200 respectively A pulse signal is supplied to the second A scan clock signal line CK1_S2, the second B scan clock signal line CK2_S2 and the second scan frame start signal line STV_S2.

The above-mentioned pixel circuit 1 includes a control transistor M7. With reference to FIG. 17, before the gate of the drive transistor M0 is reset, by controlling the control transistor M7 to be turned on, the bias voltage provided by the control signal line DVH can be written into the drive transistor M0. The first pole is to refresh the potential of the first pole of the driving transistor M0, so that the device characteristics of the driving transistor M0 are set to a certain initial state, and the influence of the data signal written in the previous frame on the device characteristics of the driving transistor M0 is eliminated. . After the data voltage V _Data is written to the driving transistor M0, the voltage of the first electrode of the driving transistor M0 will leak, especially under low-frequency driving, the leakage is more obvious, resulting in a higher potential of the first electrode of the driving transistor M0. At this time, by controlling the control transistor M7 to be turned on, and using the control transistor M7 to write a bias voltage to the first pole of the driving transistor M0, the bias state of the driving transistor M0 can be made the same as when the data voltage V _Data was just written. The paranoid state of the two is kept the same, so as to improve the stability of the working state of the driving transistor M0.

In addition, it should be noted that, referring to FIG. 2 and FIG. 16 , the pixel circuit 1 further includes a storage capacitor Cst, a first reset transistor M4 , a second reset transistor M5 and a threshold compensation transistor M6 . Wherein, in an implementation form, the first reset transistor M4, the second reset transistor M5 and the threshold compensation transistor M6 may all be P-type transistors.

The gate of the first reset transistor M4 is electrically connected to the third scan signal line Scan3, the first pole of the first reset transistor M4 is electrically connected to the reset signal line Vref, and the second pole of the first reset transistor M4 is electrically connected to the driving transistor M0 It is electrically connected, and is specifically electrically connected to the gate of the driving transistor M0. The first reset transistor M4 is used for writing the reset signal provided by the reset signal line Vref into the gate of the driving transistor M0 in response to the low level provided by the third scan signal line Scan3, so as to reset the gate of the driving transistor M0.

The gate of the second reset transistor M5 is electrically connected to the third scan signal line Scan3, the first pole of the second reset transistor M5 is electrically connected to the reset signal line Vref, and the second pole of the second reset transistor M5 is electrically connected to the anode of the light-emitting element 2 electrical connection. The second reset transistor M5 is used to write the reset signal provided by the reset signal line Vref into the anode of the light-emitting element 2 in response to the low level provided by the third scan signal line Scan3, so as to reset the anode of the light-emitting element 2.

The gate of the threshold compensation transistor M6 is electrically connected to the first scan signal line Scan1, the first pole of the threshold compensation transistor M6 is electrically connected to the second pole of the driving transistor M0, and the second pole of the threshold compensation transistor M6 is electrically connected to the gate of the driving transistor M0 pole electrical connection. The threshold compensation transistor M6 is used to perform threshold compensation on the driving transistor M0 in response to the low level (first enable voltage V _GL ) provided by the first scan signal line Scan1 .

Or, in another implementation manner, as shown in FIG. 19 and FIG. 20 , FIG. 19 is another schematic structural diagram of the pixel circuit 1 provided by the embodiment of the present invention, and FIG. 20 is the pixel provided by the embodiment of the present invention. Another timing diagram corresponding to circuit 1, the second reset transistor M5 is a P-type transistor, and in order to reduce the influence of leakage current on the gate potential stability of the driving transistor M0, the first reset transistor M4 and the threshold compensation transistor M6 are also It may be an indium gallium zinc oxide (IGZO) transistor, that is, the first reset transistor M4 and the threshold compensation transistor M6 are N-type transistors.

At this time, the gate of the first reset transistor M4 is electrically connected to the fourth scan signal line Scan4, the first pole of the first reset transistor M4 is electrically connected to the reset signal line Vref, and the second pole of the first reset transistor M4 is electrically connected to the driving transistor M0 is electrically connected, specifically, is electrically connected to the gate of the driving transistor M0. The first reset transistor M4 is used to write the reset signal provided by the reset signal line Vref into the gate of the driving transistor M0 in response to the high level provided by the fourth scan signal line Scan4, so as to reset the gate of the driving transistor M0.

The gate of the second reset transistor M5 is electrically connected to the second scan signal line Scan2, the first electrode of the second reset transistor M5 is electrically connected to the reset signal line Vref, and the second electrode of the second reset transistor M5 is electrically connected to the anode of the light-emitting element 2 electrical connection. The second reset transistor M5 is used to write the reset signal provided by the reset signal line Vref into the anode of the light-emitting element 2 in response to the low level provided by the second scan signal line Scan2 to reset the anode of the light-emitting element 2 . It should be noted that, since the second scan signal line Scan2 is set low twice within a frame time, the second reset transistor M5 can reset the anode of the light-emitting element 2 twice.

The gate of the threshold compensation transistor M6 is electrically connected to the fifth scan signal line Scan5, the first pole of the threshold compensation transistor M6 is electrically connected to the second pole of the driving transistor M0, and the second pole of the threshold compensation transistor M6 is electrically connected to the gate of the driving transistor M0 pole electrical connection. The threshold compensation transistor M6 is used for performing threshold compensation on the driving transistor M0 in response to the high level provided by the fifth scan signal line Scan5.

Based on the same inventive concept, an embodiment of the present invention further provides a display device. Referring to FIG. 1 and FIG. 2 again, the display device includes a display panel 100 and a display driving chip 200 .

The display panel 100 includes a pixel circuit 1, and the pixel circuit 1 includes a driving transistor M0 and a data writing transistor M1, wherein the gate of the data writing transistor M1 is electrically connected to the first scan signal line Scan1, and the gate of the data writing transistor M1 is electrically connected. The first pole is electrically connected to the data line Data, the second pole of the data writing transistor M1 is electrically connected to the driving transistor M0, and the first scan signal line Scan1 is used to provide the first enable voltage V to the gate of the data writing transistor M1 _GL and the first disable voltage V _GH .

The display driver chip 200 is electrically connected to the data line Data for providing a voltage lower than the first disabling voltage _VGH to the data line Data in the first stage T1, and providing the data voltage V _Data to the data line Data in the display stage T2. A stage T1 precedes and/or follows the display stage T2.

In the first stage T1, the first scan signal line Scan1 performs normal line-by-line refresh for the pixel circuits 1 in the first row to the last row. When the pixel circuit 1 is not refreshed by the first scan signal line Scan1, the data in the pixel circuit 1 The gate of the write transistor M1 receives the first disable voltage V _GH . In the embodiment of the present invention, by providing a voltage lower than the first disable voltage V _GH to the data line Data during at least a part of the time period of the first stage T1, it can be Make the gate-source voltage Vgs1 of the data writing transistor M1 greater than 0, making it much larger than the threshold voltage of the data writing transistor M1, at this time, the data writing transistor M1 can be controlled to be in a completely off state, effectively cutting off the data line Data and the light-emitting element The connection path between 2 prevents the voltage on the data line Data from leaking to the light-emitting element 2 . Since the time when the pixel circuit 1 is not refreshed by the first scan signal line Scan1 is much longer than the time when the pixel circuit 1 is refreshed by the first scan signal line Scan1 within one frame, the embodiment of the present invention can effectively prevent the light-emitting element 2 from being powered on and off It emits light abnormally, thereby effectively improving the screen splash phenomenon during power-on and power-off.

Further, referring to FIG. 1 and FIG. 2 again, the pixel circuit 1 further includes a first light-emitting control transistor M3, the gate of the first light-emitting control transistor M3 is electrically connected to the light-emitting control signal line Emit, and the first light-emitting control transistor M3 is electrically connected to the first light-emitting control transistor M3. The pole is electrically connected to the power supply signal line PVDD, and the second pole of the first light-emitting control transistor M3 is electrically connected to the driving transistor M0.

The first stage T1 includes a non-power supply period t1 and a power supply period t2, and the power supply period t2 is located between the non-power supply period t1 and the display stage T2. The display device further includes a power driver chip 300 for not supplying the power supply voltage to the power signal line PVDD during the non-power supply period t1 of the first stage T1, and supplying the power supply voltage V _PVDD to the power supply signal line PVDD during the power supply period t2.

Taking the first stage T1 as the power-on stage as an example, when the display panel 100 is powered on, the display panel 100 first enters the non-power supply period t1. The interval between stages T2 is a certain period of time, so the screen splash phenomenon is more easily detected by human eyes. Therefore, by causing the power driver chip 300 not to supply power to the power supply signal line PVDD during the non-power supply period t1, the pixel circuit 1 cannot receive the power supply voltage V _PVDD , thereby preventing the light-emitting element 2 from emitting abnormally during the non-power supply period t1 to a greater extent.

In addition, it should be noted that, in the embodiment of the present invention, the data writing transistor M1 can be controlled to be turned off when the data writing transistor M1 is not refreshed, and the second light emitting control transistor M1 can be controlled to be turned off when the data writing transistor M1 is refreshed, so as to The connection path between the data writing transistor M1 and the light emitting element 2 is cut off, so even if the power driver chip 300 normally supplies power to the power signal line PVDD during the power supply period t2, it can still prevent the light emitting element 2 from abnormally emitting light during the power supply period t2.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the present invention. within the scope of protection.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. scope.

Claims (21)

1. A driving method of a display panel is characterized in that,

the display panel comprises a pixel circuit, wherein the pixel circuit comprises a driving transistor and a data writing transistor, the grid electrode of the data writing transistor is electrically connected with a first scanning signal line, the first pole of the data writing transistor is electrically connected with a data line, the second pole of the data writing transistor is electrically connected with the driving transistor, and the first scanning signal line is used for providing a first enabling voltage and a first non-enabling voltage for the grid electrode of the data writing transistor;

the driving process of the display panel comprises a first phase and a display phase, wherein the first phase is positioned before and/or after the display phase;

the driving method includes: and in at least part of the first stage, the display driving chip provides a voltage smaller than the first non-enabling voltage to the data line.

2. The driving method according to claim 1,

the pixel circuit further includes a first light emission control transistor having a gate electrically connected to a light emission control signal line, a first pole electrically connected to a power signal line, and a second pole electrically connected to the driving transistor;

the first phase comprises a non-power supply period and a power supply period, wherein the power supply period is positioned between the non-power supply period and the display phase;

the driving method further includes: in the non-power supply period, the power supply driver chip does not supply the power supply voltage to the power supply signal line, and in the power supply period, the power supply driver chip supplies the power supply voltage to the power supply signal line.

3. The driving method according to claim 2,

in the first stage, the process of providing the voltage to the data line by the display driving chip comprises the following steps: in the power supply period, the display driving chip supplies a black state voltage to the data line.

4. The driving method according to claim 2,

in the first stage, the process of providing the voltage to the data line by the display driving chip further includes: in the non-power supply period, the display driving chip supplies a constant voltage to the data line.

5. The driving method according to claim 4,

the voltage difference between the constant voltage and the first non-enabling voltage is delta V, and the delta V is larger than or equal to 1V.

6. The driving method according to claim 2,

in the first stage, the process of providing the voltage to the data line by the display driving chip further includes: in the non-power supply period, the display driving chip provides a voltage less than or equal to a black state voltage to the data line.

7. The driving method according to claim 6,

the non-power supply period comprises x sub-periods, the voltage supplied to the data line in the ith sub-period is smaller than the voltage supplied to the data line in the (i + 1) th sub-period, x is a positive integer greater than or equal to 2, and i is greater than or equal to 1 and is less than or equal to x-1.

8. The driving method according to claim 7,

the duration of the sub-period is t0,

where k is a positive integer greater than or equal to 1, and f1 is a frequency of the first scan signal output by the first scan signal line in the display phase.

9. The driving method according to claim 7,

the voltage supplied to the data line is less than 2.5V in the 1 st sub-period, or the ground voltage is supplied to the data line in the 1 st sub-period.

10. The driving method according to claim 3,

the display panel has at least two display modes, and when the display panel executes different display modes in the display stage, the first non-enable voltage, the power supply voltage and the black state voltage corresponding to the first stage are equal.

11. The driving method according to claim 3,

the first phase is located before the display phase, and the display mode executed by the display panel after the first phase is finished is the first display mode, or the display mode executed by the display panel before the display panel enters the first phase is the first display mode after the first phase is located after the display phase;

the first display mode is a normal mode, and the first non-enabling voltage corresponding to the first phase is V _GH1 The power supply voltage is V _PVDD1 The black state voltage is V _GMP1 ；

The first display mode is a highlight mode, and the first non-enabling voltage corresponding to the first stage is V _GH2 The power supply voltage is V _PVDD2 The black state voltage is V _GMP2 Wherein V is _GH2 ＞V _GH1 ，V _PVDD2 ＞V _PVDD1 ，V _GMP2 ＞V _GMP1 And V is _GH2 -V _GH1 ≥V _GMP2 -V _GMP1 ≥V _PVDD2 -V _PVDD1 ；

The first display mode is a normal display mode, and the first non-enable voltage corresponding to the first stage is V _GH3 The power supply voltage is V _PVDD3 The black state voltage is V _GMP3 Wherein, V _GH1 ＜V _GH3 ＜V _GH2 ，V _PVDD1 ＜V _PVDD3 ＜V _PVDD2 ，V _GMP1 ＜V _GMP3 ＜V _GMP2 And V is _GH3 -V _GH1 ≥V _GMP3 -V _GMP1 ≥V _PVDD3 -V _PVDD1 Or, alternatively, V _GH3 ＜V _GH1 ，V _PVDD3 ＜V _PVDD1 ，V _GMP3 ＜V _GMP1 And V is _GH1 -V _GH3 ≤V _GMP1 -V _GMP3 ≤V _PVDD1 -V _PVDD3 。

12. The driving method according to claim 2,

the duration of the non-powered period is t1,

the duration of the power supply period is t2,

wherein f1 is the frequency of the first scanning signal outputted by the first scanning signal line in the display phase.

13. The driving method according to claim 12,

the first scanning signal output by the first scanning signal line in the display phase has a plurality of frequencies, and f1 is the maximum value of the frequencies of the first scanning signal.

14. The driving method according to claim 2,

the duration of the non-powered period is t1,

the duration of the power supply period is t2,

m and n are each an integer greater than or equal to 0;

wherein f1 is the frequency of the first scanning signal outputted by the first scanning signal line in the display phase, and f2 is the frequency of the light emission control signal outputted by the light emission control signal line in the display phase.

15. The driving method according to claim 2,

the duration of the non-power supply period is less than the duration of the power supply period.

16. The driving method according to claim 1,

the pixel circuit comprises a second light-emitting control transistor, wherein the grid electrode of the second light-emitting control transistor is electrically connected with a light-emitting control signal line, the first pole of the second light-emitting control transistor is electrically connected with the driving transistor, the second pole of the second light-emitting control transistor is electrically connected with a light-emitting element, and the light-emitting control signal line is used for providing light-emitting enabling voltage and light-emitting non-enabling voltage for the grid electrode of the second light-emitting control transistor;

the display panel further comprises a plurality of cascade-connected emission shift circuits, the emission shift circuits are electrically connected with the light-emitting control signal lines, the emission shift circuits comprise first emission shift circuits, and the first emission shift circuits are also electrically connected with emission frame starting signal lines;

the first emission shift circuit includes a first control transistor electrically connected between the emission frame start signal line and a gate of the first output transistor, a first pole of the first output transistor being electrically connected to a first fixed potential signal line, a second pole of the first output transistor being electrically connected to the emission control signal line, wherein the first fixed potential signal line is used to provide the emission enable voltage;

the driving method further includes: in the first stage, the display driving chip supplies the non-enable voltage of the first output transistor to the emission frame start signal line.

17. The driving method according to claim 16,

the emission shift circuit further comprises a protection transistor, wherein the grid electrode of the protection transistor is electrically connected with a control signal line, the first pole of the protection transistor is electrically connected with a second fixed potential signal line, the second pole of the protection transistor is electrically connected with the grid electrode of the first output transistor, and the control signal line is used for providing a second enabling voltage and a second non-enabling voltage for the grid electrode of the protection transistor;

the driving method of the display panel includes: in the first stage, the display driving chip provides the second non-enabling voltage to the control signal line.

18. The driving method according to claim 1,

the display panel also comprises a plurality of first scanning shift circuits which are arranged in a cascade mode, and the first scanning shift circuits are respectively and electrically connected with the first scanning clock signal line A, the first scanning clock signal line B and the first scanning signal line; the first scanning shift circuit comprises a first scanning shift circuit, and the first scanning shift circuit is also electrically connected with a first scanning frame starting signal line;

the driving method further includes: in the first stage, the display driving chip provides pulse signals to the first scanning clock signal line a, the first scanning clock signal line b and the first scanning frame start signal line.

19. The driving method according to claim 1,

the pixel circuit comprises a regulating transistor, wherein the grid electrode of the regulating transistor is electrically connected with a second scanning signal line, the first pole of the regulating transistor is electrically connected with the regulating signal line, and the second pole of the regulating transistor is electrically connected with the driving transistor;

the display panel also comprises a plurality of second scanning shift circuits which are arranged in a cascade mode, and the second scanning shift circuits are respectively electrically connected with a second scanning clock signal line, a second scanning clock signal line and the second scanning signal line; the second scanning shift circuit comprises a second scanning shift circuit, and the second scanning shift circuit is also electrically connected with a second scanning frame starting signal line;

the driving method further includes: in the first stage, the display driving chip provides pulse signals to the second scanning clock signal line, the second scanning clock signal line and the second scanning frame starting signal line respectively.

20. A display device, comprising:

a display panel including a pixel circuit including a driving transistor and a data writing transistor, wherein a gate of the data writing transistor is electrically connected to a first scan signal line, a first pole of the data writing transistor is electrically connected to a data line, a second pole of the data writing transistor is electrically connected to the driving transistor, and the first scan signal line is used to supply a first enable voltage and a first non-enable voltage to the gate of the data writing transistor;

and the display driving chip is electrically connected with the data line and used for providing a voltage smaller than the first non-enabling voltage to the data line in a first stage and providing a data voltage to the data line in a display stage, and the first stage is positioned before and/or after the display stage.

21. The display device according to claim 20,

the pixel circuit further includes a first light emission control transistor having a gate electrically connected to a light emission control signal line, a first pole electrically connected to a power signal line, and a second pole electrically connected to the driving transistor;

the first phase comprises a non-power supply period and a power supply period, wherein the power supply period is positioned between the non-power supply period and the display phase;

the display device further includes a power supply driver chip for supplying no power supply voltage to the power supply signal line in a non-power supply period of the first stage and supplying the power supply voltage to the power supply signal line in the power supply period.

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